4199 lines
117 KiB
YAML
4199 lines
117 KiB
YAML
block/RCC:
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description: Reset and clock controller
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items:
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- name: CR
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description: RCC clock control register
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byte_offset: 0
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fieldset: CR
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- name: HSICFGR
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description: RCC HSI calibration register
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byte_offset: 16
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fieldset: HSICFGR
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- name: CRRCR
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description: RCC clock recovery RC register
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byte_offset: 20
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fieldset: CRRCR
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- name: CSICFGR
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description: RCC CSI calibration register
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byte_offset: 24
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fieldset: CSICFGR
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- name: CFGR
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description: RCC clock configuration register
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byte_offset: 28
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fieldset: CFGR
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- name: CFGR2
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description: RCC CPU domain clock configuration register 2
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byte_offset: 32
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fieldset: CFGR2
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- name: PLLCFGR
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description: RCC PLL clock source selection register
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array:
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len: 3
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stride: 4
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byte_offset: 40
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fieldset: PLLCFGR
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- name: PLLDIVR
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description: RCC PLL1 dividers register
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array:
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len: 3
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stride: 8
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byte_offset: 52
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fieldset: PLLDIVR
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- name: PLLFRACR
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description: RCC PLL1 fractional divider register
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array:
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len: 3
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stride: 8
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byte_offset: 56
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fieldset: PLLFRACR
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- name: CIER
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description: RCC clock source interrupt enable register
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byte_offset: 80
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fieldset: CIER
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- name: CIFR
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description: RCC clock source interrupt flag register
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byte_offset: 84
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fieldset: CIFR
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- name: CICR
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description: RCC clock source interrupt clear register
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byte_offset: 88
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fieldset: CICR
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- name: AHB1RSTR
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description: RCC AHB1 reset register
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byte_offset: 96
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fieldset: AHB1RSTR
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- name: AHB2RSTR
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description: RCC AHB2 peripheral reset register
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byte_offset: 100
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fieldset: AHB2RSTR
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- name: AHB4RSTR
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description: RCC AHB4 peripheral reset register
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byte_offset: 108
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fieldset: AHB4RSTR
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- name: APB1LRSTR
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description: RCC APB1 peripheral low reset register
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byte_offset: 116
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fieldset: APB1LRSTR
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- name: APB1HRSTR
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description: RCC APB1 peripheral high reset register
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byte_offset: 120
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fieldset: APB1HRSTR
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- name: APB2RSTR
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description: RCC APB2 peripheral reset register
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byte_offset: 124
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fieldset: APB2RSTR
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- name: APB3RSTR
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description: RCC APB3 peripheral reset register
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byte_offset: 128
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fieldset: APB3RSTR
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- name: AHB1ENR
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description: RCC AHB1 peripherals clock register
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byte_offset: 136
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fieldset: AHB1ENR
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- name: AHB2ENR
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description: RCC AHB2 peripheral clock register
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byte_offset: 140
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fieldset: AHB2ENR
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- name: AHB4ENR
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description: RCC AHB4 peripheral clock register
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byte_offset: 148
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fieldset: AHB4ENR
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- name: APB1LENR
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description: RCC APB1 peripheral clock register
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byte_offset: 156
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fieldset: APB1LENR
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- name: APB1HENR
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description: RCC APB1 peripheral clock register
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byte_offset: 160
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fieldset: APB1HENR
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- name: APB2ENR
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description: RCC APB2 peripheral clock register
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byte_offset: 164
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fieldset: APB2ENR
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- name: APB3ENR
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description: RCC APB3 peripheral clock register
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byte_offset: 168
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fieldset: APB3ENR
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- name: AHB1LPENR
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description: RCC AHB1 sleep clock register
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byte_offset: 176
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fieldset: AHB1LPENR
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- name: AHB2LPENR
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description: RCC AHB2 sleep clock register
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byte_offset: 180
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fieldset: AHB2LPENR
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- name: AHB4LPENR
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description: RCC AHB4 sleep clock register
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byte_offset: 188
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fieldset: AHB4LPENR
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- name: APB1LLPENR
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description: RCC APB1 sleep clock register
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byte_offset: 196
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fieldset: APB1LLPENR
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- name: APB1HLPENR
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description: RCC APB1 sleep clock register
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byte_offset: 200
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fieldset: APB1HLPENR
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- name: APB2LPENR
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description: RCC APB2 sleep clock register
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byte_offset: 204
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fieldset: APB2LPENR
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- name: APB3LPENR
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description: RCC APB3 sleep clock register
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byte_offset: 208
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fieldset: APB3LPENR
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- name: CCIPR1
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description: RCC kernel clock configuration register
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byte_offset: 216
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fieldset: CCIPR1
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- name: CCIPR2
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description: RCC kernel clock configuration register
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byte_offset: 220
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fieldset: CCIPR2
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- name: CCIPR3
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description: RCC kernel clock configuration register
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byte_offset: 224
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fieldset: CCIPR3
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- name: CCIPR4
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description: RCC kernel clock configuration register
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byte_offset: 228
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fieldset: CCIPR4
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- name: CCIPR5
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description: RCC kernel clock configuration register
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byte_offset: 232
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fieldset: CCIPR5
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- name: BDCR
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description: RCC Backup domain control register
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byte_offset: 240
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fieldset: BDCR
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- name: RSR
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description: RCC reset status register
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byte_offset: 244
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fieldset: RSR
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- name: SECCFGR
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description: RCC secure configuration register
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byte_offset: 272
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fieldset: SECCFGR
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- name: PRIVCFGR
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description: RCC privilege configuration register
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byte_offset: 276
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fieldset: PRIVCFGR
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fieldset/AHB1ENR:
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description: RCC AHB1 peripherals clock register
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fields:
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- name: GPDMA1EN
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description: "GPDMA1 clock enable\r Set and reset by software."
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bit_offset: 0
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bit_size: 1
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- name: GPDMA2EN
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description: "GPDMA2 clock enable\r Set and reset by software."
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bit_offset: 1
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bit_size: 1
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- name: FLITFEN
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description: "Flash interface clock enable\r Set and reset by software."
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bit_offset: 8
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bit_size: 1
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- name: CRCEN
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description: "CRC clock enable\r Set and reset by software."
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bit_offset: 12
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bit_size: 1
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- name: CORDICEN
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description: "CORDIC clock enable\r Set and reset by software."
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bit_offset: 14
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bit_size: 1
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- name: FMACEN
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description: "FMAC clock enable\r Set and reset by software."
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bit_offset: 15
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bit_size: 1
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- name: RAMCFGEN
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description: "RAMCFG clock enable\r Set and reset by software."
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bit_offset: 17
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bit_size: 1
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- name: ETHEN
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description: "ETH clock enable\r Set and reset by software"
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bit_offset: 19
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bit_size: 1
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- name: ETHTXEN
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description: "ETHTX clock enable\r Set and reset by software"
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bit_offset: 20
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bit_size: 1
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- name: ETHRXEN
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description: "ETHRX clock enable\r Set and reset by software"
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bit_offset: 21
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bit_size: 1
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- name: TZSC1EN
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description: "TZSC1 clock enable\r Set and reset by software"
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bit_offset: 24
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bit_size: 1
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- name: BKPRAMEN
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description: "BKPRAM clock enable\r Set and reset by software"
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bit_offset: 28
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bit_size: 1
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- name: DCACHEEN
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description: "DCACHE clock enable\r Set and reset by software"
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bit_offset: 30
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bit_size: 1
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- name: SRAM1EN
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description: "SRAM1 clock enable\r Set and reset by software."
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bit_offset: 31
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bit_size: 1
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fieldset/AHB1LPENR:
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description: RCC AHB1 sleep clock register
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fields:
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- name: GPDMA1LPEN
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description: "GPDMA1 clock enable during sleep mode\r Set and reset by software."
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bit_offset: 0
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bit_size: 1
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- name: GPDMA2LPEN
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description: "GPDMA2 clock enable during sleep mode\r Set and reset by software."
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bit_offset: 1
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bit_size: 1
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- name: FLITFLPEN
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description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software."
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bit_offset: 8
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bit_size: 1
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- name: CRCLPEN
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description: "CRC clock enable during sleep mode\r Set and reset by software."
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bit_offset: 12
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bit_size: 1
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- name: CORDICLPEN
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description: "CORDIC clock enable during sleep mode\r Set and reset by software."
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bit_offset: 14
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bit_size: 1
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- name: FMACLPEN
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description: "FMAC clock enable during sleep mode\r Set and reset by software."
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bit_offset: 15
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bit_size: 1
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- name: RAMCFGLPEN
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description: "RAMCFG clock enable during sleep mode\r Set and reset by software."
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bit_offset: 17
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bit_size: 1
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- name: ETHLPEN
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description: "ETH clock enable during Sleep mode\r Set and reset by software"
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bit_offset: 19
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bit_size: 1
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- name: ETHTXLPEN
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description: "ETHTX clock enable during sleep mode\r Set and reset by software"
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bit_offset: 20
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bit_size: 1
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- name: ETHRXLPEN
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description: "ETHRX clock enable during sleep mode\r Set and reset by software"
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bit_offset: 21
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bit_size: 1
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- name: TZSC1LPEN
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description: "TZSC1 clock enable during sleep mode\r Set and reset by software"
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bit_offset: 24
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bit_size: 1
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- name: BKPRAMLPEN
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description: "BKPRAM clock enable during sleep mode\r Set and reset by software"
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bit_offset: 28
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bit_size: 1
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- name: ICACHELPEN
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description: "ICACHE clock enable during sleep mode\r Set and reset by software"
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bit_offset: 29
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bit_size: 1
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- name: DCACHELPEN
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description: "DCACHE clock enable during sleep mode\r Set and reset by software"
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bit_offset: 30
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bit_size: 1
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- name: SRAM1LPEN
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description: "SRAM1 clock enable during sleep mode\r Set and reset by software"
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bit_offset: 31
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bit_size: 1
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fieldset/AHB1RSTR:
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description: RCC AHB1 reset register
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fields:
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- name: GPDMA1RST
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description: "GPDMA1 block reset\r Set and reset by software."
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bit_offset: 0
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bit_size: 1
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- name: GPDMA2RST
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description: "GPDMA2 block reset\r Set and reset by software."
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bit_offset: 1
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bit_size: 1
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- name: CRCRST
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description: CRC block reset Set and reset by software.
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bit_offset: 12
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bit_size: 1
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- name: CORDICRST
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description: "CORDIC block reset\r Set and reset by software."
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bit_offset: 14
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bit_size: 1
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- name: FMACRST
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description: "FMAC block reset\r Set and reset by software."
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bit_offset: 15
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bit_size: 1
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- name: RAMCFGRST
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description: "RAMCFG block reset\r Set and reset by software."
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bit_offset: 17
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bit_size: 1
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- name: ETHRST
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description: "ETHRST block reset\r Set and reset by software"
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bit_offset: 19
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bit_size: 1
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- name: TZSC1RST
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description: "TZSC1 reset\r Set and reset by software"
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bit_offset: 24
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bit_size: 1
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fieldset/AHB2ENR:
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description: RCC AHB2 peripheral clock register
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fields:
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- name: GPIOAEN
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description: "GPIOA clock enable\r Set and reset by software."
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: "GPIOB clock enable\r Set and reset by software."
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: "GPIOC clock enable\r Set and reset by software."
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bit_offset: 2
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bit_size: 1
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- name: GPIODEN
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description: "GPIOD clock enable\r Set and reset by software."
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bit_offset: 3
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bit_size: 1
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- name: GPIOEEN
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description: "GPIOE clock enable\r Set and reset by software."
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bit_offset: 4
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bit_size: 1
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- name: GPIOFEN
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description: "GPIOF clock enable\r Set and reset by software."
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bit_offset: 5
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bit_size: 1
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- name: GPIOGEN
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description: "GPIOG clock enable\r Set and reset by software."
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bit_offset: 6
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bit_size: 1
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- name: GPIOHEN
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description: "GPIOH clock enable\r Set and reset by software."
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bit_offset: 7
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bit_size: 1
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- name: GPIOIEN
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description: "GPIOI clock enable\r Set and reset by software."
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bit_offset: 8
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bit_size: 1
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- name: ADC12EN
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description: "ADC1 and 2 peripherals clock enabled\r Set and reset by software."
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bit_offset: 10
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bit_size: 1
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- name: DAC1EN
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description: "DAC clock enable\r Set and reset by software."
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bit_offset: 11
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bit_size: 1
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- name: DCMI_PSSIEN
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description: "digital camera interface clock enable (DCMI or PSSI depending which interface is active)\r Set and reset by software."
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bit_offset: 12
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bit_size: 1
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- name: AESEN
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description: "AES clock enable\r Set and reset by software."
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bit_offset: 16
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bit_size: 1
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- name: HASHEN
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description: "HASH clock enable\r Set and reset by software."
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bit_offset: 17
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bit_size: 1
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- name: RNGEN
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description: "RNG clock enable\r Set and reset by software."
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bit_offset: 18
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bit_size: 1
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- name: PKAEN
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description: "PKA clock enable\r Set and reset by software."
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bit_offset: 19
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bit_size: 1
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- name: SAESEN
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description: "SAES clock enable\r Set and reset by software."
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bit_offset: 20
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bit_size: 1
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- name: SRAM3EN
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description: "SRAM3 clock enable\r Set and reset by software."
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bit_offset: 30
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bit_size: 1
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- name: SRAM2EN
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description: "SRAM2 clock enable\r Set and reset by software."
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bit_offset: 31
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bit_size: 1
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fieldset/AHB2LPENR:
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description: RCC AHB2 sleep clock register
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fields:
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- name: GPIOALPEN
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description: "GPIOA clock enable during sleep mode\r Set and reset by software."
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bit_offset: 0
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bit_size: 1
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- name: GPIOBLPEN
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description: "GPIOB clock enable during sleep mode\r Set and reset by software."
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bit_offset: 1
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bit_size: 1
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- name: GPIOCLPEN
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description: "GPIOC clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 2
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bit_size: 1
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- name: GPIODLPEN
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description: "GPIOD clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 3
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bit_size: 1
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- name: GPIOELPEN
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description: "GPIOE clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 4
|
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bit_size: 1
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- name: GPIOFLPEN
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description: "GPIOF clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 5
|
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bit_size: 1
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- name: GPIOGLPEN
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description: "GPIOG clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 6
|
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bit_size: 1
|
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- name: GPIOHLPEN
|
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description: "GPIOH clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 7
|
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bit_size: 1
|
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- name: GPIOILPEN
|
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description: "GPIOI clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 8
|
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bit_size: 1
|
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- name: ADC12LPEN
|
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description: "ADC1 and 2 peripherals clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 10
|
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bit_size: 1
|
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- name: DAC1LPEN
|
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description: "DAC clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 11
|
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bit_size: 1
|
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- name: DCMI_PSSILPEN
|
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description: "digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active)\r Set and reset by software."
|
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bit_offset: 12
|
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bit_size: 1
|
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- name: AESLPEN
|
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description: "AES clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 16
|
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bit_size: 1
|
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- name: HASHLPEN
|
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description: "HASH clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 17
|
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bit_size: 1
|
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- name: RNGLPEN
|
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description: "RNG clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 18
|
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bit_size: 1
|
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- name: PKALPEN
|
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description: "PKA clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 19
|
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bit_size: 1
|
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- name: SAESLPEN
|
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description: "SAES clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 20
|
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bit_size: 1
|
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- name: SRAM2LPEN
|
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description: "SRAM2 clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 30
|
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bit_size: 1
|
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- name: SRAM3LPEN
|
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description: "SRAM3 clock enable during sleep mode\r Set and reset by software."
|
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bit_offset: 31
|
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bit_size: 1
|
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fieldset/AHB2RSTR:
|
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description: RCC AHB2 peripheral reset register
|
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fields:
|
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- name: GPIOARST
|
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description: "GPIOA block reset\r Set and reset by software."
|
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bit_offset: 0
|
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bit_size: 1
|
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- name: GPIOBRST
|
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description: "GPIOB block reset\r Set and reset by software."
|
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bit_offset: 1
|
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bit_size: 1
|
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- name: GPIOCRST
|
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description: "GPIOC block reset\r Set and reset by software."
|
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bit_offset: 2
|
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bit_size: 1
|
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- name: GPIODRST
|
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description: "GPIOD block reset\r Set and reset by software."
|
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bit_offset: 3
|
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bit_size: 1
|
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- name: GPIOERST
|
|
description: "GPIOE block reset\r Set and reset by software."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: GPIOFRST
|
|
description: "GPIOF block reset\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: GPIOGRST
|
|
description: "GPIOG block reset\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: GPIOHRST
|
|
description: "GPIOH block reset\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: GPIOIRST
|
|
description: "GPIOI block reset\r Set and reset by software."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: ADC12RST
|
|
description: "ADC1 and 2 blocks reset\r Set and reset by software."
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: DAC1RST
|
|
description: "DAC block reset\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: DCMI_PSSIRST
|
|
description: "digital camera interface block reset (DCMI or PSSI depending which interface is active)\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: AESRST
|
|
description: "AES block reset\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HASHRST
|
|
description: "HASH block reset\r Set and reset by software."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: RNGRST
|
|
description: "RNG block reset\r Set and reset by software."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: PKARST
|
|
description: "PKA block reset\r Set and reset by software."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: SAESRST
|
|
description: "SAES block reset\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/AHB4ENR:
|
|
description: RCC AHB4 peripheral clock register
|
|
fields:
|
|
- name: OTFDEC1EN
|
|
description: "OTFDEC1 clock enable\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: SDMMC1EN
|
|
description: SDMMC1 and SDMMC1 delay peripheral clock enable reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SDMMC2EN
|
|
description: "SDMMC2 and SDMMC2 delay peripheral clock enabled\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: FMCEN
|
|
description: "FMC clock enable\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: OCTOSPI1EN
|
|
description: "OCTOSPI1 clock enable\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/AHB4LPENR:
|
|
description: RCC AHB4 sleep clock register
|
|
fields:
|
|
- name: OTFDEC1LPEN
|
|
description: "OTFDEC1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: SDMMC1LPEN
|
|
description: "SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode\r Set and reset by software"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SDMMC2LPEN
|
|
description: "SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: FMCLPEN
|
|
description: "FMC clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: OCTOSPI1LPEN
|
|
description: "OCTOSPI1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/AHB4RSTR:
|
|
description: RCC AHB4 peripheral reset register
|
|
fields:
|
|
- name: OTFDEC1RST
|
|
description: "OTFDEC1 block reset\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: SDMMC1RST
|
|
description: "SDMMC1 and SDMMC1 delay blocks reset\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SDMMC2RST
|
|
description: "SDMMC2 and SDMMC2 delay blocks reset\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: FMCRST
|
|
description: "FMC block reset\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: OCTOSPI1RST
|
|
description: "OCTOSPI1 block reset\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/APB1HENR:
|
|
description: RCC APB1 peripheral clock register
|
|
fields:
|
|
- name: UART9EN
|
|
description: "UART9 clock enable\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UART12EN
|
|
description: "UART12 clock enable\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DTSEN
|
|
description: "DTS clock enable\r Set and reset by software."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LPTIM2EN
|
|
description: "LPTIM2 clock enable\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: FDCAN12EN
|
|
description: "FDCAN1 and FDCAN2 peripheral clock enable\r Set and reset by software."
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: UCPDEN
|
|
description: "UCPD clock enable\r Set and reset by software."
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/APB1HLPENR:
|
|
description: RCC APB1 sleep clock register
|
|
fields:
|
|
- name: UART9LPEN
|
|
description: "UART9 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UART12LPEN
|
|
description: "UART12 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DTSLPEN
|
|
description: "DTS clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LPTIM2LPEN
|
|
description: "LPTIM2 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: FDCAN12LPEN
|
|
description: "FDCAN1 and FDCAN2 peripheral clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: UCPDLPEN
|
|
description: "UCPD clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/APB1HRSTR:
|
|
description: RCC APB1 peripheral high reset register
|
|
fields:
|
|
- name: UART9RST
|
|
description: "UART9 block reset\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: UART12RST
|
|
description: "UART12 block reset\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: DTSRST
|
|
description: "DTS block reset\r Set and reset by software."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LPTIM2RST
|
|
description: "LPTIM2 block reset\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: FDCAN12RST
|
|
description: "FDCAN1 and FDCAN2 blocks reset\r Set and reset by software."
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: UCPDRST
|
|
description: "UCPD block reset\r Set and reset by software."
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/APB1LENR:
|
|
description: RCC APB1 peripheral clock register
|
|
fields:
|
|
- name: TIM2EN
|
|
description: "TIM2 clock enable\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3EN
|
|
description: "TIM3 clock enable\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4EN
|
|
description: "TIM4 clock enable\r Set and reset by software."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5EN
|
|
description: "TIM5 clock enable\r Set and reset by software."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6EN
|
|
description: "TIM6 clock enable\r Set and reset by software."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7EN
|
|
description: "TIM7 clock enable\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TIM12EN
|
|
description: "TIM12 clock enable\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TIM13EN
|
|
description: "TIM13 clock enable\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: TIM14EN
|
|
description: "TIM14 clock enable\r Set and reset by software."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: WWDGEN
|
|
description: "WWDG clock enable\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2EN
|
|
description: "SPI2 clock enable\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3EN
|
|
description: "SPI3 clock enable\r Set and reset by software."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: USART2EN
|
|
description: "USART2 clock enable\r Set and reset by software."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3EN
|
|
description: "USART3 clock enable\r Set and reset by software."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4EN
|
|
description: "UART4 clock enable\r Set and reset by software."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5EN
|
|
description: "UART5 clock enable\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1EN
|
|
description: "I2C1 clock enable\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2EN
|
|
description: "I2C2 clock enable\r Set and reset by software."
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I3C1EN
|
|
description: "I3C1 clock enable\r Set and reset by software."
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSEN
|
|
description: "CRS clock enable\r Set and reset by software."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USART6EN
|
|
description: "USART6 clock enable\r Set and reset by software."
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: USART10EN
|
|
description: "USART10 clock enable\r Set and reset by software."
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: USART11EN
|
|
description: USART11 clock enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: CECEN
|
|
description: "HDMI-CEC clock enable\r Set and reset by software."
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: UART7EN
|
|
description: "UART7 clock enable\r Set and reset by software."
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: UART8EN
|
|
description: "UART8 clock enable\r Set and reset by software."
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1LLPENR:
|
|
description: RCC APB1 sleep clock register
|
|
fields:
|
|
- name: TIM2LPEN
|
|
description: "TIM2 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3LPEN
|
|
description: "TIM3 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4LPEN
|
|
description: "TIM4 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5LPEN
|
|
description: "TIM5 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6LPEN
|
|
description: "TIM6 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7LPEN
|
|
description: "TIM7 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TIM12LPEN
|
|
description: "TIM12 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TIM13LPEN
|
|
description: "TIM13 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: TIM14LPEN
|
|
description: "TIM14 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: WWDGLPEN
|
|
description: "WWDG clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2LPEN
|
|
description: "SPI2 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3LPEN
|
|
description: "SPI3 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: USART2LPEN
|
|
description: "USART2 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3LPEN
|
|
description: "USART3 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4LPEN
|
|
description: "UART4 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5LPEN
|
|
description: "UART5 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1LPEN
|
|
description: "I2C1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2LPEN
|
|
description: "I2C2 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I3C1LPEN
|
|
description: "I3C1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSLPEN
|
|
description: "CRS clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USART6LPEN
|
|
description: "USART6 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: USART10LPEN
|
|
description: "USART10 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: USART11LPEN
|
|
description: "USART11 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: CECLPEN
|
|
description: "HDMI-CEC clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: UART7LPEN
|
|
description: "UART7 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: UART8LPEN
|
|
description: "UART8 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1LRSTR:
|
|
description: RCC APB1 peripheral low reset register
|
|
fields:
|
|
- name: TIM2RST
|
|
description: "TIM2 block reset\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3RST
|
|
description: "TIM3 block reset\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4RST
|
|
description: "TIM4 block reset\r Set and reset by software."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5RST
|
|
description: "TIM5 block reset\r Set and reset by software."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6RST
|
|
description: "TIM6 block reset\r Set and reset by software."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7RST
|
|
description: "TIM7 block reset\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: TIM12RST
|
|
description: "TIM12 block reset\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: TIM13RST
|
|
description: "TIM13 block reset t\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: TIM14RST
|
|
description: "TIM14 block reset\r Set and reset by software."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SPI2RST
|
|
description: "SPI2 block reset\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3RST
|
|
description: "SPI3 block reset\r Set and reset by software."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: USART2RST
|
|
description: "USART2 block reset\r Set and reset by software."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3RST
|
|
description: "USART3 block reset\r Set and reset by software."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4RST
|
|
description: "UART4 block reset\r Set and reset by software."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5RST
|
|
description: "UART5 block reset\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1RST
|
|
description: "I2C1 block reset\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2RST
|
|
description: "I2C2 block reset\r Set and reset by software."
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: I3C1RST
|
|
description: "I3C1 block reset\r Set and reset by software."
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CRSRST
|
|
description: "CRS block reset\r Set and reset by software."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: USART6RST
|
|
description: "USART6 block reset\r Set and reset by software."
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: USART10RST
|
|
description: "USART10 block reset\r Set and reset by software."
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: USART11RST
|
|
description: "USART11 block reset\r Set and reset by software."
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: CECRST
|
|
description: "HDMI-CEC block reset\r Set and reset by software."
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: UART7RST
|
|
description: "UART7 block reset\r Set and reset by software."
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: UART8RST
|
|
description: "UART8 block reset\r Set and reset by software."
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB2ENR:
|
|
description: RCC APB2 peripheral clock register
|
|
fields:
|
|
- name: TIM1EN
|
|
description: "TIM1 clock enable\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: "SPI1 clock enable\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TIM8EN
|
|
description: "TIM8 clock enable\r Set and reset by software."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: "USART1 clock enable\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM15EN
|
|
description: "TIM15 clock enable\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: "TIM16 clock enable\r Set and reset by software."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: "TIM17 clock enable\r Set and reset by software."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SPI4EN
|
|
description: "SPI4 clock enable\r Set and reset by software."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: SPI6EN
|
|
description: "SPI6 clock enable\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1EN
|
|
description: "SAI1 clock enable\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: SAI2EN
|
|
description: "SAI2 clock enable\r Set and cleared by software."
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: USBEN
|
|
description: "USB clock enable\r Set and reset by software."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
fieldset/APB2LPENR:
|
|
description: RCC APB2 sleep clock register
|
|
fields:
|
|
- name: TIM1LPEN
|
|
description: "TIM1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1LPEN
|
|
description: "SPI1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TIM8LPEN
|
|
description: "TIM8 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: USART1LPEN
|
|
description: "USART1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM15LPEN
|
|
description: "TIM15 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16LPEN
|
|
description: "TIM16 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17LPEN
|
|
description: "TIM17 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SPI4LPEN
|
|
description: "SPI4 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: SPI6LPEN
|
|
description: "SPI6 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1LPEN
|
|
description: "SAI1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: SAI2LPEN
|
|
description: "SAI2 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: USBLPEN
|
|
description: "USB clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
fieldset/APB2RSTR:
|
|
description: RCC APB2 peripheral reset register
|
|
fields:
|
|
- name: TIM1RST
|
|
description: "TIM1 block reset\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1RST
|
|
description: "SPI1 block reset\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TIM8RST
|
|
description: "TIM8 block reset\r Set and reset by software."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: USART1RST
|
|
description: "USART1 block reset\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: TIM15RST
|
|
description: "TIM15 block reset\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16RST
|
|
description: "TIM16 block reset\r Set and reset by software."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17RST
|
|
description: "TIM17 block reset\r Set and reset by software."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: SPI4RST
|
|
description: "SPI4 block reset\r Set and reset by software."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: SPI6RST
|
|
description: "SPI6 block reset\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1RST
|
|
description: "SAI1 block reset\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: SAI2RST
|
|
description: "SAI2 block reset\r Set and reset by software."
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: USBRST
|
|
description: "USB block reset\r Set and reset by software."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
fieldset/APB3ENR:
|
|
description: RCC APB3 peripheral clock register
|
|
fields:
|
|
- name: SBSEN
|
|
description: "SBS clock enable\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SPI5EN
|
|
description: "SPI5 clock enable\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPUART1EN
|
|
description: "LPUART1 clock enable\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: I2C3EN
|
|
description: "I2C3 clock enable\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: I2C4EN
|
|
description: "I2C4 clock enable\r Set and reset by software."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPTIM1EN
|
|
description: "LPTIM1 clock enable\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPTIM3EN
|
|
description: "LPTIM3 clock enable\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: LPTIM4EN
|
|
description: "LPTIM4 clock enable\r Set and reset by software."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: LPTIM5EN
|
|
description: "LPTIM5 clock enable\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: LPTIM6EN
|
|
description: "LPTIM6 clock enable\r Set and reset by software."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: VREFEN
|
|
description: "VREF clock enable\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: RTCAPBEN
|
|
description: "RTC APB interface clock enable\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB3LPENR:
|
|
description: RCC APB3 sleep clock register
|
|
fields:
|
|
- name: SBSLPEN
|
|
description: "SBS clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SPI5LPEN
|
|
description: "SPI5 clock enable during Slsleepeep mode\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPUART1LPEN
|
|
description: "LPUART1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: I2C3LPEN
|
|
description: "I2C3 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: I2C4LPEN
|
|
description: "I2C4 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPTIM1LPEN
|
|
description: "LPTIM1 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPTIM3LPEN
|
|
description: "LPTIM3 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: LPTIM4LPEN
|
|
description: "LPTIM4 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: LPTIM5LPEN
|
|
description: "LPTIM5 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: LPTIM6LPEN
|
|
description: "LPTIM6 clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: VREFLPEN
|
|
description: "VREF clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: RTCAPBLPEN
|
|
description: "RTC APB interface clock enable during sleep mode\r Set and reset by software."
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
fieldset/APB3RSTR:
|
|
description: RCC APB3 peripheral reset register
|
|
fields:
|
|
- name: SBSRST
|
|
description: "SBS block reset\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: SPI5RST
|
|
description: "SPI5 block reset\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LPUART1RST
|
|
description: "LPUART1 block reset\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: I2C3RST
|
|
description: "I2C3 block reset\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: I2C4RST
|
|
description: "I2C4 block reset\r Set and reset by software."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LPTIM1RST
|
|
description: "LPTIM1 block reset\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: LPTIM3RST
|
|
description: "LPTIM3 block reset\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: LPTIM4RST
|
|
description: "LPTIM4 block reset\r Set and reset by software."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: LPTIM5RST
|
|
description: "LPTIM5 block reset\r Set and reset by software."
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: LPTIM6RST
|
|
description: "LPTIM6 block reset\r Set and reset by software."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: VREFRST
|
|
description: "VREF block reset\r Set and reset by software."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: RCC Backup domain control register
|
|
fields:
|
|
- name: LSEON
|
|
description: "LSE oscillator enabled\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)."
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: LSEDRV
|
|
- name: LSECSSON
|
|
description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD
|
|
description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: LSEEXT
|
|
description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: LSEEXT
|
|
- name: RTCSEL
|
|
description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)."
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: RTCEN
|
|
description: "RTC clock enable\r Set and reset by software."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: VSWRST
|
|
description: "VSwitch domain software reset\r Set and reset by software."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSCOEN
|
|
description: "Low-speed clock output (LSCO) enable\r Set and cleared by software."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LSCOSEL
|
|
description: "Low-speed clock output selection\r Set and cleared by software."
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: LSCOSEL
|
|
- name: LSION
|
|
description: "LSI oscillator enable\r Set and cleared by software."
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0."
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
fieldset/CCIPR1:
|
|
description: RCC kernel clock configuration register
|
|
fields:
|
|
- name: USART1SEL
|
|
description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: USARTSEL
|
|
- name: USART2SEL
|
|
description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
enum: USARTSEL
|
|
- name: USART3SEL
|
|
description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 6
|
|
bit_size: 3
|
|
enum: USARTSEL
|
|
- name: UART4SEL
|
|
description: "UART4 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 9
|
|
bit_size: 3
|
|
enum: UARTSEL
|
|
- name: UART5SEL
|
|
description: "UART5 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
enum: UARTSEL
|
|
- name: USART6SEL
|
|
description: "USART6 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 15
|
|
bit_size: 3
|
|
enum: USARTSEL
|
|
- name: UART7SEL
|
|
description: "UART7 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 18
|
|
bit_size: 3
|
|
enum: UARTSEL
|
|
- name: UART8SEL
|
|
description: "UART8 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 21
|
|
bit_size: 3
|
|
enum: UARTSEL
|
|
- name: UART9SEL
|
|
description: "UART9 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
enum: UARTSEL
|
|
- name: USART10SEL
|
|
description: "USART10 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 27
|
|
bit_size: 3
|
|
enum: USARTSEL
|
|
- name: TIMICSEL
|
|
description: "TIM12, TIM15 and LPTIM2 input capture source selection\r Set and reset by software."
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: TIMICSEL
|
|
fieldset/CCIPR2:
|
|
description: RCC kernel clock configuration register
|
|
fields:
|
|
- name: USART11SEL
|
|
description: "USART11 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: USARTSEL
|
|
- name: USART12SEL
|
|
description: "USART12 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: USARTSEL
|
|
- name: LPTIM1SEL
|
|
description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: LPTIMSEL
|
|
- name: LPTIM2SEL
|
|
description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
enum: LPTIMSEL
|
|
- name: LPTIM3SEL
|
|
description: "LPTIM3 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 16
|
|
bit_size: 3
|
|
enum: LPTIMSEL
|
|
- name: LPTIM4SEL
|
|
description: "LPTIM4 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 20
|
|
bit_size: 3
|
|
enum: LPTIMSEL
|
|
- name: LPTIM5SEL
|
|
description: "LPTIM5 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
enum: LPTIMSEL
|
|
- name: LPTIM6SEL
|
|
description: "LPTIM6 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: LPTIMSEL
|
|
fieldset/CCIPR3:
|
|
description: RCC kernel clock configuration register
|
|
fields:
|
|
- name: SPI1SEL
|
|
description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: SPI1SEL
|
|
- name: SPI2SEL
|
|
description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
enum: SPI2SEL
|
|
- name: SPI3SEL
|
|
description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 6
|
|
bit_size: 3
|
|
enum: SPI3SEL
|
|
- name: SPI4SEL
|
|
description: "SPI4 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 9
|
|
bit_size: 3
|
|
enum: SPI4SEL
|
|
- name: SPI5SEL
|
|
description: "SPI5 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
enum: SPI5SEL
|
|
- name: SPI6SEL
|
|
description: "SPI6 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 15
|
|
bit_size: 3
|
|
enum: SPI6SEL
|
|
- name: LPUART1SEL
|
|
description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 24
|
|
bit_size: 3
|
|
enum: LPUARTSEL
|
|
fieldset/CCIPR4:
|
|
description: RCC kernel clock configuration register
|
|
fields:
|
|
- name: OCTOSPI1SEL
|
|
description: "OCTOSPI1 kernel clock source selection\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: OCTOSPISEL
|
|
- name: SYSTICKSEL
|
|
description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)."
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
enum: SYSTICKSEL
|
|
- name: USBSEL
|
|
description: USB kernel clock source selection
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: USBSEL
|
|
- name: SDMMC1SEL
|
|
description: SDMMC1 kernel clock source selection
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SDMMCSEL
|
|
- name: SDMMC2SEL
|
|
description: SDMMC2 kernel clock source selection
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SDMMCSEL
|
|
- name: I2C1SEL
|
|
description: I2C1 kernel clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
enum: ICSEL
|
|
- name: I2C2SEL
|
|
description: I2C2 kernel clock source selection
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
enum: ICSEL
|
|
- name: I2C3SEL
|
|
description: I2C3 kernel clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: ICSEL
|
|
- name: I2C4SEL
|
|
description: I2C4 kernel clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
enum: ICSEL
|
|
- name: I3C1SEL
|
|
description: I3C1 kernel clock source selection
|
|
bit_offset: 24
|
|
bit_size: 2
|
|
enum: ICSEL
|
|
fieldset/CCIPR5:
|
|
description: RCC kernel clock configuration register
|
|
fields:
|
|
- name: ADCDACSEL
|
|
description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: ADCDACSEL
|
|
- name: DACSEL
|
|
description: DAC hold clock
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: DACSEL
|
|
- name: RNGSEL
|
|
description: RNG kernel clock source selection
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: RNGSEL
|
|
- name: CECSEL
|
|
description: HSMI-CEC kernel clock source selection
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
enum: CECSEL
|
|
- name: FDCAN12SEL
|
|
description: FDCAN1 and FDCAN2 kernel clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: FDCANSEL
|
|
- name: SAI1SEL
|
|
description: "SAI1 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 16
|
|
bit_size: 3
|
|
enum: SAISEL
|
|
- name: SAI2SEL
|
|
description: "SAI2 kernel clock source selection\r others: reserved, the kernel clock is disabled"
|
|
bit_offset: 19
|
|
bit_size: 3
|
|
enum: SAISEL
|
|
- name: CKPERSEL
|
|
description: per_ck clock source selection
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
enum: CKPERSEL
|
|
fieldset/CFGR:
|
|
description: RCC clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
enum: SW
|
|
- name: SWS
|
|
description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved"
|
|
bit_offset: 3
|
|
bit_size: 3
|
|
enum: SW
|
|
- name: STOPWUCK
|
|
description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: STOPWUCK
|
|
- name: STOPKERWUCK
|
|
description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: STOPKERWUCK
|
|
- name: RTCPRE
|
|
description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..."
|
|
bit_offset: 8
|
|
bit_size: 6
|
|
- name: TIMPRE
|
|
description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains."
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: TIMPRE
|
|
- name: MCO1PRE
|
|
description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..."
|
|
bit_offset: 18
|
|
bit_size: 4
|
|
enum: MCOPRE
|
|
- name: MCO1SEL
|
|
description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved"
|
|
bit_offset: 22
|
|
bit_size: 3
|
|
enum: MCO1SEL
|
|
- name: MCO2PRE
|
|
description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..."
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: MCOPRE
|
|
- name: MCO2SEL
|
|
description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved"
|
|
bit_offset: 29
|
|
bit_size: 3
|
|
enum: MCO2SEL
|
|
fieldset/CFGR2:
|
|
description: RCC CPU domain clock configuration register 2
|
|
fields:
|
|
- name: HPRE
|
|
description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)"
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: PPRE1
|
|
description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)"
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PPRE2
|
|
description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1"
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PPRE3
|
|
description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1"
|
|
bit_offset: 12
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: AHB1DIS
|
|
description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits"
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: AHB2DIS
|
|
description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits"
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: AHB4DIS
|
|
description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits"
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: APB1DIS
|
|
description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits"
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: APB2DIS
|
|
description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits"
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: APB3DIS
|
|
description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits"
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
fieldset/CICR:
|
|
description: RCC clock source interrupt clear register
|
|
fields:
|
|
- name: LSIRDYC
|
|
description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CSIRDYC
|
|
description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HSI48RDYC
|
|
description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: HSECSSC
|
|
description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done."
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: RCC clock source interrupt enable register
|
|
fields:
|
|
- name: LSIRDYIE
|
|
description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CSIRDYIE
|
|
description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HSI48RDYIE
|
|
description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
fieldset/CIFR:
|
|
description: RCC clock source interrupt flag register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CSIRDYF
|
|
description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HSI48RDYF
|
|
description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: HSECSSF
|
|
description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure."
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: RCC clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: HSIDIV
|
|
description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored."
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: HSIDIV
|
|
- name: HSIDIVF
|
|
description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSION
|
|
description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: CSIRDY
|
|
description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)."
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: CSIKERON
|
|
description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION."
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSI48ON
|
|
description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: HSI48RDY
|
|
description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: HSECSSON
|
|
description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected."
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: HSEEXT
|
|
description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled."
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: HSEEXT
|
|
- name: PLLON
|
|
description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock."
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 2
|
|
- name: PLLRDY
|
|
description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked."
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 2
|
|
fieldset/CRRCR:
|
|
description: RCC clock recovery RC register
|
|
fields:
|
|
- name: HSI48CAL
|
|
description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only."
|
|
bit_offset: 0
|
|
bit_size: 10
|
|
fieldset/CSICFGR:
|
|
description: RCC CSI calibration register
|
|
fields:
|
|
- name: CSICAL
|
|
description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value."
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
- name: CSITRIM
|
|
description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20."
|
|
bit_offset: 16
|
|
bit_size: 6
|
|
fieldset/HSICFGR:
|
|
description: RCC HSI calibration register
|
|
fields:
|
|
- name: HSICAL
|
|
description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value."
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: HSITRIM
|
|
description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40."
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
fieldset/PLLCFGR:
|
|
description: RCC PLL clock source selection register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)."
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: PLLSRC
|
|
- name: PLLRGE
|
|
description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1."
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
enum: PLLRGE
|
|
- name: PLLFRACEN
|
|
description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLVCOSEL
|
|
description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: PLLVCOSEL
|
|
- name: DIVM
|
|
description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..."
|
|
bit_offset: 8
|
|
bit_size: 6
|
|
enum: PLLM
|
|
- name: PLLPEN
|
|
description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled."
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLQEN
|
|
description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PLLREN
|
|
description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
fieldset/PLLDIVR:
|
|
description: RCC PLL1 dividers register
|
|
fields:
|
|
- name: PLLN
|
|
description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved"
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
enum: PLLN
|
|
- name: PLLP
|
|
description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..."
|
|
bit_offset: 9
|
|
bit_size: 7
|
|
enum: PLLDIV
|
|
- name: PLLQ
|
|
description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
enum: PLLDIV
|
|
- name: PLLR
|
|
description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
enum: PLLDIV
|
|
fieldset/PLLFRACR:
|
|
description: RCC PLL1 fractional divider register
|
|
fields:
|
|
- name: PLLFRACN
|
|
description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1"
|
|
bit_offset: 3
|
|
bit_size: 13
|
|
fieldset/PRIVCFGR:
|
|
description: RCC privilege configuration register
|
|
fields:
|
|
- name: SPRIV
|
|
description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SPRIV
|
|
- name: NSPRIV
|
|
description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: NSPRIV
|
|
fieldset/RSR:
|
|
description: RCC reset status register
|
|
fields:
|
|
- name: RMVF
|
|
description: "remove reset flag\r Set and reset by software to reset the value of the reset flags."
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs."
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)."
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33."
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs."
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs."
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit."
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/SECCFGR:
|
|
description: RCC secure configuration register
|
|
fields:
|
|
- name: HSISEC
|
|
description: "HSI clock configuration and status bits security\r Set and reset by software."
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSESEC
|
|
description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software."
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CSISEC
|
|
description: "CSI clock configuration and status bits security\r Set and reset by software."
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSISEC
|
|
description: "LSI clock configuration and status bits security\r Set and reset by software."
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: LSESEC
|
|
description: "LSE clock configuration and status bits security\r Set and reset by software."
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: SYSCLKSEC
|
|
description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software."
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PRESCSEC
|
|
description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software."
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: PLLSEC
|
|
description: "PLL1 clock configuration and status bits security\r Set and reset by software."
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: HSI48SEC
|
|
description: "HSI48 clock configuration and status bits security\r Set and reset by software."
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RMVFSEC
|
|
description: "Remove reset flag security\r Set and reset by software."
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: CKPERSELSEC
|
|
description: "per_ck selection security\r Set and reset by software."
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum/ADCDACSEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: HCLK1
|
|
description: rcc_hclk selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: SYS
|
|
description: sys_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL2_R
|
|
description: pll2_r_ck selected as kernel clock
|
|
value: 2
|
|
- name: HSE
|
|
description: hse_ck selected as kernel clock
|
|
value: 3
|
|
- name: HSI
|
|
description: hsi_ker_ck selected as kernel clock
|
|
value: 4
|
|
- name: CSI
|
|
description: csi_ker_ck selected as kernel clock
|
|
value: 5
|
|
enum/CECSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: LSE
|
|
description: lse_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: LSI
|
|
description: lsi_ker_ck selected as kernel clock
|
|
value: 1
|
|
- name: CSI_DIV_122
|
|
description: csi_ker_ck/122 selected as kernel clock
|
|
value: 2
|
|
enum/CKPERSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: hsi_ker_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: CSI
|
|
description: csi_ker_ck selected as kernel clock
|
|
value: 1
|
|
- name: HSE
|
|
description: hse_ck selected as kernel clock
|
|
value: 2
|
|
enum/DACSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: DAC_HOLD
|
|
description: dac_hold_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: DAC_HOLD_2
|
|
description: dac_hold_ck selected as kernel clock
|
|
value: 1
|
|
enum/FDCANSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSE
|
|
description: hse_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL2_Q
|
|
description: pll2_q_ck selected as kernel clock
|
|
value: 2
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: sys_ck not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: sys_ck divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: sys_ck divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: sys_ck divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: sys_ck divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: sys_ck divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: sys_ck divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: sys_ck divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: sys_ck divided by 512
|
|
value: 15
|
|
enum/HSEEXT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Analog
|
|
description: HSE in analog mode (default after reset)
|
|
value: 0
|
|
- name: Digital
|
|
description: HSE in digital mode
|
|
value: 1
|
|
enum/HSIDIV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div1
|
|
description: No division
|
|
value: 0
|
|
- name: Div2
|
|
description: Division by 2
|
|
value: 1
|
|
- name: Div4
|
|
description: Division by 4
|
|
value: 2
|
|
- name: Div8
|
|
description: Division by 8
|
|
value: 3
|
|
enum/ICSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: PCLK1
|
|
description: rcc_pclk1 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 1
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 2
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 3
|
|
enum/LPTIMSEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PCLK3
|
|
description: rcc_pclk3 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_R
|
|
description: pll3_r selected as peripheral clock
|
|
value: 2
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 3
|
|
- name: LSI
|
|
description: LSI selected as peripheral clock
|
|
value: 4
|
|
- name: PER
|
|
description: PER selected as peripheral clock
|
|
value: 5
|
|
enum/LPUARTSEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PCLK3
|
|
description: rcc_pclk3 selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q_ck selected as kernel clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker_ck selected as kernel clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker_ck selected as kernel clock
|
|
value: 4
|
|
- name: LSE
|
|
description: lse_ck selected as kernel clock
|
|
value: 5
|
|
enum/LSCOSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: LSI
|
|
description: LSI clock selected
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE clock selected
|
|
value: 1
|
|
enum/LSEDRV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Low
|
|
description: Low driving capability
|
|
value: 0
|
|
- name: MediumLow
|
|
description: Medium low driving capability
|
|
value: 1
|
|
- name: MediumHigh
|
|
description: Medium high driving capability
|
|
value: 2
|
|
- name: High
|
|
description: High driving capability
|
|
value: 3
|
|
enum/LSEEXT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Analog
|
|
description: LSE in analog mode (default after Backup domain reset)
|
|
value: 0
|
|
- name: Digital
|
|
description: LSE in digital mode (do not use if RTC is active).
|
|
value: 1
|
|
enum/MCO1SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected for micro-controller clock output
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE selected for micro-controller clock output
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected for micro-controller clock output
|
|
value: 2
|
|
- name: PLL1_Q
|
|
description: pll1_q selected for micro-controller clock output
|
|
value: 3
|
|
- name: HSI48
|
|
description: HSI48 selected for micro-controller clock output
|
|
value: 4
|
|
enum/MCO2SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: SYS
|
|
description: System clock selected for micro-controller clock output
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p selected for micro-controller clock output
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected for micro-controller clock output
|
|
value: 2
|
|
- name: PLL1_P
|
|
description: pll1_p selected for micro-controller clock output
|
|
value: 3
|
|
- name: CSI
|
|
description: CSI selected for micro-controller clock output
|
|
value: 4
|
|
- name: LSI
|
|
description: LSI selected for micro-controller clock output
|
|
value: 5
|
|
enum/MCOPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: Divide by 1
|
|
value: 1
|
|
- name: Div2
|
|
description: Divide by 2
|
|
value: 2
|
|
- name: Div3
|
|
description: Divide by 3
|
|
value: 3
|
|
- name: Div4
|
|
description: Divide by 4
|
|
value: 4
|
|
- name: Div5
|
|
description: Divide by 5
|
|
value: 5
|
|
- name: Div6
|
|
description: Divide by 6
|
|
value: 6
|
|
- name: Div7
|
|
description: Divide by 7
|
|
value: 7
|
|
- name: Div8
|
|
description: Divide by 8
|
|
value: 8
|
|
- name: Div9
|
|
description: Divide by 9
|
|
value: 9
|
|
- name: Div10
|
|
description: Divide by 10
|
|
value: 10
|
|
- name: Div11
|
|
description: Divide by 11
|
|
value: 11
|
|
- name: Div12
|
|
description: Divide by 12
|
|
value: 12
|
|
- name: Div13
|
|
description: Divide by 13
|
|
value: 13
|
|
- name: Div14
|
|
description: Divide by 14
|
|
value: 14
|
|
- name: Div15
|
|
description: Divide by 15
|
|
value: 15
|
|
enum/NSPRIV:
|
|
bit_size: 1
|
|
variants:
|
|
- name: B_0x0
|
|
description: Read and write to RCC non-secure functions can be done by privileged or unprivileged access.
|
|
value: 0
|
|
- name: B_0x1
|
|
description: Read and write to RCC non-secure functions can be done by privileged access only
|
|
value: 1
|
|
enum/OCTOSPISEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HCLK4
|
|
description: rcc_hclk4 selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL2_R
|
|
description: pll2_r_ck selected as kernel clock
|
|
value: 2
|
|
- name: PER
|
|
description: per_ck selected as kernel clock
|
|
value: 3
|
|
enum/PLLDIV:
|
|
bit_size: 7
|
|
variants:
|
|
- name: Div1
|
|
value: 0
|
|
- name: Div2
|
|
value: 1
|
|
- name: Div3
|
|
value: 2
|
|
- name: Div4
|
|
value: 3
|
|
- name: Div5
|
|
value: 4
|
|
- name: Div6
|
|
value: 5
|
|
- name: Div7
|
|
value: 6
|
|
- name: Div8
|
|
value: 7
|
|
- name: Div9
|
|
value: 8
|
|
- name: Div10
|
|
value: 9
|
|
- name: Div11
|
|
value: 10
|
|
- name: Div12
|
|
value: 11
|
|
- name: Div13
|
|
value: 12
|
|
- name: Div14
|
|
value: 13
|
|
- name: Div15
|
|
value: 14
|
|
- name: Div16
|
|
value: 15
|
|
- name: Div17
|
|
value: 16
|
|
- name: Div18
|
|
value: 17
|
|
- name: Div19
|
|
value: 18
|
|
- name: Div20
|
|
value: 19
|
|
- name: Div21
|
|
value: 20
|
|
- name: Div22
|
|
value: 21
|
|
- name: Div23
|
|
value: 22
|
|
- name: Div24
|
|
value: 23
|
|
- name: Div25
|
|
value: 24
|
|
- name: Div26
|
|
value: 25
|
|
- name: Div27
|
|
value: 26
|
|
- name: Div28
|
|
value: 27
|
|
- name: Div29
|
|
value: 28
|
|
- name: Div30
|
|
value: 29
|
|
- name: Div31
|
|
value: 30
|
|
- name: Div32
|
|
value: 31
|
|
- name: Div33
|
|
value: 32
|
|
- name: Div34
|
|
value: 33
|
|
- name: Div35
|
|
value: 34
|
|
- name: Div36
|
|
value: 35
|
|
- name: Div37
|
|
value: 36
|
|
- name: Div38
|
|
value: 37
|
|
- name: Div39
|
|
value: 38
|
|
- name: Div40
|
|
value: 39
|
|
- name: Div41
|
|
value: 40
|
|
- name: Div42
|
|
value: 41
|
|
- name: Div43
|
|
value: 42
|
|
- name: Div44
|
|
value: 43
|
|
- name: Div45
|
|
value: 44
|
|
- name: Div46
|
|
value: 45
|
|
- name: Div47
|
|
value: 46
|
|
- name: Div48
|
|
value: 47
|
|
- name: Div49
|
|
value: 48
|
|
- name: Div50
|
|
value: 49
|
|
- name: Div51
|
|
value: 50
|
|
- name: Div52
|
|
value: 51
|
|
- name: Div53
|
|
value: 52
|
|
- name: Div54
|
|
value: 53
|
|
- name: Div55
|
|
value: 54
|
|
- name: Div56
|
|
value: 55
|
|
- name: Div57
|
|
value: 56
|
|
- name: Div58
|
|
value: 57
|
|
- name: Div59
|
|
value: 58
|
|
- name: Div60
|
|
value: 59
|
|
- name: Div61
|
|
value: 60
|
|
- name: Div62
|
|
value: 61
|
|
- name: Div63
|
|
value: 62
|
|
- name: Div64
|
|
value: 63
|
|
- name: Div65
|
|
value: 64
|
|
- name: Div66
|
|
value: 65
|
|
- name: Div67
|
|
value: 66
|
|
- name: Div68
|
|
value: 67
|
|
- name: Div69
|
|
value: 68
|
|
- name: Div70
|
|
value: 69
|
|
- name: Div71
|
|
value: 70
|
|
- name: Div72
|
|
value: 71
|
|
- name: Div73
|
|
value: 72
|
|
- name: Div74
|
|
value: 73
|
|
- name: Div75
|
|
value: 74
|
|
- name: Div76
|
|
value: 75
|
|
- name: Div77
|
|
value: 76
|
|
- name: Div78
|
|
value: 77
|
|
- name: Div79
|
|
value: 78
|
|
- name: Div80
|
|
value: 79
|
|
- name: Div81
|
|
value: 80
|
|
- name: Div82
|
|
value: 81
|
|
- name: Div83
|
|
value: 82
|
|
- name: Div84
|
|
value: 83
|
|
- name: Div85
|
|
value: 84
|
|
- name: Div86
|
|
value: 85
|
|
- name: Div87
|
|
value: 86
|
|
- name: Div88
|
|
value: 87
|
|
- name: Div89
|
|
value: 88
|
|
- name: Div90
|
|
value: 89
|
|
- name: Div91
|
|
value: 90
|
|
- name: Div92
|
|
value: 91
|
|
- name: Div93
|
|
value: 92
|
|
- name: Div94
|
|
value: 93
|
|
- name: Div95
|
|
value: 94
|
|
- name: Div96
|
|
value: 95
|
|
- name: Div97
|
|
value: 96
|
|
- name: Div98
|
|
value: 97
|
|
- name: Div99
|
|
value: 98
|
|
- name: Div100
|
|
value: 99
|
|
- name: Div101
|
|
value: 100
|
|
- name: Div102
|
|
value: 101
|
|
- name: Div103
|
|
value: 102
|
|
- name: Div104
|
|
value: 103
|
|
- name: Div105
|
|
value: 104
|
|
- name: Div106
|
|
value: 105
|
|
- name: Div107
|
|
value: 106
|
|
- name: Div108
|
|
value: 107
|
|
- name: Div109
|
|
value: 108
|
|
- name: Div110
|
|
value: 109
|
|
- name: Div111
|
|
value: 110
|
|
- name: Div112
|
|
value: 111
|
|
- name: Div113
|
|
value: 112
|
|
- name: Div114
|
|
value: 113
|
|
- name: Div115
|
|
value: 114
|
|
- name: Div116
|
|
value: 115
|
|
- name: Div117
|
|
value: 116
|
|
- name: Div118
|
|
value: 117
|
|
- name: Div119
|
|
value: 118
|
|
- name: Div120
|
|
value: 119
|
|
- name: Div121
|
|
value: 120
|
|
- name: Div122
|
|
value: 121
|
|
- name: Div123
|
|
value: 122
|
|
- name: Div124
|
|
value: 123
|
|
- name: Div125
|
|
value: 124
|
|
- name: Div126
|
|
value: 125
|
|
- name: Div127
|
|
value: 126
|
|
- name: Div128
|
|
value: 127
|
|
enum/PLLM:
|
|
bit_size: 6
|
|
variants:
|
|
- name: Div1
|
|
value: 1
|
|
- name: Div2
|
|
value: 2
|
|
- name: Div3
|
|
value: 3
|
|
- name: Div4
|
|
value: 4
|
|
- name: Div5
|
|
value: 5
|
|
- name: Div6
|
|
value: 6
|
|
- name: Div7
|
|
value: 7
|
|
- name: Div8
|
|
value: 8
|
|
- name: Div9
|
|
value: 9
|
|
- name: Div10
|
|
value: 10
|
|
- name: Div11
|
|
value: 11
|
|
- name: Div12
|
|
value: 12
|
|
- name: Div13
|
|
value: 13
|
|
- name: Div14
|
|
value: 14
|
|
- name: Div15
|
|
value: 15
|
|
- name: Div16
|
|
value: 16
|
|
- name: Div17
|
|
value: 17
|
|
- name: Div18
|
|
value: 18
|
|
- name: Div19
|
|
value: 19
|
|
- name: Div20
|
|
value: 20
|
|
- name: Div21
|
|
value: 21
|
|
- name: Div22
|
|
value: 22
|
|
- name: Div23
|
|
value: 23
|
|
- name: Div24
|
|
value: 24
|
|
- name: Div25
|
|
value: 25
|
|
- name: Div26
|
|
value: 26
|
|
- name: Div27
|
|
value: 27
|
|
- name: Div28
|
|
value: 28
|
|
- name: Div29
|
|
value: 29
|
|
- name: Div30
|
|
value: 30
|
|
- name: Div31
|
|
value: 31
|
|
- name: Div32
|
|
value: 32
|
|
- name: Div33
|
|
value: 33
|
|
- name: Div34
|
|
value: 34
|
|
- name: Div35
|
|
value: 35
|
|
- name: Div36
|
|
value: 36
|
|
- name: Div37
|
|
value: 37
|
|
- name: Div38
|
|
value: 38
|
|
- name: Div39
|
|
value: 39
|
|
- name: Div40
|
|
value: 40
|
|
- name: Div41
|
|
value: 41
|
|
- name: Div42
|
|
value: 42
|
|
- name: Div43
|
|
value: 43
|
|
- name: Div44
|
|
value: 44
|
|
- name: Div45
|
|
value: 45
|
|
- name: Div46
|
|
value: 46
|
|
- name: Div47
|
|
value: 47
|
|
- name: Div48
|
|
value: 48
|
|
- name: Div49
|
|
value: 49
|
|
- name: Div50
|
|
value: 50
|
|
- name: Div51
|
|
value: 51
|
|
- name: Div52
|
|
value: 52
|
|
- name: Div53
|
|
value: 53
|
|
- name: Div54
|
|
value: 54
|
|
- name: Div55
|
|
value: 55
|
|
- name: Div56
|
|
value: 56
|
|
- name: Div57
|
|
value: 57
|
|
- name: Div58
|
|
value: 58
|
|
- name: Div59
|
|
value: 59
|
|
- name: Div60
|
|
value: 60
|
|
- name: Div61
|
|
value: 61
|
|
- name: Div62
|
|
value: 62
|
|
enum/PLLN:
|
|
bit_size: 9
|
|
variants:
|
|
- name: Mul4
|
|
value: 3
|
|
- name: Mul5
|
|
value: 4
|
|
- name: Mul6
|
|
value: 5
|
|
- name: Mul7
|
|
value: 6
|
|
- name: Mul8
|
|
value: 7
|
|
- name: Mul9
|
|
value: 8
|
|
- name: Mul10
|
|
value: 9
|
|
- name: Mul11
|
|
value: 10
|
|
- name: Mul12
|
|
value: 11
|
|
- name: Mul13
|
|
value: 12
|
|
- name: Mul14
|
|
value: 13
|
|
- name: Mul15
|
|
value: 14
|
|
- name: Mul16
|
|
value: 15
|
|
- name: Mul17
|
|
value: 16
|
|
- name: Mul18
|
|
value: 17
|
|
- name: Mul19
|
|
value: 18
|
|
- name: Mul20
|
|
value: 19
|
|
- name: Mul21
|
|
value: 20
|
|
- name: Mul22
|
|
value: 21
|
|
- name: Mul23
|
|
value: 22
|
|
- name: Mul24
|
|
value: 23
|
|
- name: Mul25
|
|
value: 24
|
|
- name: Mul26
|
|
value: 25
|
|
- name: Mul27
|
|
value: 26
|
|
- name: Mul28
|
|
value: 27
|
|
- name: Mul29
|
|
value: 28
|
|
- name: Mul30
|
|
value: 29
|
|
- name: Mul31
|
|
value: 30
|
|
- name: Mul32
|
|
value: 31
|
|
- name: Mul33
|
|
value: 32
|
|
- name: Mul34
|
|
value: 33
|
|
- name: Mul35
|
|
value: 34
|
|
- name: Mul36
|
|
value: 35
|
|
- name: Mul37
|
|
value: 36
|
|
- name: Mul38
|
|
value: 37
|
|
- name: Mul39
|
|
value: 38
|
|
- name: Mul40
|
|
value: 39
|
|
- name: Mul41
|
|
value: 40
|
|
- name: Mul42
|
|
value: 41
|
|
- name: Mul43
|
|
value: 42
|
|
- name: Mul44
|
|
value: 43
|
|
- name: Mul45
|
|
value: 44
|
|
- name: Mul46
|
|
value: 45
|
|
- name: Mul47
|
|
value: 46
|
|
- name: Mul48
|
|
value: 47
|
|
- name: Mul49
|
|
value: 48
|
|
- name: Mul50
|
|
value: 49
|
|
- name: Mul51
|
|
value: 50
|
|
- name: Mul52
|
|
value: 51
|
|
- name: Mul53
|
|
value: 52
|
|
- name: Mul54
|
|
value: 53
|
|
- name: Mul55
|
|
value: 54
|
|
- name: Mul56
|
|
value: 55
|
|
- name: Mul57
|
|
value: 56
|
|
- name: Mul58
|
|
value: 57
|
|
- name: Mul59
|
|
value: 58
|
|
- name: Mul60
|
|
value: 59
|
|
- name: Mul61
|
|
value: 60
|
|
- name: Mul62
|
|
value: 61
|
|
- name: Mul63
|
|
value: 62
|
|
- name: Mul64
|
|
value: 63
|
|
- name: Mul65
|
|
value: 64
|
|
- name: Mul66
|
|
value: 65
|
|
- name: Mul67
|
|
value: 66
|
|
- name: Mul68
|
|
value: 67
|
|
- name: Mul69
|
|
value: 68
|
|
- name: Mul70
|
|
value: 69
|
|
- name: Mul71
|
|
value: 70
|
|
- name: Mul72
|
|
value: 71
|
|
- name: Mul73
|
|
value: 72
|
|
- name: Mul74
|
|
value: 73
|
|
- name: Mul75
|
|
value: 74
|
|
- name: Mul76
|
|
value: 75
|
|
- name: Mul77
|
|
value: 76
|
|
- name: Mul78
|
|
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|
|
value: 418
|
|
- name: Mul420
|
|
value: 419
|
|
- name: Mul421
|
|
value: 420
|
|
- name: Mul422
|
|
value: 421
|
|
- name: Mul423
|
|
value: 422
|
|
- name: Mul424
|
|
value: 423
|
|
- name: Mul425
|
|
value: 424
|
|
- name: Mul426
|
|
value: 425
|
|
- name: Mul427
|
|
value: 426
|
|
- name: Mul428
|
|
value: 427
|
|
- name: Mul429
|
|
value: 428
|
|
- name: Mul430
|
|
value: 429
|
|
- name: Mul431
|
|
value: 430
|
|
- name: Mul432
|
|
value: 431
|
|
- name: Mul433
|
|
value: 432
|
|
- name: Mul434
|
|
value: 433
|
|
- name: Mul435
|
|
value: 434
|
|
- name: Mul436
|
|
value: 435
|
|
- name: Mul437
|
|
value: 436
|
|
- name: Mul438
|
|
value: 437
|
|
- name: Mul439
|
|
value: 438
|
|
- name: Mul440
|
|
value: 439
|
|
- name: Mul441
|
|
value: 440
|
|
- name: Mul442
|
|
value: 441
|
|
- name: Mul443
|
|
value: 442
|
|
- name: Mul444
|
|
value: 443
|
|
- name: Mul445
|
|
value: 444
|
|
- name: Mul446
|
|
value: 445
|
|
- name: Mul447
|
|
value: 446
|
|
- name: Mul448
|
|
value: 447
|
|
- name: Mul449
|
|
value: 448
|
|
- name: Mul450
|
|
value: 449
|
|
- name: Mul451
|
|
value: 450
|
|
- name: Mul452
|
|
value: 451
|
|
- name: Mul453
|
|
value: 452
|
|
- name: Mul454
|
|
value: 453
|
|
- name: Mul455
|
|
value: 454
|
|
- name: Mul456
|
|
value: 455
|
|
- name: Mul457
|
|
value: 456
|
|
- name: Mul458
|
|
value: 457
|
|
- name: Mul459
|
|
value: 458
|
|
- name: Mul460
|
|
value: 459
|
|
- name: Mul461
|
|
value: 460
|
|
- name: Mul462
|
|
value: 461
|
|
- name: Mul463
|
|
value: 462
|
|
- name: Mul464
|
|
value: 463
|
|
- name: Mul465
|
|
value: 464
|
|
- name: Mul466
|
|
value: 465
|
|
- name: Mul467
|
|
value: 466
|
|
- name: Mul468
|
|
value: 467
|
|
- name: Mul469
|
|
value: 468
|
|
- name: Mul470
|
|
value: 469
|
|
- name: Mul471
|
|
value: 470
|
|
- name: Mul472
|
|
value: 471
|
|
- name: Mul473
|
|
value: 472
|
|
- name: Mul474
|
|
value: 473
|
|
- name: Mul475
|
|
value: 474
|
|
- name: Mul476
|
|
value: 475
|
|
- name: Mul477
|
|
value: 476
|
|
- name: Mul478
|
|
value: 477
|
|
- name: Mul479
|
|
value: 478
|
|
- name: Mul480
|
|
value: 479
|
|
- name: Mul481
|
|
value: 480
|
|
- name: Mul482
|
|
value: 481
|
|
- name: Mul483
|
|
value: 482
|
|
- name: Mul484
|
|
value: 483
|
|
- name: Mul485
|
|
value: 484
|
|
- name: Mul486
|
|
value: 485
|
|
- name: Mul487
|
|
value: 486
|
|
- name: Mul488
|
|
value: 487
|
|
- name: Mul489
|
|
value: 488
|
|
- name: Mul490
|
|
value: 489
|
|
- name: Mul491
|
|
value: 490
|
|
- name: Mul492
|
|
value: 491
|
|
- name: Mul493
|
|
value: 492
|
|
- name: Mul494
|
|
value: 493
|
|
- name: Mul495
|
|
value: 494
|
|
- name: Mul496
|
|
value: 495
|
|
- name: Mul497
|
|
value: 496
|
|
- name: Mul498
|
|
value: 497
|
|
- name: Mul499
|
|
value: 498
|
|
- name: Mul500
|
|
value: 499
|
|
- name: Mul501
|
|
value: 500
|
|
- name: Mul502
|
|
value: 501
|
|
- name: Mul503
|
|
value: 502
|
|
- name: Mul504
|
|
value: 503
|
|
- name: Mul505
|
|
value: 504
|
|
- name: Mul506
|
|
value: 505
|
|
- name: Mul507
|
|
value: 506
|
|
- name: Mul508
|
|
value: 507
|
|
- name: Mul509
|
|
value: 508
|
|
- name: Mul510
|
|
value: 509
|
|
- name: Mul511
|
|
value: 510
|
|
- name: Mul512
|
|
value: 511
|
|
enum/PLLRGE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Range1
|
|
description: Frequency is between 1 and 2 MHz
|
|
value: 0
|
|
- name: Range2
|
|
description: Frequency is between 2 and 4 MHz
|
|
value: 1
|
|
- name: Range4
|
|
description: Frequency is between 4 and 8 MHz
|
|
value: 2
|
|
- name: Range8
|
|
description: Frequency is between 8 and 16 MHz
|
|
value: 3
|
|
enum/PLLSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: no clock send to DIVMx divider and PLLs (default after reset)
|
|
value: 0
|
|
- name: HSI
|
|
description: HSI selected as PLL clock (hsi_ck)
|
|
value: 1
|
|
- name: CSI
|
|
description: CSI selected as PLL clock (csi_ck)
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE selected as PLL clock (hse_ck)
|
|
value: 3
|
|
enum/PLLVCOSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: WideVCO
|
|
description: VCO frequency range 192 to 836 MHz
|
|
value: 0
|
|
- name: MediumVCO
|
|
description: VCO frequency range 150 to 420 MHz
|
|
value: 1
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: rcc_pclk3 = rcc_hclk1 / 1
|
|
value: 0
|
|
- name: Div2
|
|
description: rcc_pclk3 = rcc_hclk1 / 2
|
|
value: 4
|
|
- name: Div4
|
|
description: rcc_pclk3 = rcc_hclk1 / 4
|
|
value: 5
|
|
- name: Div8
|
|
description: rcc_pclk3 = rcc_hclk1 / 8
|
|
value: 6
|
|
- name: Div16
|
|
description: rcc_pclk3 = rcc_hclk1 / 16
|
|
value: 7
|
|
enum/RNGSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI48
|
|
description: hsi48_ker_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock
|
|
value: 1
|
|
- name: LSE
|
|
description: lse_ck selected as kernel clock
|
|
value: 2
|
|
- name: LSI
|
|
description: lsi_ker_ck selected as kernel clock
|
|
value: 3
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: no clock (default after Backup domain reset)
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE selected as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI selected as RTC clock
|
|
value: 2
|
|
- name: HSE_DIV_RTCPRE
|
|
description: HSE divided by RTCPRE value selected as RTC clock
|
|
value: 3
|
|
enum/SAISEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL3_P
|
|
description: pll3_p_ck selected as kernel clock
|
|
value: 2
|
|
- name: AUDIOCLK
|
|
description: AUDIOCLK selected as kernel clock
|
|
value: 3
|
|
- name: PER
|
|
description: per_ck selected as kernel clock
|
|
value: 4
|
|
enum/SDMMCSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_R
|
|
description: pll2_r_ck selected as kernel clock
|
|
value: 1
|
|
enum/SPI1SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL3_P
|
|
description: pll3_p_ck selected as kernel clock
|
|
value: 2
|
|
- name: AUDIOCLK
|
|
description: AUDIOCLK selected as kernel clock
|
|
value: 3
|
|
- name: PER
|
|
description: per_ck selected as kernel clock
|
|
value: 4
|
|
enum/SPI2SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL3_P
|
|
description: pll3_p_ck selected as kernel clock
|
|
value: 2
|
|
- name: AUDIOCLK
|
|
description: AUDIOCLK selected as kernel clock
|
|
value: 3
|
|
- name: PER
|
|
description: per_ck selected as kernel clock
|
|
value: 4
|
|
enum/SPI3SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PLL1_Q
|
|
description: pll1_q_ck selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_P
|
|
description: pll2_p_ck selected as kernel clock
|
|
value: 1
|
|
- name: PLL3_P
|
|
description: pll3_p_ck selected as kernel clock
|
|
value: 2
|
|
- name: AUDIOCLK
|
|
description: AUDIOCLK selected as kernel clock
|
|
value: 3
|
|
- name: PER
|
|
description: per_ck selected as kernel clock
|
|
value: 4
|
|
enum/SPI4SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PCLK2
|
|
description: rcc_pclk2 selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: HSE
|
|
description: HSE selected as peripheral clock
|
|
value: 5
|
|
enum/SPI5SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PCLK3
|
|
description: rcc_pclk3 selected as kernel clock (default after reset)
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: HSE
|
|
description: HSE selected as peripheral clock
|
|
value: 5
|
|
enum/SPI6SEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PCLK4
|
|
description: rcc_pclk4 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: HSE
|
|
description: HSE selected as peripheral clock
|
|
value: 5
|
|
enum/SPRIV:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Any
|
|
description: Read and write to RCC secure functions can be done by privileged or unprivileged access.
|
|
value: 0
|
|
- name: Privileged
|
|
description: Read and write to RCC secure functions can be done by privileged access only
|
|
value: 1
|
|
enum/STOPKERWUCK:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as wakeup clock from system Stop (default after reset)
|
|
value: 0
|
|
- name: CSI
|
|
description: CSI selected as wakeup clock from system Stop
|
|
value: 1
|
|
enum/STOPWUCK:
|
|
bit_size: 1
|
|
variants:
|
|
- name: CSI
|
|
description: CSI selected as wakeup clock from system Stop
|
|
value: 1
|
|
enum/SW:
|
|
bit_size: 3
|
|
variants:
|
|
- name: HSI
|
|
description: HSI selected as system clock
|
|
value: 0
|
|
- name: CSI
|
|
description: CSI selected as system clock
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected as system clock
|
|
value: 2
|
|
- name: PLL1_P
|
|
description: PLL1 selected as system clock
|
|
value: 3
|
|
enum/SYSTICKSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HCLK1_DIV_8
|
|
description: rcc_hclk/8 selected as clock source (default after reset)
|
|
value: 0
|
|
- name: LSI
|
|
description: lsi_ker_ck[1] selected as clock source
|
|
value: 1
|
|
- name: LSE
|
|
description: lse_ck[1] selected as clock source
|
|
value: 2
|
|
enum/TIMICSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: B_0x0
|
|
description: No internal clock available for timers input capture (default after reset)
|
|
value: 0
|
|
- name: B_0x1
|
|
description: hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture
|
|
value: 1
|
|
enum/TIMPRE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: DefaultX2
|
|
description: The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset)
|
|
value: 0
|
|
- name: DefaultX4
|
|
description: The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2
|
|
value: 1
|
|
enum/UARTSEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PCLK1
|
|
description: rcc_pclk1 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 5
|
|
enum/USARTSEL:
|
|
bit_size: 3
|
|
variants:
|
|
- name: PCLK2
|
|
description: rcc_pclk2 selected as peripheral clock
|
|
value: 0
|
|
- name: PLL2_Q
|
|
description: pll2_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI
|
|
description: hsi_ker selected as peripheral clock
|
|
value: 3
|
|
- name: CSI
|
|
description: csi_ker selected as peripheral clock
|
|
value: 4
|
|
- name: LSE
|
|
description: LSE selected as peripheral clock
|
|
value: 5
|
|
enum/USBSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: DISABLE
|
|
description: Disable the kernel clock
|
|
value: 0
|
|
- name: PLL1_Q
|
|
description: pll1_q selected as peripheral clock
|
|
value: 1
|
|
- name: PLL3_Q
|
|
description: pll3_q selected as peripheral clock
|
|
value: 2
|
|
- name: HSI48
|
|
description: HSI48 selected as peripheral clock
|
|
value: 3
|