604 lines
14 KiB
YAML
604 lines
14 KiB
YAML
---
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block/ADC:
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description: Analog-to-digital converter
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items:
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- name: SR
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description: status register
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byte_offset: 0
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fieldset: SR
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- name: CR1
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description: control register 1
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byte_offset: 4
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fieldset: CR1
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- name: CR2
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description: control register 2
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byte_offset: 8
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fieldset: CR2
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- name: SMPR1
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description: sample time register 1
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byte_offset: 12
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fieldset: SMPR1
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- name: SMPR2
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description: sample time register 2
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byte_offset: 16
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fieldset: SMPR2
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- name: JOFR
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description: injected channel data offset register x
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array:
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len: 4
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stride: 4
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byte_offset: 20
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fieldset: JOFR
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- name: HTR
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description: watchdog higher threshold register
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byte_offset: 36
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fieldset: HTR
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- name: LTR
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description: watchdog lower threshold register
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byte_offset: 40
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fieldset: LTR
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- name: SQR1
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description: regular sequence register 1
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byte_offset: 44
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fieldset: SQR1
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- name: SQR2
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description: regular sequence register 2
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byte_offset: 48
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fieldset: SQR2
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- name: SQR3
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description: regular sequence register 3
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byte_offset: 52
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fieldset: SQR3
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- name: JSQR
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description: injected sequence register
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byte_offset: 56
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fieldset: JSQR
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- name: JDR
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description: injected data register x
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array:
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len: 4
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stride: 4
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byte_offset: 60
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access: Read
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fieldset: JDR
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- name: DR
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description: regular data register
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byte_offset: 76
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access: Read
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fieldset: DR
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fieldset/CR1:
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description: control register 1
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fields:
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- name: AWDCH
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description: Analog watchdog channel select bits
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bit_offset: 0
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bit_size: 5
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- name: EOCIE
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description: Interrupt enable for EOC
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bit_offset: 5
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bit_size: 1
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- name: AWDIE
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description: Analog watchdog interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: JEOCIE
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description: Interrupt enable for injected channels
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bit_offset: 7
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bit_size: 1
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- name: SCAN
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description: Scan mode
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bit_offset: 8
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bit_size: 1
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- name: AWDSGL
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description: Enable the watchdog on a single channel in scan mode
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bit_offset: 9
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bit_size: 1
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enum: AWDSGL
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- name: JAUTO
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description: Automatic injected group conversion
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bit_offset: 10
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bit_size: 1
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- name: DISCEN
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description: Discontinuous mode on regular channels
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bit_offset: 11
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bit_size: 1
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- name: JDISCEN
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description: Discontinuous mode on injected channels
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bit_offset: 12
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bit_size: 1
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- name: DISCNUM
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description: Discontinuous mode channel count
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bit_offset: 13
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bit_size: 3
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- name: JAWDEN
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description: Analog watchdog enable on injected channels
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bit_offset: 22
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bit_size: 1
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- name: AWDEN
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description: Analog watchdog enable on regular channels
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bit_offset: 23
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bit_size: 1
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- name: RES
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description: Resolution
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bit_offset: 24
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bit_size: 2
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enum: RES
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- name: OVRIE
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description: Overrun interrupt enable
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bit_offset: 26
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bit_size: 1
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fieldset/CR2:
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description: control register 2
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fields:
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- name: ADON
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description: A/D Converter ON / OFF
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bit_offset: 0
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bit_size: 1
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- name: CONT
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description: Continuous conversion
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bit_offset: 1
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bit_size: 1
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enum: CONT
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- name: DMA
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description: Direct memory access mode (for single ADC mode)
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bit_offset: 8
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bit_size: 1
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- name: DDS
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description: DMA disable selection (for single ADC mode)
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bit_offset: 9
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bit_size: 1
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enum: DDS
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- name: EOCS
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description: End of conversion selection
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bit_offset: 10
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bit_size: 1
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enum: EOCS
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- name: ALIGN
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description: Data alignment
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bit_offset: 11
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bit_size: 1
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enum: ALIGN
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- name: JEXTSEL
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description: External event select for injected group
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bit_offset: 16
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bit_size: 4
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enum: JEXTSEL
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- name: JEXTEN
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description: External trigger enable for injected channels
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bit_offset: 20
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bit_size: 2
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enum: JEXTEN
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- name: JSWSTART
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description: Start conversion of injected channels
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bit_offset: 22
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bit_size: 1
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- name: EXTSEL
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description: External event select for regular group
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bit_offset: 24
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bit_size: 4
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enum: EXTSEL
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- name: EXTEN
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description: External trigger enable for regular channels
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bit_offset: 28
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bit_size: 2
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enum: EXTEN
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- name: SWSTART
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description: Start conversion of regular channels
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bit_offset: 30
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bit_size: 1
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fieldset/DR:
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description: regular data register
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fields:
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- name: DATA
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description: Regular data
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bit_offset: 0
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bit_size: 16
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fieldset/HTR:
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description: watchdog higher threshold register
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fields:
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- name: HT
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description: Analog watchdog higher threshold
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bit_offset: 0
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bit_size: 12
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fieldset/JDR:
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description: injected data register x
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fields:
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- name: JDATA
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description: Injected data
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bit_offset: 0
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bit_size: 16
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fieldset/JOFR:
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description: injected channel data offset register x
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fields:
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- name: JOFFSET
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description: Data offset for injected channel x
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bit_offset: 0
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bit_size: 12
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fieldset/JSQR:
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description: injected sequence register
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fields:
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- name: JSQ
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description: 1st conversion in injected sequence
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bit_offset: 0
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bit_size: 5
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array:
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len: 4
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stride: 5
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- name: JL
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description: Injected sequence length
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bit_offset: 20
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bit_size: 2
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fieldset/LTR:
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description: watchdog lower threshold register
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fields:
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- name: LT
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description: Analog watchdog lower threshold
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bit_offset: 0
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bit_size: 12
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fieldset/SMPR1:
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description: sample time register 1
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fields:
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- name: SMP
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description: Channel 10 sampling time selection
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bit_offset: 0
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bit_size: 3
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array:
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len: 9
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stride: 3
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enum: SAMPLE_TIME
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- name: SMPx_x
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description: Sample time bits
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bit_offset: 0
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bit_size: 32
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enum: SMPR_SMPx_x
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fieldset/SMPR2:
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description: sample time register 2
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fields:
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- name: SMP
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description: Channel 0 sampling time selection
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bit_offset: 0
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bit_size: 3
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array:
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len: 10
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stride: 3
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enum: SAMPLE_TIME
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- name: SMPx_x
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description: Sample time bits
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bit_offset: 0
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bit_size: 32
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enum: SMPR_SMPx_x
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fieldset/SQR1:
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description: regular sequence register 1
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fields:
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- name: SQ
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description: 13th conversion in regular sequence
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bit_offset: 0
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bit_size: 5
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array:
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len: 4
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stride: 5
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- name: L
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description: Regular channel sequence length
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bit_offset: 20
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bit_size: 4
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fieldset/SQR2:
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description: regular sequence register 2
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fields:
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- name: SQ
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description: 7th conversion in regular sequence
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bit_offset: 0
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bit_size: 5
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array:
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len: 6
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stride: 5
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fieldset/SQR3:
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description: regular sequence register 3
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fields:
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- name: SQ
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description: 1st conversion in regular sequence
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bit_offset: 0
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bit_size: 5
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array:
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len: 6
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stride: 5
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fieldset/SR:
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description: status register
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fields:
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- name: AWD
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description: Analog watchdog flag
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bit_offset: 0
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bit_size: 1
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enum: AWD
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- name: EOC
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description: Regular channel end of conversion
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bit_offset: 1
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bit_size: 1
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enum: EOC
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- name: JEOC
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description: Injected channel end of conversion
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bit_offset: 2
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bit_size: 1
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enum: JEOC
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- name: JSTRT
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description: Injected channel start flag
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bit_offset: 3
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bit_size: 1
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enum: JSTRT
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- name: STRT
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description: Regular channel start flag
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bit_offset: 4
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bit_size: 1
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enum: STRT
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- name: OVR
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description: Overrun
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bit_offset: 5
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bit_size: 1
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enum: OVR
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enum/ALIGN:
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bit_size: 1
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variants:
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- name: Right
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description: Right alignment
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value: 0
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- name: Left
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description: Left alignment
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value: 1
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enum/AWD:
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bit_size: 1
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variants:
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- name: NoEvent
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description: No analog watchdog event occurred
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value: 0
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- name: Event
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description: Analog watchdog event occurred
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value: 1
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enum/AWDSGL:
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bit_size: 1
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variants:
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- name: AllChannels
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description: Analog watchdog enabled on all channels
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value: 0
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- name: SingleChannel
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description: Analog watchdog enabled on a single channel
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value: 1
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enum/CONT:
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bit_size: 1
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variants:
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- name: Single
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description: Single conversion mode
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value: 0
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- name: Continuous
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description: Continuous conversion mode
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value: 1
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enum/DDS:
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bit_size: 1
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variants:
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- name: Single
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description: No new DMA request is issued after the last transfer
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value: 0
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- name: Continuous
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description: DMA requests are issued as long as data are converted and DMA=1
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value: 1
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enum/EOC:
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bit_size: 1
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variants:
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- name: NotComplete
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description: Conversion is not complete
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value: 0
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- name: Complete
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description: Conversion complete
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value: 1
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enum/EOCS:
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bit_size: 1
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variants:
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- name: EachSequence
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description: The EOC bit is set at the end of each sequence of regular conversions
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value: 0
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- name: EachConversion
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description: The EOC bit is set at the end of each regular conversion
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value: 1
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enum/EXTEN:
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bit_size: 2
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variants:
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- name: Disabled
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description: Trigger detection disabled
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value: 0
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- name: RisingEdge
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description: Trigger detection on the rising edge
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value: 1
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- name: FallingEdge
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description: Trigger detection on the falling edge
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value: 2
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- name: BothEdges
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description: Trigger detection on both the rising and falling edges
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value: 3
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enum/EXTSEL:
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bit_size: 4
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variants:
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- name: TIM1CC1
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description: Timer 1 CC1 event
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value: 0
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- name: TIM1CC2
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description: Timer 1 CC2 event
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value: 1
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- name: TIM1CC3
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description: Timer 1 CC3 event
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value: 2
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- name: TIM2CC2
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description: Timer 2 CC2 event
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value: 3
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- name: TIM2CC3
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description: Timer 2 CC3 event
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value: 4
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- name: TIM2CC4
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description: Timer 2 CC4 event
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value: 5
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- name: TIM2TRGO
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description: Timer 2 TRGO event
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value: 6
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enum/JEOC:
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bit_size: 1
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variants:
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- name: NotComplete
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description: Conversion is not complete
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value: 0
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- name: Complete
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description: Conversion complete
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value: 1
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enum/JEXTEN:
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bit_size: 2
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variants:
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- name: Disabled
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description: Trigger detection disabled
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value: 0
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- name: RisingEdge
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description: Trigger detection on the rising edge
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value: 1
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- name: FallingEdge
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description: Trigger detection on the falling edge
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value: 2
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- name: BothEdges
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description: Trigger detection on both the rising and falling edges
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value: 3
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enum/JEXTSEL:
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bit_size: 4
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variants:
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- name: TIM1TRGO
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description: Timer 1 TRGO event
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value: 0
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- name: TIM1CC4
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description: Timer 1 CC4 event
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value: 1
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- name: TIM2TRGO
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description: Timer 2 TRGO event
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value: 2
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- name: TIM2CC1
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description: Timer 2 CC1 event
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value: 3
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- name: TIM3CC4
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description: Timer 3 CC4 event
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value: 4
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- name: TIM4TRGO
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description: Timer 4 TRGO event
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value: 5
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- name: TIM8CC4
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description: Timer 8 CC4 event
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value: 7
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- name: TIM1TRGO2
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description: Timer 1 TRGO(2) event
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value: 8
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- name: TIM8TRGO
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description: Timer 8 TRGO event
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value: 9
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- name: TIM8TRGO2
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description: Timer 8 TRGO(2) event
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value: 10
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- name: TIM3CC3
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description: Timer 3 CC3 event
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value: 11
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- name: TIM5TRGO
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description: Timer 5 TRGO event
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value: 12
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- name: TIM3CC1
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description: Timer 3 CC1 event
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value: 13
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- name: TIM6TRGO
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description: Timer 6 TRGO event
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value: 14
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enum/JSTRT:
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bit_size: 1
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variants:
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- name: NotStarted
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description: No injected channel conversion started
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value: 0
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- name: Started
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description: Injected channel conversion has started
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value: 1
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enum/OVR:
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bit_size: 1
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variants:
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- name: NoOverrun
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description: No overrun occurred
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value: 0
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- name: Overrun
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description: Overrun occurred
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value: 1
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enum/RES:
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bit_size: 2
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variants:
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- name: TwelveBit
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description: 12-bit (15 ADCCLK cycles)
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value: 0
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- name: TenBit
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description: 10-bit (13 ADCCLK cycles)
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value: 1
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- name: EightBit
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description: 8-bit (11 ADCCLK cycles)
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value: 2
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- name: SixBit
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description: 6-bit (9 ADCCLK cycles)
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value: 3
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enum/SAMPLE_TIME:
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bit_size: 3
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variants:
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- name: Cycles3
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description: 3 cycles
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value: 0
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- name: Cycles15
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description: 15 cycles
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value: 1
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- name: Cycles28
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description: 28 cycles
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value: 2
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- name: Cycles56
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description: 56 cycles
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value: 3
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- name: Cycles84
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description: 84 cycles
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value: 4
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- name: Cycles112
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description: 112 cycles
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value: 5
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- name: Cycles144
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description: 144 cycles
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value: 6
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- name: Cycles480
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description: 480 cycles
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value: 7
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enum/SMPR_SMPx_x:
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bit_size: 32
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variants:
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- name: Cycles3
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description: 3 cycles
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value: 0
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- name: Cycles15
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description: 15 cycles
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value: 1
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- name: Cycles28
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description: 28 cycles
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value: 2
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- name: Cycles56
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description: 56 cycles
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value: 3
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- name: Cycles84
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description: 84 cycles
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value: 4
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- name: Cycles112
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description: 112 cycles
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value: 5
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- name: Cycles144
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description: 144 cycles
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value: 6
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- name: Cycles480
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description: 480 cycles
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value: 7
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enum/STRT:
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bit_size: 1
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variants:
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- name: NotStarted
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description: No regular channel conversion started
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value: 0
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- name: Started
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description: Regular channel conversion has started
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value: 1
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