636 lines
8.4 KiB
YAML
636 lines
8.4 KiB
YAML
PA0:
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COMP1_OUT: 7
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I2S2_CK: 0
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LPTIM1_OUT: 5
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SPI2_SCK: 0
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TIM2_CH1: 2
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TIM2_ETR: 2
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UCPD2_FRSTX1: 6
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UCPD2_FRSTX2: 6
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USART2_CTS: 1
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USART2_NSS: 1
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USART4_TX: 4
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PA1:
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EVENTOUT: 7
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I2C1_SMBA: 6
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I2S1_CK: 0
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SPI1_SCK: 0
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TIM15_CH1N: 5
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TIM2_CH2: 2
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USART2_CK: 1
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USART2_DE: 1
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USART2_RTS: 1
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USART4_RX: 4
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PA10:
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EVENTOUT: 7
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I2C1_SDA: 6
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I2C2_SDA: 8
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I2S2_SD: 0
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RCC_MCO_2: 3
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SPI2_MOSI: 0
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TIM17_BK: 5
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TIM1_CH3: 2
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USART1_RX: 1
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PA11:
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COMP1_OUT: 7
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FDCAN1_RX: 3
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I2C2_SCL: 6
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I2S1_MCK: 0
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SPI1_MISO: 0
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TIM1_BK2: 5
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TIM1_CH4: 2
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USART1_CTS: 1
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USART1_NSS: 1
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PA12:
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COMP2_OUT: 7
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FDCAN1_TX: 3
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I2C2_SDA: 6
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I2S1_SD: 0
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I2S_CKIN: 5
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SPI1_MOSI: 0
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TIM1_ETR: 2
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USART1_CK: 1
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USART1_DE: 1
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USART1_RTS: 1
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PA13:
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EVENTOUT: 7
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IR_OUT: 1
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LPUART2_RX: 10
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SYS_SWDIO: 0
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USB_NOE: 2
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PA14:
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EVENTOUT: 7
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LPUART2_TX: 10
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SYS_SWCLK: 0
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USART2_TX: 1
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PA15:
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EVENTOUT: 7
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I2C2_SMBA: 8
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I2S1_WS: 0
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RCC_MCO_2: 3
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SPI1_NSS: 0
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SPI3_NSS: 9
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TIM2_CH1: 2
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TIM2_ETR: 2
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USART2_RX: 1
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USART3_CK: 5
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USART3_DE: 5
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USART3_RTS: 5
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USART4_CK: 4
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USART4_DE: 4
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USART4_RTS: 4
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USB_NOE: 6
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PA2:
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COMP2_OUT: 7
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I2S1_SD: 0
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LPUART1_TX: 6
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SPI1_MOSI: 0
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TIM15_CH1: 5
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TIM2_CH3: 2
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UCPD1_FRSTX1: 4
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UCPD1_FRSTX2: 4
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USART2_TX: 1
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PA3:
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EVENTOUT: 7
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I2S2_MCK: 0
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LPUART1_RX: 6
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SPI2_MISO: 0
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TIM15_CH2: 5
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TIM2_CH4: 2
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UCPD2_FRSTX1: 4
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UCPD2_FRSTX2: 4
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USART2_RX: 1
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PA4:
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EVENTOUT: 7
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I2S1_WS: 0
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I2S2_SD: 1
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LPTIM2_OUT: 5
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SPI1_NSS: 0
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SPI2_MOSI: 1
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SPI3_NSS: 9
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TIM14_CH1: 4
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UCPD2_FRSTX1: 6
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UCPD2_FRSTX2: 6
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USART6_TX: 3
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USB_NOE: 2
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PA5:
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CEC: 1
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EVENTOUT: 7
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I2S1_CK: 0
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LPTIM2_ETR: 5
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SPI1_SCK: 0
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TIM2_CH1: 2
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TIM2_ETR: 2
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UCPD1_FRSTX1: 6
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UCPD1_FRSTX2: 6
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USART3_TX: 4
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USART6_RX: 3
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PA6:
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COMP1_OUT: 7
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I2C2_SDA: 8
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I2C3_SDA: 9
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I2S1_MCK: 0
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LPUART1_CTS: 6
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SPI1_MISO: 0
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TIM16_CH1: 5
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TIM1_BK: 2
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TIM3_CH1: 1
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USART3_CTS: 4
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USART3_NSS: 4
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USART6_CTS: 3
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USART6_NSS: 3
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PA7:
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COMP2_OUT: 7
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I2C2_SCL: 8
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I2C3_SCL: 9
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I2S1_SD: 0
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SPI1_MOSI: 0
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TIM14_CH1: 4
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TIM17_CH1: 5
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TIM1_CH1N: 2
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TIM3_CH2: 1
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UCPD1_FRSTX1: 6
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UCPD1_FRSTX2: 6
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USART6_CK: 3
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USART6_DE: 3
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USART6_RTS: 3
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PA8:
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CRS1_SYNC: 4
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EVENTOUT: 7
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I2C2_SMBA: 8
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I2S2_WS: 1
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LPTIM2_OUT: 5
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RCC_MCO: 0
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SPI2_NSS: 1
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TIM1_CH1: 2
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PA9:
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EVENTOUT: 7
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I2C1_SCL: 6
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I2C2_SCL: 8
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I2S2_MCK: 4
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RCC_MCO: 0
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SPI2_MISO: 4
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TIM15_BK: 5
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TIM1_CH2: 2
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USART1_TX: 1
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PB0:
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COMP1_OUT: 7
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FDCAN2_RX: 3
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I2S1_WS: 0
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LPTIM1_OUT: 5
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LPUART2_CTS: 10
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SPI1_NSS: 0
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TIM1_CH2N: 2
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TIM3_CH3: 1
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UCPD1_FRSTX1: 6
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UCPD1_FRSTX2: 6
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USART3_RX: 4
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USART5_TX: 8
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PB1:
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COMP3_OUT: 7
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FDCAN2_TX: 3
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LPTIM2_IN1: 5
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LPUART1_DE: 6
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LPUART1_RTS: 6
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LPUART2_DE: 10
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LPUART2_RTS: 10
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TIM14_CH1: 0
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TIM1_CH3N: 2
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TIM3_CH4: 1
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USART3_CK: 4
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USART3_DE: 4
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USART3_RTS: 4
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USART5_RX: 8
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PB10:
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CEC: 0
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COMP1_OUT: 7
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I2C2_SCL: 6
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I2S2_CK: 5
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LPUART1_RX: 1
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SPI2_SCK: 5
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TIM2_CH3: 2
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USART3_TX: 4
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PB11:
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COMP2_OUT: 7
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I2C2_SDA: 6
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I2S2_SD: 0
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LPUART1_TX: 1
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SPI2_MOSI: 0
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TIM2_CH4: 2
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USART3_RX: 4
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PB12:
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EVENTOUT: 7
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FDCAN2_RX: 3
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I2C2_SMBA: 8
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I2S2_WS: 0
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LPUART1_DE: 1
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LPUART1_RTS: 1
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SPI2_NSS: 0
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TIM15_BK: 5
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TIM1_BK: 2
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UCPD2_FRSTX1: 6
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UCPD2_FRSTX2: 6
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PB13:
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EVENTOUT: 7
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FDCAN2_TX: 3
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I2C2_SCL: 6
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I2S2_CK: 0
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LPUART1_CTS: 1
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SPI2_SCK: 0
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TIM15_CH1N: 5
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TIM1_CH1N: 2
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USART3_CTS: 4
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USART3_NSS: 4
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PB14:
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EVENTOUT: 7
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I2C2_SDA: 6
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I2S2_MCK: 0
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SPI2_MISO: 0
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TIM15_CH1: 5
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TIM1_CH2N: 2
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UCPD1_FRSTX1: 1
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UCPD1_FRSTX2: 1
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USART3_CK: 4
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USART3_DE: 4
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USART3_RTS: 4
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USART6_CK: 8
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USART6_DE: 8
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USART6_RTS: 8
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PB15:
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EVENTOUT: 7
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I2S2_SD: 0
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SPI2_MOSI: 0
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TIM15_CH1N: 4
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TIM15_CH2: 5
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TIM1_CH3N: 2
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USART6_CTS: 8
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USART6_NSS: 8
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PB2:
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EVENTOUT: 7
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I2S2_MCK: 1
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LPTIM1_OUT: 5
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RCC_MCO_2: 3
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SPI2_MISO: 1
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USART3_TX: 4
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PB3:
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EVENTOUT: 7
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I2C2_SCL: 8
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I2C3_SCL: 6
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I2S1_CK: 0
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SPI1_SCK: 0
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SPI3_SCK: 9
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TIM1_CH2: 1
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TIM2_CH2: 2
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USART1_CK: 4
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USART1_DE: 4
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USART1_RTS: 4
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USART5_TX: 3
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PB4:
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EVENTOUT: 7
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I2C2_SDA: 8
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I2C3_SDA: 6
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I2S1_MCK: 0
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SPI1_MISO: 0
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SPI3_MISO: 9
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TIM17_BK: 5
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TIM3_CH1: 1
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USART1_CTS: 4
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USART1_NSS: 4
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USART5_RX: 3
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PB5:
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COMP2_OUT: 7
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FDCAN2_RX: 3
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I2C1_SMBA: 6
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I2S1_SD: 0
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LPTIM1_IN1: 5
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SPI1_MOSI: 0
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SPI3_MOSI: 9
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TIM16_BK: 2
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TIM3_CH2: 1
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USART5_CK: 8
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USART5_DE: 8
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USART5_RTS: 8
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PB6:
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EVENTOUT: 7
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FDCAN2_TX: 3
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I2C1_SCL: 6
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I2S2_MCK: 4
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LPTIM1_ETR: 5
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LPUART2_TX: 10
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SPI2_MISO: 4
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TIM16_CH1N: 2
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TIM1_CH3: 1
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TIM4_CH1: 9
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USART1_TX: 0
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USART5_CTS: 8
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USART5_NSS: 8
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PB7:
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EVENTOUT: 7
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I2C1_SDA: 6
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I2S2_SD: 1
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LPTIM1_IN2: 5
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LPUART2_RX: 10
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SPI2_MOSI: 1
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TIM17_CH1N: 2
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TIM4_CH2: 9
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USART1_RX: 0
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USART4_CTS: 4
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USART4_NSS: 4
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PB8:
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CEC: 0
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EVENTOUT: 7
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FDCAN1_RX: 3
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I2C1_SCL: 6
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I2S2_CK: 1
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SPI2_SCK: 1
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TIM15_BK: 5
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TIM16_CH1: 2
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TIM4_CH3: 9
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USART3_TX: 4
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USART6_TX: 8
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PB9:
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EVENTOUT: 7
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FDCAN1_TX: 3
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I2C1_SDA: 6
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I2S2_WS: 5
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IR_OUT: 0
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SPI2_NSS: 5
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TIM17_CH1: 2
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TIM4_CH4: 9
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UCPD2_FRSTX1: 1
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UCPD2_FRSTX2: 1
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USART3_RX: 4
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USART6_RX: 8
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PC0:
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COMP3_OUT: 7
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I2C3_SCL: 6
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LPTIM1_IN1: 0
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LPTIM2_IN1: 2
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LPUART1_RX: 1
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LPUART2_TX: 3
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USART6_TX: 4
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PC1:
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I2C3_SDA: 6
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LPTIM1_OUT: 0
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LPUART1_TX: 1
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LPUART2_RX: 3
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TIM15_CH1: 2
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USART6_RX: 4
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PC10:
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SPI3_SCK: 4
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TIM1_CH3: 2
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USART3_TX: 0
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USART4_TX: 1
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PC11:
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SPI3_MISO: 4
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TIM1_CH4: 2
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USART3_RX: 0
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USART4_RX: 1
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PC12:
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LPTIM1_IN1: 0
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SPI3_MOSI: 4
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TIM14_CH1: 2
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UCPD1_FRSTX1: 1
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UCPD1_FRSTX2: 1
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USART5_TX: 3
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PC13:
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TIM1_BK: 2
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PC14:
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TIM1_BK2: 2
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PC15:
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RCC_OSC32_EN: 0
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RCC_OSC_EN: 1
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TIM15_BK: 2
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PC2:
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COMP3_OUT: 7
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FDCAN2_RX: 3
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I2S2_MCK: 1
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LPTIM1_IN2: 0
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SPI2_MISO: 1
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TIM15_CH2: 2
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PC3:
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FDCAN2_TX: 3
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I2S2_SD: 1
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LPTIM1_ETR: 0
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LPTIM2_ETR: 2
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SPI2_MOSI: 1
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PC4:
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FDCAN1_RX: 3
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TIM2_CH1: 2
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TIM2_ETR: 2
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USART1_TX: 1
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USART3_TX: 0
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PC5:
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FDCAN1_TX: 3
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TIM2_CH2: 2
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USART1_RX: 1
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USART3_RX: 0
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PC6:
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LPUART2_TX: 3
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TIM2_CH3: 2
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TIM3_CH1: 1
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UCPD1_FRSTX1: 0
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UCPD1_FRSTX2: 0
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PC7:
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LPUART2_RX: 3
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TIM2_CH4: 2
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TIM3_CH2: 1
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UCPD2_FRSTX1: 0
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UCPD2_FRSTX2: 0
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PC8:
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LPUART2_CTS: 3
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TIM1_CH1: 2
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TIM3_CH3: 1
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UCPD2_FRSTX1: 0
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UCPD2_FRSTX2: 0
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PC9:
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I2S_CKIN: 0
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LPUART2_DE: 3
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LPUART2_RTS: 3
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TIM1_CH2: 2
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TIM3_CH4: 1
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USB_NOE: 6
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PD0:
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EVENTOUT: 0
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FDCAN1_RX: 3
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I2S2_WS: 1
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SPI2_NSS: 1
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TIM16_CH1: 2
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PD1:
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EVENTOUT: 0
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FDCAN1_TX: 3
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I2S2_CK: 1
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SPI2_SCK: 1
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TIM17_CH1: 2
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PD10:
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RCC_MCO: 0
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PD11:
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LPTIM2_ETR: 1
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USART3_CTS: 0
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USART3_NSS: 0
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PD12:
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FDCAN1_RX: 3
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LPTIM2_IN1: 1
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TIM4_CH1: 2
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USART3_CK: 0
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USART3_DE: 0
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USART3_RTS: 0
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PD13:
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FDCAN1_TX: 3
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LPTIM2_OUT: 1
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TIM4_CH2: 2
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PD14:
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FDCAN2_RX: 3
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LPUART2_CTS: 1
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TIM4_CH3: 2
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PD15:
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CRS1_SYNC: 0
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FDCAN2_TX: 3
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LPUART2_DE: 1
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LPUART2_RTS: 1
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TIM4_CH4: 2
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PD2:
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TIM1_CH1N: 2
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TIM3_ETR: 1
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USART3_CK: 0
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USART3_DE: 0
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USART3_RTS: 0
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USART5_RX: 3
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PD3:
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I2S2_MCK: 1
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SPI2_MISO: 1
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TIM1_CH2N: 2
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USART2_CTS: 0
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USART2_NSS: 0
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USART5_TX: 3
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PD4:
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I2S2_SD: 1
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SPI2_MOSI: 1
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TIM1_CH3N: 2
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USART2_CK: 0
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USART2_DE: 0
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USART2_RTS: 0
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USART5_CK: 3
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USART5_DE: 3
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USART5_RTS: 3
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PD5:
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I2S1_MCK: 1
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SPI1_MISO: 1
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TIM1_BK: 2
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USART2_TX: 0
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USART5_CTS: 3
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USART5_NSS: 3
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PD6:
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I2S1_SD: 1
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LPTIM2_OUT: 2
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SPI1_MOSI: 1
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USART2_RX: 0
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PD7:
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RCC_MCO_2: 3
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PD8:
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I2S1_CK: 1
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LPTIM1_OUT: 2
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SPI1_SCK: 1
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USART3_TX: 0
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PD9:
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I2S1_WS: 1
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SPI1_NSS: 1
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TIM1_BK2: 2
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USART3_RX: 0
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PE0:
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EVENTOUT: 1
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|
TIM16_CH1: 0
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|
TIM4_ETR: 2
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PE1:
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|
EVENTOUT: 1
|
|
TIM17_CH1: 0
|
|
PE10:
|
|
TIM1_CH2N: 1
|
|
USART5_TX: 3
|
|
PE11:
|
|
TIM1_CH2: 1
|
|
USART5_RX: 3
|
|
PE12:
|
|
I2S1_WS: 0
|
|
SPI1_NSS: 0
|
|
TIM1_CH3N: 1
|
|
PE13:
|
|
I2S1_CK: 0
|
|
SPI1_SCK: 0
|
|
TIM1_CH3: 1
|
|
PE14:
|
|
I2S1_MCK: 0
|
|
SPI1_MISO: 0
|
|
TIM1_BK2: 2
|
|
TIM1_CH4: 1
|
|
PE15:
|
|
I2S1_SD: 0
|
|
SPI1_MOSI: 0
|
|
TIM1_BK: 1
|
|
PE2:
|
|
TIM3_ETR: 1
|
|
PE3:
|
|
TIM3_CH1: 1
|
|
PE4:
|
|
TIM3_CH2: 1
|
|
PE5:
|
|
TIM3_CH3: 1
|
|
PE6:
|
|
TIM3_CH4: 1
|
|
PE7:
|
|
TIM1_ETR: 1
|
|
USART5_CK: 3
|
|
USART5_DE: 3
|
|
USART5_RTS: 3
|
|
PE8:
|
|
TIM1_CH1N: 1
|
|
USART4_TX: 0
|
|
PE9:
|
|
TIM1_CH1: 1
|
|
USART4_RX: 0
|
|
PF0:
|
|
CRS1_SYNC: 0
|
|
EVENTOUT: 1
|
|
TIM14_CH1: 2
|
|
PF1:
|
|
EVENTOUT: 1
|
|
RCC_OSC_EN: 0
|
|
TIM15_CH1N: 2
|
|
PF10:
|
|
USART6_RX: 3
|
|
PF11:
|
|
USART6_CK: 3
|
|
USART6_DE: 3
|
|
USART6_RTS: 3
|
|
PF12:
|
|
TIM15_CH1: 0
|
|
USART6_CTS: 3
|
|
USART6_NSS: 3
|
|
PF13:
|
|
TIM15_CH2: 0
|
|
PF2:
|
|
LPUART2_DE: 3
|
|
LPUART2_RTS: 3
|
|
LPUART2_TX: 1
|
|
RCC_MCO: 0
|
|
PF3:
|
|
LPUART2_RX: 1
|
|
USART6_CK: 3
|
|
USART6_DE: 3
|
|
USART6_RTS: 3
|
|
PF4:
|
|
LPUART1_TX: 1
|
|
PF5:
|
|
LPUART1_RX: 1
|
|
PF6:
|
|
LPUART1_DE: 1
|
|
LPUART1_RTS: 1
|
|
PF7:
|
|
LPUART1_CTS: 1
|
|
USART5_CTS: 3
|
|
USART5_NSS: 3
|
|
PF8: {}
|
|
PF9:
|
|
USART6_TX: 3
|
|
PI8: {}
|