451 lines
12 KiB
YAML
451 lines
12 KiB
YAML
---
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block/EXTI:
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description: External interrupt/event controller
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items:
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- name: RTSR1
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description: rising trigger selection register
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byte_offset: 0
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fieldset: RTSR1
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- name: FTSR1
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description: falling trigger selection register
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byte_offset: 4
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fieldset: FTSR1
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- name: SWIER1
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description: software interrupt event register
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byte_offset: 8
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fieldset: SWIER1
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- name: PR1
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description: EXTI pending register
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byte_offset: 12
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fieldset: PR1
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- name: RTSR2
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description: rising trigger selection register
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byte_offset: 32
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fieldset: RTSR2
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- name: FTSR2
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description: falling trigger selection register
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byte_offset: 36
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fieldset: FTSR2
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- name: SWIER2
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description: software interrupt event register
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byte_offset: 40
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fieldset: SWIER2
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- name: PR2
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description: pending register
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byte_offset: 44
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fieldset: PR2
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- name: C1IMR1
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description: CPUm wakeup with interrupt mask register
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byte_offset: 128
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fieldset: C1IMR1
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- name: C1EMR1
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description: CPUm wakeup with event mask register
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byte_offset: 132
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fieldset: C1EMR1
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- name: C1IMR2
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description: CPUm wakeup with interrupt mask register
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byte_offset: 144
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fieldset: C1IMR2
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- name: C1EMR2
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description: CPUm wakeup with event mask register
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byte_offset: 148
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fieldset: C1EMR2
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- name: C2IMR1
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description: CPUm wakeup with interrupt mask register
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byte_offset: 192
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fieldset: C2IMR1
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- name: C2EMR1
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description: CPUm wakeup with event mask register
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byte_offset: 196
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fieldset: C2EMR1
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- name: C2IMR2
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description: CPUm wakeup with interrupt mask register
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byte_offset: 208
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fieldset: C2IMR2
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- name: C2EMR2
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description: CPUm wakeup with event mask register
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byte_offset: 212
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fieldset: C2EMR2
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- name: HWCFGR7
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description: EXTI Hardware configuration registers
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byte_offset: 984
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access: Read
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fieldset: HWCFGR7
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- name: HWCFGR6
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description: Hardware configuration registers
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byte_offset: 988
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access: Read
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fieldset: HWCFGR6
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- name: HWCFGR5
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description: Hardware configuration registers
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byte_offset: 992
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access: Read
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fieldset: HWCFGR5
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- name: HWCFGR4
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description: Hardware configuration registers
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byte_offset: 996
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access: Read
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fieldset: HWCFGR4
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- name: HWCFGR3
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description: Hardware configuration registers
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byte_offset: 1000
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access: Read
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fieldset: HWCFGR3
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- name: HWCFGR2
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description: Hardware configuration registers
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byte_offset: 1004
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access: Read
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fieldset: HWCFGR2
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- name: HWCFGR1
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description: Hardware configuration register 1
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byte_offset: 1008
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access: Read
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fieldset: HWCFGR1
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- name: VERR
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description: EXTI IP Version register
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byte_offset: 1012
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access: Read
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fieldset: VERR
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- name: IPIDR
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description: Identification register
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byte_offset: 1016
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access: Read
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fieldset: IPIDR
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- name: SIDR
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description: Size ID register
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byte_offset: 1020
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access: Read
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fieldset: SIDR
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fieldset/C1EMR1:
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description: CPUm wakeup with event mask register
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fields:
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- name: EM0_15
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description: CPU(m) Wakeup with event generation Mask on Event input
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bit_offset: 0
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bit_size: 16
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- name: EM17_21
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description: CPU(m) Wakeup with event generation Mask on Event input
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bit_offset: 17
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bit_size: 5
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fieldset/C1EMR2:
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description: CPUm wakeup with event mask register
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fields:
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- name: EM
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description: CPU(m) Wakeup with event generation Mask on Event input
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bit_offset: 8
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bit_size: 2
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fieldset/C1IMR1:
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description: CPUm wakeup with interrupt mask register
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fields:
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- name: IM
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description: CPU(m) wakeup with interrupt Mask on Event input
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: MR
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fieldset/C1IMR2:
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description: CPUm wakeup with interrupt mask register
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fields:
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- name: IM
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description: CPUm Wakeup with interrupt Mask on Event input
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bit_offset: 0
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bit_size: 1
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array:
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len: 17
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stride: 1
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enum: MR
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fieldset/C2EMR1:
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description: CPUm wakeup with event mask register
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fields:
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- name: EM0_15
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description: CPU(m) Wakeup with event generation Mask on Event input
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bit_offset: 0
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bit_size: 16
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- name: EM17_21
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description: CPU(m) Wakeup with event generation Mask on Event input
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bit_offset: 17
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bit_size: 5
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fieldset/C2EMR2:
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description: CPUm wakeup with event mask register
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fields:
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- name: EM
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description: CPU(m) Wakeup with event generation Mask on Event input
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bit_offset: 8
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bit_size: 2
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fieldset/C2IMR1:
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description: CPUm wakeup with interrupt mask register
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fields:
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- name: IM
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description: CPU(m) wakeup with interrupt Mask on Event input
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bit_offset: 0
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bit_size: 1
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array:
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len: 32
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stride: 1
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enum: MR
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fieldset/C2IMR2:
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description: CPUm wakeup with interrupt mask register
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fields:
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- name: IM
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description: CPUm Wakeup with interrupt Mask on Event input
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bit_offset: 0
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bit_size: 1
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array:
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len: 17
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stride: 1
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enum: MR
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fieldset/FTSR1:
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description: falling trigger selection register
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fields:
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- name: FT
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description: Falling trigger event configuration bit of Configurable Event input
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bit_offset: 0
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bit_size: 1
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array:
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len: 22
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stride: 1
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enum: FT
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- name: FT_31
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description: Falling trigger event configuration bit of Configurable Event input
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bit_offset: 31
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bit_size: 1
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enum: FT
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fieldset/FTSR2:
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description: falling trigger selection register
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fields:
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- name: FT
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description: Falling trigger event configuration bit of Configurable Event input
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 0
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enum: FT
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- name: FT40_41
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description: Falling trigger event configuration bit of Configurable Event input
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum: FT
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fieldset/HWCFGR1:
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description: Hardware configuration register 1
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fields:
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- name: NBEVENTS
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description: HW configuration number of event
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bit_offset: 0
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bit_size: 8
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- name: NBCPUS
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description: HW configuration number of CPUs
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bit_offset: 8
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bit_size: 4
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- name: CPUEVTEN
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description: HW configuration of CPU(m) event output enable
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bit_offset: 12
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bit_size: 4
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fieldset/HWCFGR2:
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description: Hardware configuration registers
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fields:
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- name: EVENT_TRG
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description: HW configuration event trigger type
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bit_offset: 0
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bit_size: 32
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fieldset/HWCFGR3:
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description: Hardware configuration registers
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fields:
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- name: EVENT_TRG
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description: HW configuration event trigger type
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bit_offset: 0
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bit_size: 32
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fieldset/HWCFGR4:
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description: Hardware configuration registers
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fields:
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- name: EVENT_TRG
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description: HW configuration event trigger type
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bit_offset: 0
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bit_size: 32
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fieldset/HWCFGR5:
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description: Hardware configuration registers
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fields:
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- name: CPUEVENT
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description: HW configuration CPU event generation
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bit_offset: 0
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bit_size: 32
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fieldset/HWCFGR6:
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description: Hardware configuration registers
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fields:
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- name: CPUEVENT
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description: HW configuration CPU event generation
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bit_offset: 0
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bit_size: 32
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fieldset/HWCFGR7:
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description: EXTI Hardware configuration registers
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fields:
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- name: CPUEVENT
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description: HW configuration CPU event generation
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bit_offset: 0
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bit_size: 32
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fieldset/IPIDR:
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description: Identification register
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fields:
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- name: IPID
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description: IP Identification
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bit_offset: 0
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bit_size: 32
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fieldset/PR1:
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description: EXTI pending register
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fields:
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- name: PIF
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description: Configurable event inputs Pending bit
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bit_offset: 0
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bit_size: 1
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array:
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len: 22
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stride: 1
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enum_read: PRR
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enum_write: PRW
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- name: PIF_31
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description: Configurable event inputs Pending bit
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bit_offset: 31
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bit_size: 1
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enum_read: PRR
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enum_write: PRW
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fieldset/PR2:
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description: pending register
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fields:
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- name: PIF
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description: Configurable event inputs x+32 Pending bit.
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bit_offset: 1
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bit_size: 1
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enum_read: PRR
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enum_write: PRW
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- name: PIF40_41
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description: Configurable event inputs x+32 Pending bit.
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum_read: PRR
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enum_write: PRW
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fieldset/RTSR1:
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description: rising trigger selection register
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fields:
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- name: RT
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description: Rising trigger event configuration bit of Configurable Event input
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bit_offset: 0
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bit_size: 22
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array:
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len: 22
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stride: 1
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enum: RT
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- name: RT_31
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description: Rising trigger event configuration bit of Configurable Event input
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bit_offset: 31
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bit_size: 1
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enum: RT
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fieldset/RTSR2:
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description: rising trigger selection register
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fields:
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- name: RT
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description: Rising trigger event configuration bit of Configurable Event input
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bit_offset: 1
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bit_size: 1
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enum: RT
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- name: RT40_41
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description: Rising trigger event configuration bit of Configurable Event input
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bit_offset: 8
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum: RT
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fieldset/SIDR:
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description: Size ID register
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fields:
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- name: SID
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description: Size Identification
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bit_offset: 0
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bit_size: 32
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fieldset/SWIER1:
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description: software interrupt event register
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fields:
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- name: SWI
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description: Software interrupt on event
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bit_offset: 0
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bit_size: 22
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- name: SWI_31
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description: Software interrupt on event
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bit_offset: 31
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bit_size: 1
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fieldset/SWIER2:
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description: software interrupt event register
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fields:
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- name: SWI
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description: Software interrupt on event
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bit_offset: 1
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bit_size: 1
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array:
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len: 1
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stride: 0
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- name: SWI40_41
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description: Software interrupt on event
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bit_offset: 8
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bit_size: 2
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fieldset/VERR:
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description: EXTI IP Version register
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fields:
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- name: MINREV
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description: Minor Revision number
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bit_offset: 0
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bit_size: 4
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- name: MAJREV
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description: Major Revision number
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bit_offset: 4
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bit_size: 4
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enum/FT:
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bit_size: 1
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variants:
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- name: Disabled
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description: Falling edge trigger is disabled
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value: 0
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- name: Enabled
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description: Falling edge trigger is enabled
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value: 1
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enum/RT:
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bit_size: 1
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variants:
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- name: Disabled
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description: Falling edge trigger is disabled
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value: 0
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- name: Enabled
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description: Falling edge trigger is enabled
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value: 1
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enum/MR:
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bit_size: 1
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variants:
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- name: Masked
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description: Interrupt request line is masked
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value: 0
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- name: Unmasked
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description: Interrupt request line is unmasked
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value: 1
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enum/PRR:
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bit_size: 1
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variants:
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- name: NotPending
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description: No trigger request occurred
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value: 0
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- name: Pending
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description: Selected trigger request occurred
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value: 1
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enum/PRW:
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bit_size: 1
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variants:
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- name: Clear
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description: Clears pending bit
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value: 1
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