11479 lines
274 KiB
YAML
11479 lines
274 KiB
YAML
---
|
|
block/HRTIM_Master:
|
|
description: "High Resolution Timer: Master\r Timers"
|
|
items:
|
|
- name: MCR
|
|
description: Master Timer Control Register
|
|
byte_offset: 0
|
|
fieldset: MCR
|
|
- name: MISR
|
|
description: "Master Timer Interrupt Status\r Register"
|
|
byte_offset: 4
|
|
access: Read
|
|
fieldset: MISR
|
|
- name: MICR
|
|
description: "Master Timer Interrupt Clear\r Register"
|
|
byte_offset: 8
|
|
access: Write
|
|
fieldset: MICR
|
|
- name: MDIER
|
|
description: MDIER4
|
|
byte_offset: 12
|
|
fieldset: MDIER
|
|
- name: MCNTR
|
|
description: Master Timer Counter Register
|
|
byte_offset: 16
|
|
fieldset: MCNTR
|
|
- name: MPER
|
|
description: Master Timer Period Register
|
|
byte_offset: 20
|
|
fieldset: MPER
|
|
- name: MREP
|
|
description: "Master Timer Repetition\r Register"
|
|
byte_offset: 24
|
|
fieldset: MREP
|
|
- name: MCMP1R
|
|
description: "Master Timer Compare 1\r Register"
|
|
byte_offset: 28
|
|
fieldset: MCMP1R
|
|
- name: MCMP2R
|
|
description: "Master Timer Compare 2\r Register"
|
|
byte_offset: 36
|
|
fieldset: MCMP2R
|
|
- name: MCMP3R
|
|
description: "Master Timer Compare 3\r Register"
|
|
byte_offset: 40
|
|
fieldset: MCMP3R
|
|
- name: MCMP4R
|
|
description: "Master Timer Compare 4\r Register"
|
|
byte_offset: 44
|
|
fieldset: MCMP4R
|
|
block/HRTIM_TIMA:
|
|
description: "High Resolution Timer: TIMA"
|
|
items:
|
|
- name: TIMACR
|
|
description: Timerx Control Register
|
|
byte_offset: 0
|
|
fieldset: TIMACR
|
|
- name: TIMAISR
|
|
description: "Timerx Interrupt Status\r Register"
|
|
byte_offset: 4
|
|
access: Read
|
|
fieldset: TIMAISR
|
|
- name: TIMAICR
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
byte_offset: 8
|
|
access: Write
|
|
fieldset: TIMAICR
|
|
- name: TIMADIER
|
|
description: TIMxDIER5
|
|
byte_offset: 12
|
|
fieldset: TIMADIER
|
|
- name: CNTAR
|
|
description: Timerx Counter Register
|
|
byte_offset: 16
|
|
fieldset: CNTAR
|
|
- name: PERAR
|
|
description: Timerx Period Register
|
|
byte_offset: 20
|
|
fieldset: PERAR
|
|
- name: REPAR
|
|
description: Timerx Repetition Register
|
|
byte_offset: 24
|
|
fieldset: REPAR
|
|
- name: CMP1AR
|
|
description: Timerx Compare 1 Register
|
|
byte_offset: 28
|
|
fieldset: CMP1AR
|
|
- name: CMP1CAR
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
byte_offset: 32
|
|
fieldset: CMP1CAR
|
|
- name: CMP2AR
|
|
description: Timerx Compare 2 Register
|
|
byte_offset: 36
|
|
fieldset: CMP2AR
|
|
- name: CMP3AR
|
|
description: Timerx Compare 3 Register
|
|
byte_offset: 40
|
|
fieldset: CMP3AR
|
|
- name: CMP4AR
|
|
description: Timerx Compare 4 Register
|
|
byte_offset: 44
|
|
fieldset: CMP4AR
|
|
- name: CPT1AR
|
|
description: Timerx Capture 1 Register
|
|
byte_offset: 48
|
|
access: Read
|
|
fieldset: CPT1AR
|
|
- name: CPT2AR
|
|
description: Timerx Capture 2 Register
|
|
byte_offset: 52
|
|
access: Read
|
|
fieldset: CPT2AR
|
|
- name: DTAR
|
|
description: Timerx Deadtime Register
|
|
byte_offset: 56
|
|
fieldset: DTAR
|
|
- name: SETA1R
|
|
description: Timerx Output1 Set Register
|
|
byte_offset: 60
|
|
fieldset: SETA1R
|
|
- name: RSTA1R
|
|
description: Timerx Output1 Reset Register
|
|
byte_offset: 64
|
|
fieldset: RSTA1R
|
|
- name: SETA2R
|
|
description: Timerx Output2 Set Register
|
|
byte_offset: 68
|
|
fieldset: SETA2R
|
|
- name: RSTA2R
|
|
description: Timerx Output2 Reset Register
|
|
byte_offset: 72
|
|
fieldset: RSTA2R
|
|
- name: EEFAR1
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
byte_offset: 76
|
|
fieldset: EEFAR1
|
|
- name: EEFAR2
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
byte_offset: 80
|
|
fieldset: EEFAR2
|
|
- name: RSTAR
|
|
description: TimerA Reset Register
|
|
byte_offset: 84
|
|
fieldset: RSTAR
|
|
- name: CHPAR
|
|
description: Timerx Chopper Register
|
|
byte_offset: 88
|
|
fieldset: CHPAR
|
|
- name: CPT1ACR
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
byte_offset: 92
|
|
fieldset: CPT1ACR
|
|
- name: CPT2ACR
|
|
description: CPT2xCR
|
|
byte_offset: 96
|
|
fieldset: CPT2ACR
|
|
- name: OUTAR
|
|
description: Timerx Output Register
|
|
byte_offset: 100
|
|
fieldset: OUTAR
|
|
- name: FLTAR
|
|
description: Timerx Fault Register
|
|
byte_offset: 104
|
|
fieldset: FLTAR
|
|
block/HRTIM_TIMB:
|
|
description: "High Resolution Timer: TIMB"
|
|
items:
|
|
- name: TIMBCR
|
|
description: Timerx Control Register
|
|
byte_offset: 0
|
|
fieldset: TIMBCR
|
|
- name: TIMBISR
|
|
description: "Timerx Interrupt Status\r Register"
|
|
byte_offset: 4
|
|
access: Read
|
|
fieldset: TIMBISR
|
|
- name: TIMBICR
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
byte_offset: 8
|
|
access: Write
|
|
fieldset: TIMBICR
|
|
- name: TIMBDIER
|
|
description: TIMxDIER5
|
|
byte_offset: 12
|
|
fieldset: TIMBDIER
|
|
- name: CNTBR
|
|
description: Timerx Counter Register
|
|
byte_offset: 16
|
|
fieldset: CNTBR
|
|
- name: PERBR
|
|
description: Timerx Period Register
|
|
byte_offset: 20
|
|
fieldset: PERBR
|
|
- name: REPBR
|
|
description: Timerx Repetition Register
|
|
byte_offset: 24
|
|
fieldset: REPBR
|
|
- name: CMP1BR
|
|
description: Timerx Compare 1 Register
|
|
byte_offset: 28
|
|
fieldset: CMP1BR
|
|
- name: CMP1CBR
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
byte_offset: 32
|
|
fieldset: CMP1CBR
|
|
- name: CMP2BR
|
|
description: Timerx Compare 2 Register
|
|
byte_offset: 36
|
|
fieldset: CMP2BR
|
|
- name: CMP3BR
|
|
description: Timerx Compare 3 Register
|
|
byte_offset: 40
|
|
fieldset: CMP3BR
|
|
- name: CMP4BR
|
|
description: Timerx Compare 4 Register
|
|
byte_offset: 44
|
|
fieldset: CMP4BR
|
|
- name: CPT1BR
|
|
description: Timerx Capture 1 Register
|
|
byte_offset: 48
|
|
access: Read
|
|
fieldset: CPT1BR
|
|
- name: CPT2BR
|
|
description: Timerx Capture 2 Register
|
|
byte_offset: 52
|
|
access: Read
|
|
fieldset: CPT2BR
|
|
- name: DTBR
|
|
description: Timerx Deadtime Register
|
|
byte_offset: 56
|
|
fieldset: DTBR
|
|
- name: SETB1R
|
|
description: Timerx Output1 Set Register
|
|
byte_offset: 60
|
|
fieldset: SETB1R
|
|
- name: RSTB1R
|
|
description: Timerx Output1 Reset Register
|
|
byte_offset: 64
|
|
fieldset: RSTB1R
|
|
- name: SETB2R
|
|
description: Timerx Output2 Set Register
|
|
byte_offset: 68
|
|
fieldset: SETB2R
|
|
- name: RSTB2R
|
|
description: Timerx Output2 Reset Register
|
|
byte_offset: 72
|
|
fieldset: RSTB2R
|
|
- name: EEFBR1
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
byte_offset: 76
|
|
fieldset: EEFBR1
|
|
- name: EEFBR2
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
byte_offset: 80
|
|
fieldset: EEFBR2
|
|
- name: RSTBR
|
|
description: TimerA Reset Register
|
|
byte_offset: 84
|
|
fieldset: RSTBR
|
|
- name: CHPBR
|
|
description: Timerx Chopper Register
|
|
byte_offset: 88
|
|
fieldset: CHPBR
|
|
- name: CPT1BCR
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
byte_offset: 92
|
|
fieldset: CPT1BCR
|
|
- name: CPT2BCR
|
|
description: CPT2xCR
|
|
byte_offset: 96
|
|
fieldset: CPT2BCR
|
|
- name: OUTBR
|
|
description: Timerx Output Register
|
|
byte_offset: 100
|
|
fieldset: OUTBR
|
|
- name: FLTBR
|
|
description: Timerx Fault Register
|
|
byte_offset: 104
|
|
fieldset: FLTBR
|
|
block/HRTIM_TIMC:
|
|
description: "High Resolution Timer: TIMC"
|
|
items:
|
|
- name: TIMCCR
|
|
description: Timerx Control Register
|
|
byte_offset: 0
|
|
fieldset: TIMCCR
|
|
- name: TIMCISR
|
|
description: "Timerx Interrupt Status\r Register"
|
|
byte_offset: 4
|
|
access: Read
|
|
fieldset: TIMCISR
|
|
- name: TIMCICR
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
byte_offset: 8
|
|
access: Write
|
|
fieldset: TIMCICR
|
|
- name: TIMCDIER
|
|
description: TIMxDIER5
|
|
byte_offset: 12
|
|
fieldset: TIMCDIER
|
|
- name: CNTCR
|
|
description: Timerx Counter Register
|
|
byte_offset: 16
|
|
fieldset: CNTCR
|
|
- name: PERCR
|
|
description: Timerx Period Register
|
|
byte_offset: 20
|
|
fieldset: PERCR
|
|
- name: REPCR
|
|
description: Timerx Repetition Register
|
|
byte_offset: 24
|
|
fieldset: REPCR
|
|
- name: CMP1CR
|
|
description: Timerx Compare 1 Register
|
|
byte_offset: 28
|
|
fieldset: CMP1CR
|
|
- name: CMP1CCR
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
byte_offset: 32
|
|
fieldset: CMP1CCR
|
|
- name: CMP2CR
|
|
description: Timerx Compare 2 Register
|
|
byte_offset: 36
|
|
fieldset: CMP2CR
|
|
- name: CMP3CR
|
|
description: Timerx Compare 3 Register
|
|
byte_offset: 40
|
|
fieldset: CMP3CR
|
|
- name: CMP4CR
|
|
description: Timerx Compare 4 Register
|
|
byte_offset: 44
|
|
fieldset: CMP4CR
|
|
- name: CPT1CR
|
|
description: Timerx Capture 1 Register
|
|
byte_offset: 48
|
|
access: Read
|
|
fieldset: CPT1CR
|
|
- name: CPT2CR
|
|
description: Timerx Capture 2 Register
|
|
byte_offset: 52
|
|
access: Read
|
|
fieldset: CPT2CR
|
|
- name: DTCR
|
|
description: Timerx Deadtime Register
|
|
byte_offset: 56
|
|
fieldset: DTCR
|
|
- name: SETC1R
|
|
description: Timerx Output1 Set Register
|
|
byte_offset: 60
|
|
fieldset: SETC1R
|
|
- name: RSTC1R
|
|
description: Timerx Output1 Reset Register
|
|
byte_offset: 64
|
|
fieldset: RSTC1R
|
|
- name: SETC2R
|
|
description: Timerx Output2 Set Register
|
|
byte_offset: 68
|
|
fieldset: SETC2R
|
|
- name: RSTC2R
|
|
description: Timerx Output2 Reset Register
|
|
byte_offset: 72
|
|
fieldset: RSTC2R
|
|
- name: EEFCR1
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
byte_offset: 76
|
|
fieldset: EEFCR1
|
|
- name: EEFCR2
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
byte_offset: 80
|
|
fieldset: EEFCR2
|
|
- name: RSTCR
|
|
description: TimerA Reset Register
|
|
byte_offset: 84
|
|
fieldset: RSTCR
|
|
- name: CHPCR
|
|
description: Timerx Chopper Register
|
|
byte_offset: 88
|
|
fieldset: CHPCR
|
|
- name: CPT1CCR
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
byte_offset: 92
|
|
fieldset: CPT1CCR
|
|
- name: CPT2CCR
|
|
description: CPT2xCR
|
|
byte_offset: 96
|
|
fieldset: CPT2CCR
|
|
- name: OUTCR
|
|
description: Timerx Output Register
|
|
byte_offset: 100
|
|
fieldset: OUTCR
|
|
- name: FLTCR
|
|
description: Timerx Fault Register
|
|
byte_offset: 104
|
|
fieldset: FLTCR
|
|
block/HRTIM_TIMD:
|
|
description: "High Resolution Timer: TIMD"
|
|
items:
|
|
- name: TIMDCR
|
|
description: Timerx Control Register
|
|
byte_offset: 0
|
|
fieldset: TIMDCR
|
|
- name: TIMDISR
|
|
description: "Timerx Interrupt Status\r Register"
|
|
byte_offset: 4
|
|
access: Read
|
|
fieldset: TIMDISR
|
|
- name: TIMDICR
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
byte_offset: 8
|
|
access: Write
|
|
fieldset: TIMDICR
|
|
- name: TIMDDIER
|
|
description: TIMxDIER5
|
|
byte_offset: 12
|
|
fieldset: TIMDDIER
|
|
- name: CNTDR
|
|
description: Timerx Counter Register
|
|
byte_offset: 16
|
|
fieldset: CNTDR
|
|
- name: PERDR
|
|
description: Timerx Period Register
|
|
byte_offset: 20
|
|
fieldset: PERDR
|
|
- name: REPDR
|
|
description: Timerx Repetition Register
|
|
byte_offset: 24
|
|
fieldset: REPDR
|
|
- name: CMP1DR
|
|
description: Timerx Compare 1 Register
|
|
byte_offset: 28
|
|
fieldset: CMP1DR
|
|
- name: CMP1CDR
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
byte_offset: 32
|
|
fieldset: CMP1CDR
|
|
- name: CMP2DR
|
|
description: Timerx Compare 2 Register
|
|
byte_offset: 36
|
|
fieldset: CMP2DR
|
|
- name: CMP3DR
|
|
description: Timerx Compare 3 Register
|
|
byte_offset: 40
|
|
fieldset: CMP3DR
|
|
- name: CMP4DR
|
|
description: Timerx Compare 4 Register
|
|
byte_offset: 44
|
|
fieldset: CMP4DR
|
|
- name: CPT1DR
|
|
description: Timerx Capture 1 Register
|
|
byte_offset: 48
|
|
access: Read
|
|
fieldset: CPT1DR
|
|
- name: CPT2DR
|
|
description: Timerx Capture 2 Register
|
|
byte_offset: 52
|
|
access: Read
|
|
fieldset: CPT2DR
|
|
- name: DTDR
|
|
description: Timerx Deadtime Register
|
|
byte_offset: 56
|
|
fieldset: DTDR
|
|
- name: SETD1R
|
|
description: Timerx Output1 Set Register
|
|
byte_offset: 60
|
|
fieldset: SETD1R
|
|
- name: RSTD1R
|
|
description: Timerx Output1 Reset Register
|
|
byte_offset: 64
|
|
fieldset: RSTD1R
|
|
- name: SETD2R
|
|
description: Timerx Output2 Set Register
|
|
byte_offset: 68
|
|
fieldset: SETD2R
|
|
- name: RSTD2R
|
|
description: Timerx Output2 Reset Register
|
|
byte_offset: 72
|
|
fieldset: RSTD2R
|
|
- name: EEFDR1
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
byte_offset: 76
|
|
fieldset: EEFDR1
|
|
- name: EEFDR2
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
byte_offset: 80
|
|
fieldset: EEFDR2
|
|
- name: RSTDR
|
|
description: TimerA Reset Register
|
|
byte_offset: 84
|
|
fieldset: RSTDR
|
|
- name: CHPDR
|
|
description: Timerx Chopper Register
|
|
byte_offset: 88
|
|
fieldset: CHPDR
|
|
- name: CPT1DCR
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
byte_offset: 92
|
|
fieldset: CPT1DCR
|
|
- name: CPT2DCR
|
|
description: CPT2xCR
|
|
byte_offset: 96
|
|
fieldset: CPT2DCR
|
|
- name: OUTDR
|
|
description: Timerx Output Register
|
|
byte_offset: 100
|
|
fieldset: OUTDR
|
|
- name: FLTDR
|
|
description: Timerx Fault Register
|
|
byte_offset: 104
|
|
fieldset: FLTDR
|
|
block/HRTIM_TIME:
|
|
description: "High Resolution Timer: TIME"
|
|
items:
|
|
- name: TIMECR
|
|
description: Timerx Control Register
|
|
byte_offset: 0
|
|
fieldset: TIMECR
|
|
- name: TIMEISR
|
|
description: "Timerx Interrupt Status\r Register"
|
|
byte_offset: 4
|
|
access: Read
|
|
fieldset: TIMEISR
|
|
- name: TIMEICR
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
byte_offset: 8
|
|
access: Write
|
|
fieldset: TIMEICR
|
|
- name: TIMEDIER
|
|
description: TIMxDIER5
|
|
byte_offset: 12
|
|
fieldset: TIMEDIER
|
|
- name: CNTER
|
|
description: Timerx Counter Register
|
|
byte_offset: 16
|
|
fieldset: CNTER
|
|
- name: PERER
|
|
description: Timerx Period Register
|
|
byte_offset: 20
|
|
fieldset: PERER
|
|
- name: REPER
|
|
description: Timerx Repetition Register
|
|
byte_offset: 24
|
|
fieldset: REPER
|
|
- name: CMP1ER
|
|
description: Timerx Compare 1 Register
|
|
byte_offset: 28
|
|
fieldset: CMP1ER
|
|
- name: CMP1CER
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
byte_offset: 32
|
|
fieldset: CMP1CER
|
|
- name: CMP2ER
|
|
description: Timerx Compare 2 Register
|
|
byte_offset: 36
|
|
fieldset: CMP2ER
|
|
- name: CMP3ER
|
|
description: Timerx Compare 3 Register
|
|
byte_offset: 40
|
|
fieldset: CMP3ER
|
|
- name: CMP4ER
|
|
description: Timerx Compare 4 Register
|
|
byte_offset: 44
|
|
fieldset: CMP4ER
|
|
- name: CPT1ER
|
|
description: Timerx Capture 1 Register
|
|
byte_offset: 48
|
|
access: Read
|
|
fieldset: CPT1ER
|
|
- name: CPT2ER
|
|
description: Timerx Capture 2 Register
|
|
byte_offset: 52
|
|
access: Read
|
|
fieldset: CPT2ER
|
|
- name: DTER
|
|
description: Timerx Deadtime Register
|
|
byte_offset: 56
|
|
fieldset: DTER
|
|
- name: SETE1R
|
|
description: Timerx Output1 Set Register
|
|
byte_offset: 60
|
|
fieldset: SETE1R
|
|
- name: RSTE1R
|
|
description: Timerx Output1 Reset Register
|
|
byte_offset: 64
|
|
fieldset: RSTE1R
|
|
- name: SETE2R
|
|
description: Timerx Output2 Set Register
|
|
byte_offset: 68
|
|
fieldset: SETE2R
|
|
- name: RSTE2R
|
|
description: Timerx Output2 Reset Register
|
|
byte_offset: 72
|
|
fieldset: RSTE2R
|
|
- name: EEFER1
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
byte_offset: 76
|
|
fieldset: EEFER1
|
|
- name: EEFER2
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
byte_offset: 80
|
|
fieldset: EEFER2
|
|
- name: RSTER
|
|
description: TimerA Reset Register
|
|
byte_offset: 84
|
|
fieldset: RSTER
|
|
- name: CHPER
|
|
description: Timerx Chopper Register
|
|
byte_offset: 88
|
|
fieldset: CHPER
|
|
- name: CPT1ECR
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
byte_offset: 92
|
|
fieldset: CPT1ECR
|
|
- name: CPT2ECR
|
|
description: CPT2xCR
|
|
byte_offset: 96
|
|
fieldset: CPT2ECR
|
|
- name: OUTER
|
|
description: Timerx Output Register
|
|
byte_offset: 100
|
|
fieldset: OUTER
|
|
- name: FLTER
|
|
description: Timerx Fault Register
|
|
byte_offset: 104
|
|
fieldset: FLTER
|
|
fieldset/CHPAR:
|
|
description: Timerx Chopper Register
|
|
fields:
|
|
- name: CARFRQ
|
|
description: "Timerx carrier frequency\r value"
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: CARDTY
|
|
description: "Timerx chopper duty cycle\r value"
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: STRTPW
|
|
description: STRTPW
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
fieldset/CHPBR:
|
|
description: Timerx Chopper Register
|
|
fields:
|
|
- name: CARFRQ
|
|
description: "Timerx carrier frequency\r value"
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: CARDTY
|
|
description: "Timerx chopper duty cycle\r value"
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: STRTPW
|
|
description: STRTPW
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
fieldset/CHPCR:
|
|
description: Timerx Chopper Register
|
|
fields:
|
|
- name: CARFRQ
|
|
description: "Timerx carrier frequency\r value"
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: CARDTY
|
|
description: "Timerx chopper duty cycle\r value"
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: STRTPW
|
|
description: STRTPW
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
fieldset/CHPDR:
|
|
description: Timerx Chopper Register
|
|
fields:
|
|
- name: CARFRQ
|
|
description: "Timerx carrier frequency\r value"
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: CARDTY
|
|
description: "Timerx chopper duty cycle\r value"
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: STRTPW
|
|
description: STRTPW
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
fieldset/CHPER:
|
|
description: Timerx Chopper Register
|
|
fields:
|
|
- name: CARFRQ
|
|
description: "Timerx carrier frequency\r value"
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: CARDTY
|
|
description: "Timerx chopper duty cycle\r value"
|
|
bit_offset: 4
|
|
bit_size: 3
|
|
- name: STRTPW
|
|
description: STRTPW
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
fieldset/CMP1AR:
|
|
description: Timerx Compare 1 Register
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP1BR:
|
|
description: Timerx Compare 1 Register
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP1CAR:
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: REPx
|
|
description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)"
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/CMP1CBR:
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: REPx
|
|
description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)"
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/CMP1CCR:
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: REPx
|
|
description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)"
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/CMP1CDR:
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: REPx
|
|
description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)"
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/CMP1CER:
|
|
description: "Timerx Compare 1 Compound\r Register"
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
- name: REPx
|
|
description: "Timerx Repetition value (aliased from\r HRTIM_REPx register)"
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
fieldset/CMP1CR:
|
|
description: Timerx Compare 1 Register
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP1DR:
|
|
description: Timerx Compare 1 Register
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP1ER:
|
|
description: Timerx Compare 1 Register
|
|
fields:
|
|
- name: CMP1x
|
|
description: Timerx Compare 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP2AR:
|
|
description: Timerx Compare 2 Register
|
|
fields:
|
|
- name: CMP2x
|
|
description: Timerx Compare 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP2BR:
|
|
description: Timerx Compare 2 Register
|
|
fields:
|
|
- name: CMP2x
|
|
description: Timerx Compare 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP2CR:
|
|
description: Timerx Compare 2 Register
|
|
fields:
|
|
- name: CMP2x
|
|
description: Timerx Compare 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP2DR:
|
|
description: Timerx Compare 2 Register
|
|
fields:
|
|
- name: CMP2x
|
|
description: Timerx Compare 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP2ER:
|
|
description: Timerx Compare 2 Register
|
|
fields:
|
|
- name: CMP2x
|
|
description: Timerx Compare 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP3AR:
|
|
description: Timerx Compare 3 Register
|
|
fields:
|
|
- name: CMP3x
|
|
description: Timerx Compare 3 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP3BR:
|
|
description: Timerx Compare 3 Register
|
|
fields:
|
|
- name: CMP3x
|
|
description: Timerx Compare 3 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP3CR:
|
|
description: Timerx Compare 3 Register
|
|
fields:
|
|
- name: CMP3x
|
|
description: Timerx Compare 3 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP3DR:
|
|
description: Timerx Compare 3 Register
|
|
fields:
|
|
- name: CMP3x
|
|
description: Timerx Compare 3 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP3ER:
|
|
description: Timerx Compare 3 Register
|
|
fields:
|
|
- name: CMP3x
|
|
description: Timerx Compare 3 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP4AR:
|
|
description: Timerx Compare 4 Register
|
|
fields:
|
|
- name: CMP4x
|
|
description: Timerx Compare 4 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP4BR:
|
|
description: Timerx Compare 4 Register
|
|
fields:
|
|
- name: CMP4x
|
|
description: Timerx Compare 4 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP4CR:
|
|
description: Timerx Compare 4 Register
|
|
fields:
|
|
- name: CMP4x
|
|
description: Timerx Compare 4 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP4DR:
|
|
description: Timerx Compare 4 Register
|
|
fields:
|
|
- name: CMP4x
|
|
description: Timerx Compare 4 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CMP4ER:
|
|
description: Timerx Compare 4 Register
|
|
fields:
|
|
- name: CMP4x
|
|
description: Timerx Compare 4 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CNTAR:
|
|
description: Timerx Counter Register
|
|
fields:
|
|
- name: CNTx
|
|
description: Timerx Counter value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CNTBR:
|
|
description: Timerx Counter Register
|
|
fields:
|
|
- name: CNTx
|
|
description: Timerx Counter value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CNTCR:
|
|
description: Timerx Counter Register
|
|
fields:
|
|
- name: CNTx
|
|
description: Timerx Counter value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CNTDR:
|
|
description: Timerx Counter Register
|
|
fields:
|
|
- name: CNTx
|
|
description: Timerx Counter value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CNTER:
|
|
description: Timerx Counter Register
|
|
fields:
|
|
- name: CNTx
|
|
description: Timerx Counter value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT1ACR:
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT1AR:
|
|
description: Timerx Capture 1 Register
|
|
fields:
|
|
- name: CPT1x
|
|
description: Timerx Capture 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT1BCR:
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT1BR:
|
|
description: Timerx Capture 1 Register
|
|
fields:
|
|
- name: CPT1x
|
|
description: Timerx Capture 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT1CCR:
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT1CR:
|
|
description: Timerx Capture 1 Register
|
|
fields:
|
|
- name: CPT1x
|
|
description: Timerx Capture 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT1DCR:
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT1DR:
|
|
description: Timerx Capture 1 Register
|
|
fields:
|
|
- name: CPT1x
|
|
description: Timerx Capture 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT1ECR:
|
|
description: "Timerx Capture 2 Control\r Register"
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT1ER:
|
|
description: Timerx Capture 1 Register
|
|
fields:
|
|
- name: CPT1x
|
|
description: Timerx Capture 1 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT2ACR:
|
|
description: CPT2xCR
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT2AR:
|
|
description: Timerx Capture 2 Register
|
|
fields:
|
|
- name: CPT2x
|
|
description: Timerx Capture 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT2BCR:
|
|
description: CPT2xCR
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT2BR:
|
|
description: Timerx Capture 2 Register
|
|
fields:
|
|
- name: CPT2x
|
|
description: Timerx Capture 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT2CCR:
|
|
description: CPT2xCR
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT2CR:
|
|
description: Timerx Capture 2 Register
|
|
fields:
|
|
- name: CPT2x
|
|
description: Timerx Capture 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT2DCR:
|
|
description: CPT2xCR
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1SET
|
|
description: Timer E output 1 Set
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TE1RST
|
|
description: Timer E output 1 Reset
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT2DR:
|
|
description: Timerx Capture 2 Register
|
|
fields:
|
|
- name: CPT2x
|
|
description: Timerx Capture 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/CPT2ECR:
|
|
description: CPT2xCR
|
|
fields:
|
|
- name: SWCPT
|
|
description: Software Capture
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: UPDCPT
|
|
description: Update Capture
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV1CPT
|
|
description: External Event 1 Capture
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV2CPT
|
|
description: External Event 2 Capture
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV3CPT
|
|
description: External Event 3 Capture
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV4CPT
|
|
description: External Event 4 Capture
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV5CPT
|
|
description: External Event 5 Capture
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV6CPT
|
|
description: External Event 6 Capture
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV7CPT
|
|
description: External Event 7 Capture
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV8CPT
|
|
description: External Event 8 Capture
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV9CPT
|
|
description: External Event 9 Capture
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: EXEV10CPT
|
|
description: External Event 10 Capture
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1SET
|
|
description: Timer A output 1 Set
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TA1RST
|
|
description: Timer A output 1 Reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1SET
|
|
description: Timer B output 1 Set
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TB1RST
|
|
description: Timer B output 1 Reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1SET
|
|
description: Timer C output 1 Set
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TC1RST
|
|
description: Timer C output 1 Reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1SET
|
|
description: Timer D output 1 Set
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TD1RST
|
|
description: Timer D output 1 Reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
- name: TDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: CPTXXCR_XXXXX
|
|
fieldset/CPT2ER:
|
|
description: Timerx Capture 2 Register
|
|
fields:
|
|
- name: CPT2x
|
|
description: Timerx Capture 2 value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/DTAR:
|
|
description: Timerx Deadtime Register
|
|
fields:
|
|
- name: DTRx
|
|
description: Deadtime Rising value
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
- name: SDTRx
|
|
description: Sign Deadtime Rising value
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SDTRx
|
|
- name: DTPRSC
|
|
description: Deadtime Prescaler
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
- name: DTRSLKx
|
|
description: Deadtime Rising Sign Lock
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTRLKx
|
|
description: Deadtime Rising Lock
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFx
|
|
description: Deadtime Falling value
|
|
bit_offset: 16
|
|
bit_size: 9
|
|
- name: SDTFx
|
|
description: "Sign Deadtime Falling\r value"
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SDTFx
|
|
- name: DTFSLKx
|
|
description: Deadtime Falling Sign Lock
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFLKx
|
|
description: Deadtime Falling Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/DTBR:
|
|
description: Timerx Deadtime Register
|
|
fields:
|
|
- name: DTRx
|
|
description: Deadtime Rising value
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
- name: SDTRx
|
|
description: Sign Deadtime Rising value
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SDTRx
|
|
- name: DTPRSC
|
|
description: Deadtime Prescaler
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
- name: DTRSLKx
|
|
description: Deadtime Rising Sign Lock
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTRLKx
|
|
description: Deadtime Rising Lock
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFx
|
|
description: Deadtime Falling value
|
|
bit_offset: 16
|
|
bit_size: 9
|
|
- name: SDTFx
|
|
description: "Sign Deadtime Falling\r value"
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SDTFx
|
|
- name: DTFSLKx
|
|
description: Deadtime Falling Sign Lock
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFLKx
|
|
description: Deadtime Falling Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/DTCR:
|
|
description: Timerx Deadtime Register
|
|
fields:
|
|
- name: DTRx
|
|
description: Deadtime Rising value
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
- name: SDTRx
|
|
description: Sign Deadtime Rising value
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SDTRx
|
|
- name: DTPRSC
|
|
description: Deadtime Prescaler
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
- name: DTRSLKx
|
|
description: Deadtime Rising Sign Lock
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTRLKx
|
|
description: Deadtime Rising Lock
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFx
|
|
description: Deadtime Falling value
|
|
bit_offset: 16
|
|
bit_size: 9
|
|
- name: SDTFx
|
|
description: "Sign Deadtime Falling\r value"
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SDTFx
|
|
- name: DTFSLKx
|
|
description: Deadtime Falling Sign Lock
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFLKx
|
|
description: Deadtime Falling Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/DTDR:
|
|
description: Timerx Deadtime Register
|
|
fields:
|
|
- name: DTRx
|
|
description: Deadtime Rising value
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
- name: SDTRx
|
|
description: Sign Deadtime Rising value
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SDTRx
|
|
- name: DTPRSC
|
|
description: Deadtime Prescaler
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
- name: DTRSLKx
|
|
description: Deadtime Rising Sign Lock
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTRLKx
|
|
description: Deadtime Rising Lock
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFx
|
|
description: Deadtime Falling value
|
|
bit_offset: 16
|
|
bit_size: 9
|
|
- name: SDTFx
|
|
description: "Sign Deadtime Falling\r value"
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SDTFx
|
|
- name: DTFSLKx
|
|
description: Deadtime Falling Sign Lock
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFLKx
|
|
description: Deadtime Falling Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/DTER:
|
|
description: Timerx Deadtime Register
|
|
fields:
|
|
- name: DTRx
|
|
description: Deadtime Rising value
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
- name: SDTRx
|
|
description: Sign Deadtime Rising value
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SDTRx
|
|
- name: DTPRSC
|
|
description: Deadtime Prescaler
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
- name: DTRSLKx
|
|
description: Deadtime Rising Sign Lock
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTRLKx
|
|
description: Deadtime Rising Lock
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFx
|
|
description: Deadtime Falling value
|
|
bit_offset: 16
|
|
bit_size: 9
|
|
- name: SDTFx
|
|
description: "Sign Deadtime Falling\r value"
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SDTFx
|
|
- name: DTFSLKx
|
|
description: Deadtime Falling Sign Lock
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
- name: DTFLKx
|
|
description: Deadtime Falling Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/EEFAR1:
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
fields:
|
|
- name: EE1LTCH
|
|
description: External Event 1 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE1FLTR
|
|
description: External Event 1 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE2LTCH
|
|
description: External Event 2 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE2FLTR
|
|
description: External Event 2 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE3LTCH
|
|
description: External Event 3 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE3FLTR
|
|
description: External Event 3 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE4LTCH
|
|
description: External Event 4 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE4FLTR
|
|
description: External Event 4 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE5LTCH
|
|
description: External Event 5 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE5FLTR
|
|
description: External Event 5 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
fieldset/EEFAR2:
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
fields:
|
|
- name: EE6LTCH
|
|
description: External Event 6 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE6FLTR
|
|
description: External Event 6 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE7LTCH
|
|
description: External Event 7 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE7FLTR
|
|
description: External Event 7 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE8LTCH
|
|
description: External Event 8 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE8FLTR
|
|
description: External Event 8 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE9LTCH
|
|
description: External Event 9 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE9FLTR
|
|
description: External Event 9 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE10LTCH
|
|
description: External Event 10 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE10FLTR
|
|
description: External Event 10 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
fieldset/EEFBR1:
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
fields:
|
|
- name: EE1LTCH
|
|
description: External Event 1 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE1FLTR
|
|
description: External Event 1 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE2LTCH
|
|
description: External Event 2 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE2FLTR
|
|
description: External Event 2 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE3LTCH
|
|
description: External Event 3 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE3FLTR
|
|
description: External Event 3 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE4LTCH
|
|
description: External Event 4 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE4FLTR
|
|
description: External Event 4 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE5LTCH
|
|
description: External Event 5 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE5FLTR
|
|
description: External Event 5 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
fieldset/EEFBR2:
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
fields:
|
|
- name: EE6LTCH
|
|
description: External Event 6 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE6FLTR
|
|
description: External Event 6 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE7LTCH
|
|
description: External Event 7 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE7FLTR
|
|
description: External Event 7 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE8LTCH
|
|
description: External Event 8 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE8FLTR
|
|
description: External Event 8 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE9LTCH
|
|
description: External Event 9 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE9FLTR
|
|
description: External Event 9 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE10LTCH
|
|
description: External Event 10 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE10FLTR
|
|
description: External Event 10 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
fieldset/EEFCR1:
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
fields:
|
|
- name: EE1LTCH
|
|
description: External Event 1 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE1FLTR
|
|
description: External Event 1 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE2LTCH
|
|
description: External Event 2 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE2FLTR
|
|
description: External Event 2 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE3LTCH
|
|
description: External Event 3 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE3FLTR
|
|
description: External Event 3 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE4LTCH
|
|
description: External Event 4 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE4FLTR
|
|
description: External Event 4 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE5LTCH
|
|
description: External Event 5 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE5FLTR
|
|
description: External Event 5 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
fieldset/EEFCR2:
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
fields:
|
|
- name: EE6LTCH
|
|
description: External Event 6 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE6FLTR
|
|
description: External Event 6 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE7LTCH
|
|
description: External Event 7 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE7FLTR
|
|
description: External Event 7 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE8LTCH
|
|
description: External Event 8 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE8FLTR
|
|
description: External Event 8 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE9LTCH
|
|
description: External Event 9 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE9FLTR
|
|
description: External Event 9 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE10LTCH
|
|
description: External Event 10 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE10FLTR
|
|
description: External Event 10 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
fieldset/EEFDR1:
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
fields:
|
|
- name: EE1LTCH
|
|
description: External Event 1 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE1FLTR
|
|
description: External Event 1 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE2LTCH
|
|
description: External Event 2 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE2FLTR
|
|
description: External Event 2 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE3LTCH
|
|
description: External Event 3 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE3FLTR
|
|
description: External Event 3 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE4LTCH
|
|
description: External Event 4 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE4FLTR
|
|
description: External Event 4 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE5LTCH
|
|
description: External Event 5 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE5FLTR
|
|
description: External Event 5 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
fieldset/EEFDR2:
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
fields:
|
|
- name: EE6LTCH
|
|
description: External Event 6 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE6FLTR
|
|
description: External Event 6 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE7LTCH
|
|
description: External Event 7 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE7FLTR
|
|
description: External Event 7 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE8LTCH
|
|
description: External Event 8 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE8FLTR
|
|
description: External Event 8 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE9LTCH
|
|
description: External Event 9 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE9FLTR
|
|
description: External Event 9 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE10LTCH
|
|
description: External Event 10 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE10FLTR
|
|
description: External Event 10 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
fieldset/EEFER1:
|
|
description: "Timerx External Event Filtering Register\r 1"
|
|
fields:
|
|
- name: EE1LTCH
|
|
description: External Event 1 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE1FLTR
|
|
description: External Event 1 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE2LTCH
|
|
description: External Event 2 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE2FLTR
|
|
description: External Event 2 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE3LTCH
|
|
description: External Event 3 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE3FLTR
|
|
description: External Event 3 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE4LTCH
|
|
description: External Event 4 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE4FLTR
|
|
description: External Event 4 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
- name: EE5LTCH
|
|
description: External Event 5 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE5FLTR
|
|
description: External Event 5 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE1FLTR
|
|
fieldset/EEFER2:
|
|
description: "Timerx External Event Filtering Register\r 2"
|
|
fields:
|
|
- name: EE6LTCH
|
|
description: External Event 6 latch
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EE6FLTR
|
|
description: External Event 6 filter
|
|
bit_offset: 1
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE7LTCH
|
|
description: External Event 7 latch
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: EE7FLTR
|
|
description: External Event 7 filter
|
|
bit_offset: 7
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE8LTCH
|
|
description: External Event 8 latch
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: EE8FLTR
|
|
description: External Event 8 filter
|
|
bit_offset: 13
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE9LTCH
|
|
description: External Event 9 latch
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: EE9FLTR
|
|
description: External Event 9 filter
|
|
bit_offset: 19
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
- name: EE10LTCH
|
|
description: External Event 10 latch
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: EE10FLTR
|
|
description: External Event 10 filter
|
|
bit_offset: 25
|
|
bit_size: 4
|
|
enum: EE6FLTR
|
|
fieldset/FLTAR:
|
|
description: Timerx Fault Register
|
|
fields:
|
|
- name: FLT1EN
|
|
description: Fault 1 enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT2EN
|
|
description: Fault 2 enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT3EN
|
|
description: Fault 3 enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT4EN
|
|
description: Fault 4 enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT5EN
|
|
description: Fault 5 enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLTLCK
|
|
description: Fault sources Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/FLTBR:
|
|
description: Timerx Fault Register
|
|
fields:
|
|
- name: FLT1EN
|
|
description: Fault 1 enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT2EN
|
|
description: Fault 2 enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT3EN
|
|
description: Fault 3 enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT4EN
|
|
description: Fault 4 enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT5EN
|
|
description: Fault 5 enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLTLCK
|
|
description: Fault sources Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/FLTCR:
|
|
description: Timerx Fault Register
|
|
fields:
|
|
- name: FLT1EN
|
|
description: Fault 1 enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT2EN
|
|
description: Fault 2 enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT3EN
|
|
description: Fault 3 enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT4EN
|
|
description: Fault 4 enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT5EN
|
|
description: Fault 5 enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLTLCK
|
|
description: Fault sources Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/FLTDR:
|
|
description: Timerx Fault Register
|
|
fields:
|
|
- name: FLT1EN
|
|
description: Fault 1 enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT2EN
|
|
description: Fault 2 enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT3EN
|
|
description: Fault 3 enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT4EN
|
|
description: Fault 4 enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT5EN
|
|
description: Fault 5 enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLTLCK
|
|
description: Fault sources Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/FLTER:
|
|
description: Timerx Fault Register
|
|
fields:
|
|
- name: FLT1EN
|
|
description: Fault 1 enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT2EN
|
|
description: Fault 2 enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT3EN
|
|
description: Fault 3 enable
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT4EN
|
|
description: Fault 4 enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLT5EN
|
|
description: Fault 5 enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: FLT1EN
|
|
- name: FLTLCK
|
|
description: Fault sources Lock
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: LOCKED
|
|
fieldset/MCMP1R:
|
|
description: "Master Timer Compare 1\r Register"
|
|
fields:
|
|
- name: MCMP1
|
|
description: "Master Timer Compare 1\r value"
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/MCMP2R:
|
|
description: "Master Timer Compare 2\r Register"
|
|
fields:
|
|
- name: MCMP2
|
|
description: "Master Timer Compare 2\r value"
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/MCMP3R:
|
|
description: "Master Timer Compare 3\r Register"
|
|
fields:
|
|
- name: MCMP3
|
|
description: "Master Timer Compare 3\r value"
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/MCMP4R:
|
|
description: "Master Timer Compare 4\r Register"
|
|
fields:
|
|
- name: MCMP4
|
|
description: "Master Timer Compare 4\r value"
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/MCNTR:
|
|
description: Master Timer Counter Register
|
|
fields:
|
|
- name: MCNT
|
|
description: Counter value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/MCR:
|
|
description: Master Timer Control Register
|
|
fields:
|
|
- name: CKPSC
|
|
description: "HRTIM Master Clock\r prescaler"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: CONT
|
|
description: Master Continuous mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CONT
|
|
- name: RETRIG
|
|
description: Master Re-triggerable mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HALF
|
|
description: Half mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: SYNCIN
|
|
description: ynchronization input
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: SYNCIN
|
|
- name: SYNCRSTM
|
|
description: "Synchronization Resets\r Master"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SYNCSTRTM
|
|
description: "Synchronization Starts\r Master"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SYNCOUT
|
|
description: Synchronization output
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: SYNCOUT
|
|
- name: SYNCSRC
|
|
description: Synchronization source
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
enum: SYNCSRC
|
|
- name: MCEN
|
|
description: Master Counter enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TACEN
|
|
description: Timer A counter enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TBCEN
|
|
description: Timer B counter enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TCCEN
|
|
description: Timer C counter enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: TDCEN
|
|
description: Timer D counter enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TECEN
|
|
description: Timer E counter enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: MREPU
|
|
description: "Master Timer Repetition\r update"
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: BRSTDMA
|
|
description: Burst DMA Update
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
enum: BRSTDMA
|
|
fieldset/MDIER:
|
|
description: MDIER4
|
|
fields:
|
|
- name: MCMP1IE
|
|
description: MCMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: MCMP2IE
|
|
description: MCMP2IE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: MCMP3IE
|
|
description: MCMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: MCMP4IE
|
|
description: MCMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: MREPIE
|
|
description: MREPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: SYNCIE
|
|
description: SYNCIE
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: MUPDIE
|
|
description: MUPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: MCMP1DE
|
|
description: MCMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: MCMP2DE
|
|
description: MCMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: MCMP3DE
|
|
description: MCMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: MCMP4DE
|
|
description: MCMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: MREPDE
|
|
description: MREPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SYNCDE
|
|
description: SYNCDE
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: MUPDDE
|
|
description: MUPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
fieldset/MICR:
|
|
description: "Master Timer Interrupt Clear\r Register"
|
|
fields:
|
|
- name: MCMP1C
|
|
description: "Master Compare 1 Interrupt flag\r clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MCMP2C
|
|
description: "Master Compare 2 Interrupt flag\r clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MCMP3C
|
|
description: "Master Compare 3 Interrupt flag\r clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MCMP4C
|
|
description: "Master Compare 4 Interrupt flag\r clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MREPC
|
|
description: "Repetition Interrupt flag\r clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: SYNCC
|
|
description: "Sync Input Interrupt flag\r clear"
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
- name: MUPDC
|
|
description: "Master update Interrupt flag\r clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: MCMP1C
|
|
fieldset/MISR:
|
|
description: "Master Timer Interrupt Status\r Register"
|
|
fields:
|
|
- name: MCMP1
|
|
description: "Master Compare 1 Interrupt\r Flag"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MCMP2
|
|
description: "Master Compare 2 Interrupt\r Flag"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MCMP3
|
|
description: "Master Compare 3 Interrupt\r Flag"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MCMP4
|
|
description: "Master Compare 4 Interrupt\r Flag"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MREP
|
|
description: "Master Repetition Interrupt\r Flag"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SYNC
|
|
description: Sync Input Interrupt Flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: MUPD
|
|
description: "Master Update Interrupt\r Flag"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
fieldset/MPER:
|
|
description: Master Timer Period Register
|
|
fields:
|
|
- name: MPER
|
|
description: Master Timer Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/MREP:
|
|
description: "Master Timer Repetition\r Register"
|
|
fields:
|
|
- name: MREP
|
|
description: "Master Timer Repetition counter\r value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/OUTAR:
|
|
description: Timerx Output Register
|
|
fields:
|
|
- name: POL1
|
|
description: Output 1 polarity
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM1
|
|
description: Output 1 Idle mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES1
|
|
description: Output 1 Idle State
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT1
|
|
description: Output 1 Fault state
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP1
|
|
description: Output 1 Chopper enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: DIDL1
|
|
description: "Output 1 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: DTEN
|
|
description: Deadtime enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: DLYPRTEN
|
|
description: Delayed Protection Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: DLYPRT
|
|
description: Delayed Protection
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: OUTAR_DLYPRT
|
|
- name: POL2
|
|
description: Output 2 polarity
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM2
|
|
description: Output 2 Idle mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES2
|
|
description: Output 2 Idle State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT2
|
|
description: Output 2 Fault state
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP2
|
|
description: Output 2 Chopper enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: DIDL2
|
|
description: "Output 2 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/OUTBR:
|
|
description: Timerx Output Register
|
|
fields:
|
|
- name: POL1
|
|
description: Output 1 polarity
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM1
|
|
description: Output 1 Idle mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES1
|
|
description: Output 1 Idle State
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT1
|
|
description: Output 1 Fault state
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP1
|
|
description: Output 1 Chopper enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: DIDL1
|
|
description: "Output 1 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: DTEN
|
|
description: Deadtime enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: DLYPRTEN
|
|
description: Delayed Protection Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: DLYPRT
|
|
description: Delayed Protection
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: OUTBR_DLYPRT
|
|
- name: POL2
|
|
description: Output 2 polarity
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM2
|
|
description: Output 2 Idle mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES2
|
|
description: Output 2 Idle State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT2
|
|
description: Output 2 Fault state
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP2
|
|
description: Output 2 Chopper enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: DIDL2
|
|
description: "Output 2 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/OUTCR:
|
|
description: Timerx Output Register
|
|
fields:
|
|
- name: POL1
|
|
description: Output 1 polarity
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM1
|
|
description: Output 1 Idle mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES1
|
|
description: Output 1 Idle State
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT1
|
|
description: Output 1 Fault state
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP1
|
|
description: Output 1 Chopper enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: DIDL1
|
|
description: "Output 1 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: DTEN
|
|
description: Deadtime enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: DLYPRTEN
|
|
description: Delayed Protection Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: DLYPRT
|
|
description: Delayed Protection
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: OUTCR_DLYPRT
|
|
- name: POL2
|
|
description: Output 2 polarity
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM2
|
|
description: Output 2 Idle mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES2
|
|
description: Output 2 Idle State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT2
|
|
description: Output 2 Fault state
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP2
|
|
description: Output 2 Chopper enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: DIDL2
|
|
description: "Output 2 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/OUTDR:
|
|
description: Timerx Output Register
|
|
fields:
|
|
- name: POL1
|
|
description: Output 1 polarity
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM1
|
|
description: Output 1 Idle mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES1
|
|
description: Output 1 Idle State
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT1
|
|
description: Output 1 Fault state
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP1
|
|
description: Output 1 Chopper enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: DIDL1
|
|
description: "Output 1 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: DTEN
|
|
description: Deadtime enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: DLYPRTEN
|
|
description: Delayed Protection Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: DLYPRT
|
|
description: Delayed Protection
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: OUTDR_DLYPRT
|
|
- name: POL2
|
|
description: Output 2 polarity
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM2
|
|
description: Output 2 Idle mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES2
|
|
description: Output 2 Idle State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT2
|
|
description: Output 2 Fault state
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP2
|
|
description: Output 2 Chopper enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: DIDL2
|
|
description: "Output 2 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/OUTER:
|
|
description: Timerx Output Register
|
|
fields:
|
|
- name: POL1
|
|
description: Output 1 polarity
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM1
|
|
description: Output 1 Idle mode
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES1
|
|
description: Output 1 Idle State
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT1
|
|
description: Output 1 Fault state
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP1
|
|
description: Output 1 Chopper enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: DIDL1
|
|
description: "Output 1 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: DTEN
|
|
description: Deadtime enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: DLYPRTEN
|
|
description: Delayed Protection Enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: DLYPRT
|
|
description: Delayed Protection
|
|
bit_offset: 10
|
|
bit_size: 3
|
|
enum: OUTER_DLYPRT
|
|
- name: POL2
|
|
description: Output 2 polarity
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: POL1
|
|
- name: IDLEM2
|
|
description: Output 2 Idle mode
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: IDLEM1
|
|
- name: IDLES2
|
|
description: Output 2 Idle State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: IDLES1
|
|
- name: FAULT2
|
|
description: Output 2 Fault state
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
enum: FAULT1
|
|
- name: CHP2
|
|
description: Output 2 Chopper enable
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: DIDL2
|
|
description: "Output 2 Deadtime upon burst mode Idle\r entry"
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/PERAR:
|
|
description: Timerx Period Register
|
|
fields:
|
|
- name: PERx
|
|
description: Timerx Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/PERBR:
|
|
description: Timerx Period Register
|
|
fields:
|
|
- name: PERx
|
|
description: Timerx Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/PERCR:
|
|
description: Timerx Period Register
|
|
fields:
|
|
- name: PERx
|
|
description: Timerx Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/PERDR:
|
|
description: Timerx Period Register
|
|
fields:
|
|
- name: PERx
|
|
description: Timerx Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/PERER:
|
|
description: Timerx Period Register
|
|
fields:
|
|
- name: PERx
|
|
description: Timerx Period value
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/REPAR:
|
|
description: Timerx Repetition Register
|
|
fields:
|
|
- name: REPx
|
|
description: "Timerx Repetition counter\r value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/REPBR:
|
|
description: Timerx Repetition Register
|
|
fields:
|
|
- name: REPx
|
|
description: "Timerx Repetition counter\r value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/REPCR:
|
|
description: Timerx Repetition Register
|
|
fields:
|
|
- name: REPx
|
|
description: "Timerx Repetition counter\r value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/REPDR:
|
|
description: Timerx Repetition Register
|
|
fields:
|
|
- name: REPx
|
|
description: "Timerx Repetition counter\r value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/REPER:
|
|
description: Timerx Repetition Register
|
|
fields:
|
|
- name: REPx
|
|
description: "Timerx Repetition counter\r value"
|
|
bit_offset: 0
|
|
bit_size: 8
|
|
fieldset/RSTA1R:
|
|
description: Timerx Output1 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTA2R:
|
|
description: Timerx Output2 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTAR:
|
|
description: TimerA Reset Register
|
|
fields:
|
|
- name: UPDT
|
|
description: Timer A Update reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: UPDT
|
|
- name: CMP2
|
|
description: Timer A compare 2 reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: CMP4
|
|
description: Timer A compare 4 reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: MSTPER
|
|
description: Master timer Period
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: RSTAR_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master compare 1
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: RSTAR_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master compare 2
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: RSTAR_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master compare 3
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: RSTAR_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master compare 4
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: RSTAR_MSTCMP1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: RSTAR_EXTEVNT1
|
|
- name: TIMBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMBCMP4
|
|
description: Timer B Compare 4
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMCCMP4
|
|
description: Timer C Compare 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMDCMP4
|
|
description: Timer D Compare 4
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
- name: TIMECMP4
|
|
description: Timer E Compare 4
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: TIMBCMP1
|
|
fieldset/RSTB1R:
|
|
description: Timerx Output1 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTB2R:
|
|
description: Timerx Output2 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTBR:
|
|
description: TimerA Reset Register
|
|
fields:
|
|
- name: UPDT
|
|
description: Timer A Update reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: UPDT
|
|
- name: CMP2
|
|
description: Timer A compare 2 reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: CMP4
|
|
description: Timer A compare 4 reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: MSTPER
|
|
description: Master timer Period
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: RSTBR_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master compare 1
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: RSTBR_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master compare 2
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: RSTBR_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master compare 3
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: RSTBR_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master compare 4
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: RSTBR_MSTCMP1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: RSTBR_EXTEVNT1
|
|
- name: TIMACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP4
|
|
description: Timer A Compare 4
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP4
|
|
description: Timer C Compare 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP4
|
|
description: Timer D Compare 4
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP4
|
|
description: Timer E Compare 4
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
fieldset/RSTC1R:
|
|
description: Timerx Output1 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTC2R:
|
|
description: Timerx Output2 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTCR:
|
|
description: TimerA Reset Register
|
|
fields:
|
|
- name: UPDT
|
|
description: Timer A Update reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: UPDT
|
|
- name: CMP2
|
|
description: Timer A compare 2 reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: CMP4
|
|
description: Timer A compare 4 reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: MSTPER
|
|
description: Master timer Period
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: RSTCR_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master compare 1
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: RSTCR_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master compare 2
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: RSTCR_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master compare 3
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: RSTCR_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master compare 4
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: RSTCR_MSTCMP1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: RSTCR_EXTEVNT1
|
|
- name: TIMACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP4
|
|
description: Timer A Compare 4
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP4
|
|
description: Timer B Compare 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP4
|
|
description: Timer D Compare 4
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP4
|
|
description: Timer E Compare 4
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
fieldset/RSTD1R:
|
|
description: Timerx Output1 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTD2R:
|
|
description: Timerx Output2 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTDR:
|
|
description: TimerA Reset Register
|
|
fields:
|
|
- name: UPDT
|
|
description: Timer A Update reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: UPDT
|
|
- name: CMP2
|
|
description: Timer A compare 2 reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: CMP4
|
|
description: Timer A compare 4 reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: MSTPER
|
|
description: Master timer Period
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: RSTDR_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master compare 1
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: RSTDR_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master compare 2
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: RSTDR_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master compare 3
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: RSTDR_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master compare 4
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: RSTDR_MSTCMP1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: RSTDR_EXTEVNT1
|
|
- name: TIMACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP4
|
|
description: Timer A Compare 4
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP4
|
|
description: Timer B Compare 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP4
|
|
description: Timer C Compare 4
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP1
|
|
description: Timer E Compare 1
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP2
|
|
description: Timer E Compare 2
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMECMP4
|
|
description: Timer E Compare 4
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
fieldset/RSTE1R:
|
|
description: Timerx Output1 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTE2R:
|
|
description: Timerx Output2 Reset Register
|
|
fields:
|
|
- name: SRT
|
|
description: SRT
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: EFFECT
|
|
fieldset/RSTER:
|
|
description: TimerA Reset Register
|
|
fields:
|
|
- name: UPDT
|
|
description: Timer A Update reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: UPDT
|
|
- name: CMP2
|
|
description: Timer A compare 2 reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: CMP4
|
|
description: Timer A compare 4 reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CMP2
|
|
- name: MSTPER
|
|
description: Master timer Period
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: RSTER_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master compare 1
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: RSTER_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master compare 2
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: RSTER_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master compare 3
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: RSTER_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master compare 4
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: RSTER_MSTCMP1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: RSTER_EXTEVNT1
|
|
- name: TIMACMP1
|
|
description: Timer A Compare 1
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP2
|
|
description: Timer A Compare 2
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMACMP4
|
|
description: Timer A Compare 4
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP1
|
|
description: Timer B Compare 1
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP2
|
|
description: Timer B Compare 2
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMBCMP4
|
|
description: Timer B Compare 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP1
|
|
description: Timer C Compare 1
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP2
|
|
description: Timer C Compare 2
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMCCMP4
|
|
description: Timer C Compare 4
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP1
|
|
description: Timer D Compare 1
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP2
|
|
description: Timer D Compare 2
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
- name: TIMDCMP4
|
|
description: Timer D Compare 4
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: TIMACMP1
|
|
fieldset/SETA1R:
|
|
description: Timerx Output1 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: Software Set trigger
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETA1R_SST
|
|
- name: RESYNC
|
|
description: Timer A resynchronizaton
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETA1R_RESYNC
|
|
- name: PER
|
|
description: Timer A Period
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETA1R_PER
|
|
- name: CMP1
|
|
description: Timer A compare 1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETA1R_CMP1
|
|
- name: CMP2
|
|
description: Timer A compare 2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETA1R_CMP1
|
|
- name: CMP3
|
|
description: Timer A compare 3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETA1R_CMP1
|
|
- name: CMP4
|
|
description: Timer A compare 4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETA1R_CMP1
|
|
- name: MSTPER
|
|
description: Master Period
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETA1R_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master Compare 1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETA1R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master Compare 2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETA1R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master Compare 3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETA1R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master Compare 4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETA1R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: Timer Event 1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: Timer Event 2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: Timer Event 3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: Timer Event 4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: Timer Event 5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: Timer Event 6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: Timer Event 7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: Timer Event 8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: Timer Event 9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETA1R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETA1R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: "Registers update (transfer preload to\r active)"
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETA1R_UPDATE
|
|
fieldset/SETA2R:
|
|
description: Timerx Output2 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: SST
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETA2R_SST
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETA2R_RESYNC
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETA2R_PER
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETA2R_CMP1
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETA2R_CMP1
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETA2R_CMP1
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETA2R_CMP1
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETA2R_MSTPER
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETA2R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETA2R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETA2R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETA2R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETA2R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETA2R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETA2R_UPDATE
|
|
fieldset/SETB1R:
|
|
description: Timerx Output1 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: Software Set trigger
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETB1R_SST
|
|
- name: RESYNC
|
|
description: Timer A resynchronizaton
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETB1R_RESYNC
|
|
- name: PER
|
|
description: Timer A Period
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETB1R_PER
|
|
- name: CMP1
|
|
description: Timer A compare 1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETB1R_CMP1
|
|
- name: CMP2
|
|
description: Timer A compare 2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETB1R_CMP1
|
|
- name: CMP3
|
|
description: Timer A compare 3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETB1R_CMP1
|
|
- name: CMP4
|
|
description: Timer A compare 4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETB1R_CMP1
|
|
- name: MSTPER
|
|
description: Master Period
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETB1R_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master Compare 1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETB1R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master Compare 2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETB1R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master Compare 3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETB1R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master Compare 4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETB1R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: Timer Event 1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: Timer Event 2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: Timer Event 3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: Timer Event 4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: Timer Event 5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: Timer Event 6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: Timer Event 7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: Timer Event 8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: Timer Event 9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETB1R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETB1R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: "Registers update (transfer preload to\r active)"
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETB1R_UPDATE
|
|
fieldset/SETB2R:
|
|
description: Timerx Output2 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: SST
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETB2R_SST
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETB2R_RESYNC
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETB2R_PER
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETB2R_CMP1
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETB2R_CMP1
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETB2R_CMP1
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETB2R_CMP1
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETB2R_MSTPER
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETB2R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETB2R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETB2R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETB2R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETB2R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETB2R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETB2R_UPDATE
|
|
fieldset/SETC1R:
|
|
description: Timerx Output1 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: Software Set trigger
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETC1R_SST
|
|
- name: RESYNC
|
|
description: Timer A resynchronizaton
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETC1R_RESYNC
|
|
- name: PER
|
|
description: Timer A Period
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETC1R_PER
|
|
- name: CMP1
|
|
description: Timer A compare 1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETC1R_CMP1
|
|
- name: CMP2
|
|
description: Timer A compare 2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETC1R_CMP1
|
|
- name: CMP3
|
|
description: Timer A compare 3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETC1R_CMP1
|
|
- name: CMP4
|
|
description: Timer A compare 4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETC1R_CMP1
|
|
- name: MSTPER
|
|
description: Master Period
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETC1R_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master Compare 1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETC1R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master Compare 2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETC1R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master Compare 3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETC1R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master Compare 4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETC1R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: Timer Event 1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: Timer Event 2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: Timer Event 3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: Timer Event 4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: Timer Event 5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: Timer Event 6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: Timer Event 7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: Timer Event 8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: Timer Event 9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETC1R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETC1R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: "Registers update (transfer preload to\r active)"
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETC1R_UPDATE
|
|
fieldset/SETC2R:
|
|
description: Timerx Output2 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: SST
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETC2R_SST
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETC2R_RESYNC
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETC2R_PER
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETC2R_CMP1
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETC2R_CMP1
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETC2R_CMP1
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETC2R_CMP1
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETC2R_MSTPER
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETC2R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETC2R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETC2R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETC2R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETC2R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETC2R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETC2R_UPDATE
|
|
fieldset/SETD1R:
|
|
description: Timerx Output1 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: Software Set trigger
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETD1R_SST
|
|
- name: RESYNC
|
|
description: Timer A resynchronizaton
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETD1R_RESYNC
|
|
- name: PER
|
|
description: Timer A Period
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETD1R_PER
|
|
- name: CMP1
|
|
description: Timer A compare 1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETD1R_CMP1
|
|
- name: CMP2
|
|
description: Timer A compare 2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETD1R_CMP1
|
|
- name: CMP3
|
|
description: Timer A compare 3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETD1R_CMP1
|
|
- name: CMP4
|
|
description: Timer A compare 4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETD1R_CMP1
|
|
- name: MSTPER
|
|
description: Master Period
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETD1R_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master Compare 1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETD1R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master Compare 2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETD1R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master Compare 3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETD1R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master Compare 4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETD1R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: Timer Event 1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: Timer Event 2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: Timer Event 3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: Timer Event 4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: Timer Event 5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: Timer Event 6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: Timer Event 7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: Timer Event 8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: Timer Event 9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETD1R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETD1R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: "Registers update (transfer preload to\r active)"
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETD1R_UPDATE
|
|
fieldset/SETD2R:
|
|
description: Timerx Output2 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: SST
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETD2R_SST
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETD2R_RESYNC
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETD2R_PER
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETD2R_CMP1
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETD2R_CMP1
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETD2R_CMP1
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETD2R_CMP1
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETD2R_MSTPER
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETD2R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETD2R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETD2R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETD2R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETD2R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETD2R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETD2R_UPDATE
|
|
fieldset/SETE1R:
|
|
description: Timerx Output1 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: Software Set trigger
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETE1R_SST
|
|
- name: RESYNC
|
|
description: Timer A resynchronizaton
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETE1R_RESYNC
|
|
- name: PER
|
|
description: Timer A Period
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETE1R_PER
|
|
- name: CMP1
|
|
description: Timer A compare 1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETE1R_CMP1
|
|
- name: CMP2
|
|
description: Timer A compare 2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETE1R_CMP1
|
|
- name: CMP3
|
|
description: Timer A compare 3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETE1R_CMP1
|
|
- name: CMP4
|
|
description: Timer A compare 4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETE1R_CMP1
|
|
- name: MSTPER
|
|
description: Master Period
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETE1R_MSTPER
|
|
- name: MSTCMP1
|
|
description: Master Compare 1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETE1R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: Master Compare 2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETE1R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: Master Compare 3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETE1R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: Master Compare 4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETE1R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: Timer Event 1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: Timer Event 2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: Timer Event 3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: Timer Event 4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: Timer Event 5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: Timer Event 6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: Timer Event 7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: Timer Event 8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: Timer Event 9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETE1R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: External Event 1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: External Event 2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: External Event 3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: External Event 4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: External Event 5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: External Event 6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: External Event 7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: External Event 8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: External Event 9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: External Event 10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETE1R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: "Registers update (transfer preload to\r active)"
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETE1R_UPDATE
|
|
fieldset/SETE2R:
|
|
description: Timerx Output2 Set Register
|
|
fields:
|
|
- name: SST
|
|
description: SST
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum: SETE2R_SST
|
|
- name: RESYNC
|
|
description: RESYNC
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum: SETE2R_RESYNC
|
|
- name: PER
|
|
description: PER
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum: SETE2R_PER
|
|
- name: CMP1
|
|
description: CMP1
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: SETE2R_CMP1
|
|
- name: CMP2
|
|
description: CMP2
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum: SETE2R_CMP1
|
|
- name: CMP3
|
|
description: CMP3
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
enum: SETE2R_CMP1
|
|
- name: CMP4
|
|
description: CMP4
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum: SETE2R_CMP1
|
|
- name: MSTPER
|
|
description: MSTPER
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum: SETE2R_MSTPER
|
|
- name: MSTCMP1
|
|
description: MSTCMP1
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum: SETE2R_MSTCMP1
|
|
- name: MSTCMP2
|
|
description: MSTCMP2
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum: SETE2R_MSTCMP1
|
|
- name: MSTCMP3
|
|
description: MSTCMP3
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SETE2R_MSTCMP1
|
|
- name: MSTCMP4
|
|
description: MSTCMP4
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SETE2R_MSTCMP1
|
|
- name: TIMEVNT1
|
|
description: TIMEVNT1
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT2
|
|
description: TIMEVNT2
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT3
|
|
description: TIMEVNT3
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT4
|
|
description: TIMEVNT4
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT5
|
|
description: TIMEVNT5
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT6
|
|
description: TIMEVNT6
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT7
|
|
description: TIMEVNT7
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT8
|
|
description: TIMEVNT8
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: TIMEVNT9
|
|
description: TIMEVNT9
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum: SETE2R_TIMEVNT1
|
|
- name: EXTEVNT1
|
|
description: EXTEVNT1
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT2
|
|
description: EXTEVNT2
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT3
|
|
description: EXTEVNT3
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT4
|
|
description: EXTEVNT4
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT5
|
|
description: EXTEVNT5
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT6
|
|
description: EXTEVNT6
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT7
|
|
description: EXTEVNT7
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT8
|
|
description: EXTEVNT8
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT9
|
|
description: EXTEVNT9
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: EXTEVNT10
|
|
description: EXTEVNT10
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
enum: SETE2R_EXTEVNT1
|
|
- name: UPDATE
|
|
description: UPDATE
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum: SETE2R_UPDATE
|
|
fieldset/TIMACR:
|
|
description: Timerx Control Register
|
|
fields:
|
|
- name: CKPSCx
|
|
description: "HRTIM Timer x Clock\r prescaler"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: CONT
|
|
description: Continuous mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CONT
|
|
- name: RETRIG
|
|
description: Re-triggerable mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HALF
|
|
description: Half mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PSHPLL
|
|
description: Push-Pull mode enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SYNCRSTx
|
|
description: "Synchronization Resets Timer\r x"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SYNCRSTx
|
|
- name: SYNCSTRTx
|
|
description: "Synchronization Starts Timer\r x"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SYNCSTRTx
|
|
- name: DELCMP2
|
|
description: Delayed CMP2 mode
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: DELCMP2
|
|
- name: DELCMP4
|
|
description: Delayed CMP4 mode
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
enum: DELCMP4
|
|
- name: TxREPU
|
|
description: Timer x Repetition update
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TxRSTU
|
|
description: Timerx reset update
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TBU
|
|
description: TBU
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TCU
|
|
description: TCU
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: TDU
|
|
description: TDU
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TEU
|
|
description: TEU
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: MSTU
|
|
description: Master Timer update
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: UPDGAT
|
|
description: Update Gating
|
|
bit_offset: 28
|
|
bit_size: 4
|
|
enum: UPDGAT
|
|
fieldset/TIMADIER:
|
|
description: TIMxDIER5
|
|
fields:
|
|
- name: CMP1IE
|
|
description: CMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMP2IE
|
|
description: CMP2IE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CMP3IE
|
|
description: CMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CMP4IE
|
|
description: CMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: REPIE
|
|
description: REPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UPDIE
|
|
description: UPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CPT1IE
|
|
description: CPT1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CPT2IE
|
|
description: CPT2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SETx1IE
|
|
description: SET1xIE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RSTx1IE
|
|
description: RSTx1IE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SETx2IE
|
|
description: SETx2IE
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RSTx2IE
|
|
description: RSTx2IE
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RSTIE
|
|
description: RSTIE
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: DLYPRTIE
|
|
description: DLYPRTIE
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: CMP1DE
|
|
description: CMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CMP2DE
|
|
description: CMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CMP3DE
|
|
description: CMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CMP4DE
|
|
description: CMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: REPDE
|
|
description: REPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: UPDDE
|
|
description: UPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: CPT1DE
|
|
description: CPT1DE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CPT2DE
|
|
description: CPT2DE
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: SETx1DE
|
|
description: SET1xDE
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: RSTx1DE
|
|
description: RSTx1DE
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: SETx2DE
|
|
description: SETx2DE
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: RSTx2DE
|
|
description: RSTx2DE
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: RSTDE
|
|
description: RSTDE
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: DLYPRTDE
|
|
description: DLYPRTDE
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/TIMAICR:
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
fields:
|
|
- name: CMP1C
|
|
description: "Compare 1 Interrupt flag\r Clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP2C
|
|
description: "Compare 2 Interrupt flag\r Clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP3C
|
|
description: "Compare 3 Interrupt flag\r Clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP4C
|
|
description: "Compare 4 Interrupt flag\r Clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: REPC
|
|
description: "Repetition Interrupt flag\r Clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: UPDC
|
|
description: "Update Interrupt flag\r Clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT1C
|
|
description: "Capture1 Interrupt flag\r Clear"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT2C
|
|
description: "Capture2 Interrupt flag\r Clear"
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET1xC
|
|
description: Output 1 Set flag Clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx1C
|
|
description: Output 1 Reset flag Clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET2xC
|
|
description: Output 2 Set flag Clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx2C
|
|
description: Output 2 Reset flag Clear
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTC
|
|
description: Reset Interrupt flag Clear
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: DLYPRTC
|
|
description: "Delayed Protection Flag\r Clear"
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
fieldset/TIMAISR:
|
|
description: "Timerx Interrupt Status\r Register"
|
|
fields:
|
|
- name: CMP1
|
|
description: Compare 1 Interrupt Flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP2
|
|
description: Compare 2 Interrupt Flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP3
|
|
description: Compare 3 Interrupt Flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP4
|
|
description: Compare 4 Interrupt Flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: REP
|
|
description: Repetition Interrupt Flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: UPD
|
|
description: Update Interrupt Flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT1
|
|
description: Capture1 Interrupt Flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT2
|
|
description: Capture2 Interrupt Flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx1
|
|
description: "Output 1 Set Interrupt\r Flag"
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx1
|
|
description: "Output 1 Reset Interrupt\r Flag"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx2
|
|
description: "Output 2 Set Interrupt\r Flag"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx2
|
|
description: "Output 2 Reset Interrupt\r Flag"
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RST
|
|
description: Reset Interrupt Flag
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: DLYPRT
|
|
description: Delayed Protection Flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_read: TIMAISR_DLYPRT
|
|
- name: CPPSTAT
|
|
description: Current Push Pull Status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum_read: CPPSTAT
|
|
- name: IPPSTAT
|
|
description: Idle Push Pull Status
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum_read: IPPSTAT
|
|
- name: O1STAT
|
|
description: Output 1 State
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O2STAT
|
|
description: Output 2 State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O1CPY
|
|
description: Output 1 Copy
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
- name: O2CPY
|
|
description: Output 2 Copy
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
fieldset/TIMBCR:
|
|
description: Timerx Control Register
|
|
fields:
|
|
- name: CKPSCx
|
|
description: "HRTIM Timer x Clock\r prescaler"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: CONT
|
|
description: Continuous mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CONT
|
|
- name: RETRIG
|
|
description: Re-triggerable mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HALF
|
|
description: Half mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PSHPLL
|
|
description: Push-Pull mode enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SYNCRSTx
|
|
description: "Synchronization Resets Timer\r x"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SYNCRSTx
|
|
- name: SYNCSTRTx
|
|
description: "Synchronization Starts Timer\r x"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SYNCSTRTx
|
|
- name: DELCMP2
|
|
description: Delayed CMP2 mode
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: DELCMP2
|
|
- name: DELCMP4
|
|
description: Delayed CMP4 mode
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
enum: DELCMP4
|
|
- name: TxREPU
|
|
description: Timer x Repetition update
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TxRSTU
|
|
description: Timerx reset update
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TBU
|
|
description: TBU
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TCU
|
|
description: TCU
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: TDU
|
|
description: TDU
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TEU
|
|
description: TEU
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: MSTU
|
|
description: Master Timer update
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: UPDGAT
|
|
description: Update Gating
|
|
bit_offset: 28
|
|
bit_size: 4
|
|
enum: UPDGAT
|
|
fieldset/TIMBDIER:
|
|
description: TIMxDIER5
|
|
fields:
|
|
- name: CMP1IE
|
|
description: CMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMP2IE
|
|
description: CMP2IE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CMP3IE
|
|
description: CMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CMP4IE
|
|
description: CMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: REPIE
|
|
description: REPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UPDIE
|
|
description: UPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CPT1IE
|
|
description: CPT1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CPT2IE
|
|
description: CPT2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SETx1IE
|
|
description: SET1xIE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RSTx1IE
|
|
description: RSTx1IE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SETx2IE
|
|
description: SETx2IE
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RSTx2IE
|
|
description: RSTx2IE
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RSTIE
|
|
description: RSTIE
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: DLYPRTIE
|
|
description: DLYPRTIE
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: CMP1DE
|
|
description: CMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CMP2DE
|
|
description: CMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CMP3DE
|
|
description: CMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CMP4DE
|
|
description: CMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: REPDE
|
|
description: REPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: UPDDE
|
|
description: UPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: CPT1DE
|
|
description: CPT1DE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CPT2DE
|
|
description: CPT2DE
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: SETx1DE
|
|
description: SET1xDE
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: RSTx1DE
|
|
description: RSTx1DE
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: SETx2DE
|
|
description: SETx2DE
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: RSTx2DE
|
|
description: RSTx2DE
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: RSTDE
|
|
description: RSTDE
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: DLYPRTDE
|
|
description: DLYPRTDE
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/TIMBICR:
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
fields:
|
|
- name: CMP1C
|
|
description: "Compare 1 Interrupt flag\r Clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP2C
|
|
description: "Compare 2 Interrupt flag\r Clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP3C
|
|
description: "Compare 3 Interrupt flag\r Clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP4C
|
|
description: "Compare 4 Interrupt flag\r Clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: REPC
|
|
description: "Repetition Interrupt flag\r Clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: UPDC
|
|
description: "Update Interrupt flag\r Clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT1C
|
|
description: "Capture1 Interrupt flag\r Clear"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT2C
|
|
description: "Capture2 Interrupt flag\r Clear"
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET1xC
|
|
description: Output 1 Set flag Clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx1C
|
|
description: Output 1 Reset flag Clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET2xC
|
|
description: Output 2 Set flag Clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx2C
|
|
description: Output 2 Reset flag Clear
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTC
|
|
description: Reset Interrupt flag Clear
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: DLYPRTC
|
|
description: "Delayed Protection Flag\r Clear"
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
fieldset/TIMBISR:
|
|
description: "Timerx Interrupt Status\r Register"
|
|
fields:
|
|
- name: CMP1
|
|
description: Compare 1 Interrupt Flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP2
|
|
description: Compare 2 Interrupt Flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP3
|
|
description: Compare 3 Interrupt Flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP4
|
|
description: Compare 4 Interrupt Flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: REP
|
|
description: Repetition Interrupt Flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: UPD
|
|
description: Update Interrupt Flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT1
|
|
description: Capture1 Interrupt Flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT2
|
|
description: Capture2 Interrupt Flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx1
|
|
description: "Output 1 Set Interrupt\r Flag"
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx1
|
|
description: "Output 1 Reset Interrupt\r Flag"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx2
|
|
description: "Output 2 Set Interrupt\r Flag"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx2
|
|
description: "Output 2 Reset Interrupt\r Flag"
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RST
|
|
description: Reset Interrupt Flag
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: DLYPRT
|
|
description: Delayed Protection Flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_read: TIMBISR_DLYPRT
|
|
- name: CPPSTAT
|
|
description: Current Push Pull Status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum_read: CPPSTAT
|
|
- name: IPPSTAT
|
|
description: Idle Push Pull Status
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum_read: IPPSTAT
|
|
- name: O1STAT
|
|
description: Output 1 State
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O2STAT
|
|
description: Output 2 State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O1CPY
|
|
description: Output 1 Copy
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
- name: O2CPY
|
|
description: Output 2 Copy
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
fieldset/TIMCCR:
|
|
description: Timerx Control Register
|
|
fields:
|
|
- name: CKPSCx
|
|
description: "HRTIM Timer x Clock\r prescaler"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: CONT
|
|
description: Continuous mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CONT
|
|
- name: RETRIG
|
|
description: Re-triggerable mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HALF
|
|
description: Half mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PSHPLL
|
|
description: Push-Pull mode enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SYNCRSTx
|
|
description: "Synchronization Resets Timer\r x"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SYNCRSTx
|
|
- name: SYNCSTRTx
|
|
description: "Synchronization Starts Timer\r x"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SYNCSTRTx
|
|
- name: DELCMP2
|
|
description: Delayed CMP2 mode
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: DELCMP2
|
|
- name: DELCMP4
|
|
description: Delayed CMP4 mode
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
enum: DELCMP4
|
|
- name: TxREPU
|
|
description: Timer x Repetition update
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TxRSTU
|
|
description: Timerx reset update
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TBU
|
|
description: TBU
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TCU
|
|
description: TCU
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: TDU
|
|
description: TDU
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TEU
|
|
description: TEU
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: MSTU
|
|
description: Master Timer update
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: UPDGAT
|
|
description: Update Gating
|
|
bit_offset: 28
|
|
bit_size: 4
|
|
enum: UPDGAT
|
|
fieldset/TIMCDIER:
|
|
description: TIMxDIER5
|
|
fields:
|
|
- name: CMP1IE
|
|
description: CMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMP2IE
|
|
description: CMP2IE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CMP3IE
|
|
description: CMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CMP4IE
|
|
description: CMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: REPIE
|
|
description: REPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UPDIE
|
|
description: UPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CPT1IE
|
|
description: CPT1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CPT2IE
|
|
description: CPT2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SETx1IE
|
|
description: SET1xIE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RSTx1IE
|
|
description: RSTx1IE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SETx2IE
|
|
description: SETx2IE
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RSTx2IE
|
|
description: RSTx2IE
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RSTIE
|
|
description: RSTIE
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: DLYPRTIE
|
|
description: DLYPRTIE
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: CMP1DE
|
|
description: CMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CMP2DE
|
|
description: CMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CMP3DE
|
|
description: CMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CMP4DE
|
|
description: CMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: REPDE
|
|
description: REPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: UPDDE
|
|
description: UPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: CPT1DE
|
|
description: CPT1DE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CPT2DE
|
|
description: CPT2DE
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: SETx1DE
|
|
description: SET1xDE
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: RSTx1DE
|
|
description: RSTx1DE
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: SETx2DE
|
|
description: SETx2DE
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: RSTx2DE
|
|
description: RSTx2DE
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: RSTDE
|
|
description: RSTDE
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: DLYPRTDE
|
|
description: DLYPRTDE
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/TIMCICR:
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
fields:
|
|
- name: CMP1C
|
|
description: "Compare 1 Interrupt flag\r Clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP2C
|
|
description: "Compare 2 Interrupt flag\r Clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP3C
|
|
description: "Compare 3 Interrupt flag\r Clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP4C
|
|
description: "Compare 4 Interrupt flag\r Clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: REPC
|
|
description: "Repetition Interrupt flag\r Clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: UPDC
|
|
description: "Update Interrupt flag\r Clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT1C
|
|
description: "Capture1 Interrupt flag\r Clear"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT2C
|
|
description: "Capture2 Interrupt flag\r Clear"
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET1xC
|
|
description: Output 1 Set flag Clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx1C
|
|
description: Output 1 Reset flag Clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET2xC
|
|
description: Output 2 Set flag Clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx2C
|
|
description: Output 2 Reset flag Clear
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTC
|
|
description: Reset Interrupt flag Clear
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: DLYPRTC
|
|
description: "Delayed Protection Flag\r Clear"
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
fieldset/TIMCISR:
|
|
description: "Timerx Interrupt Status\r Register"
|
|
fields:
|
|
- name: CMP1
|
|
description: Compare 1 Interrupt Flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP2
|
|
description: Compare 2 Interrupt Flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP3
|
|
description: Compare 3 Interrupt Flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP4
|
|
description: Compare 4 Interrupt Flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: REP
|
|
description: Repetition Interrupt Flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: UPD
|
|
description: Update Interrupt Flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT1
|
|
description: Capture1 Interrupt Flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT2
|
|
description: Capture2 Interrupt Flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx1
|
|
description: "Output 1 Set Interrupt\r Flag"
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx1
|
|
description: "Output 1 Reset Interrupt\r Flag"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx2
|
|
description: "Output 2 Set Interrupt\r Flag"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx2
|
|
description: "Output 2 Reset Interrupt\r Flag"
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RST
|
|
description: Reset Interrupt Flag
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: DLYPRT
|
|
description: Delayed Protection Flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_read: TIMCISR_DLYPRT
|
|
- name: CPPSTAT
|
|
description: Current Push Pull Status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum_read: CPPSTAT
|
|
- name: IPPSTAT
|
|
description: Idle Push Pull Status
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum_read: IPPSTAT
|
|
- name: O1STAT
|
|
description: Output 1 State
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O2STAT
|
|
description: Output 2 State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O1CPY
|
|
description: Output 1 Copy
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
- name: O2CPY
|
|
description: Output 2 Copy
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
fieldset/TIMDCR:
|
|
description: Timerx Control Register
|
|
fields:
|
|
- name: CKPSCx
|
|
description: "HRTIM Timer x Clock\r prescaler"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: CONT
|
|
description: Continuous mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CONT
|
|
- name: RETRIG
|
|
description: Re-triggerable mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HALF
|
|
description: Half mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PSHPLL
|
|
description: Push-Pull mode enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SYNCRSTx
|
|
description: "Synchronization Resets Timer\r x"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SYNCRSTx
|
|
- name: SYNCSTRTx
|
|
description: "Synchronization Starts Timer\r x"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SYNCSTRTx
|
|
- name: DELCMP2
|
|
description: Delayed CMP2 mode
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: DELCMP2
|
|
- name: DELCMP4
|
|
description: Delayed CMP4 mode
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
enum: DELCMP4
|
|
- name: TxREPU
|
|
description: Timer x Repetition update
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TxRSTU
|
|
description: Timerx reset update
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TBU
|
|
description: TBU
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TCU
|
|
description: TCU
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: TDU
|
|
description: TDU
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TEU
|
|
description: TEU
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: MSTU
|
|
description: Master Timer update
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: UPDGAT
|
|
description: Update Gating
|
|
bit_offset: 28
|
|
bit_size: 4
|
|
enum: UPDGAT
|
|
fieldset/TIMDDIER:
|
|
description: TIMxDIER5
|
|
fields:
|
|
- name: CMP1IE
|
|
description: CMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMP2IE
|
|
description: CMP2IE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CMP3IE
|
|
description: CMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CMP4IE
|
|
description: CMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: REPIE
|
|
description: REPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UPDIE
|
|
description: UPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CPT1IE
|
|
description: CPT1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CPT2IE
|
|
description: CPT2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SETx1IE
|
|
description: SET1xIE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RSTx1IE
|
|
description: RSTx1IE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SETx2IE
|
|
description: SETx2IE
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RSTx2IE
|
|
description: RSTx2IE
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RSTIE
|
|
description: RSTIE
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: DLYPRTIE
|
|
description: DLYPRTIE
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: CMP1DE
|
|
description: CMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CMP2DE
|
|
description: CMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CMP3DE
|
|
description: CMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CMP4DE
|
|
description: CMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: REPDE
|
|
description: REPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: UPDDE
|
|
description: UPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: CPT1DE
|
|
description: CPT1DE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CPT2DE
|
|
description: CPT2DE
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: SETx1DE
|
|
description: SET1xDE
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: RSTx1DE
|
|
description: RSTx1DE
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: SETx2DE
|
|
description: SETx2DE
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: RSTx2DE
|
|
description: RSTx2DE
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: RSTDE
|
|
description: RSTDE
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: DLYPRTDE
|
|
description: DLYPRTDE
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/TIMDICR:
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
fields:
|
|
- name: CMP1C
|
|
description: "Compare 1 Interrupt flag\r Clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP2C
|
|
description: "Compare 2 Interrupt flag\r Clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP3C
|
|
description: "Compare 3 Interrupt flag\r Clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP4C
|
|
description: "Compare 4 Interrupt flag\r Clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: REPC
|
|
description: "Repetition Interrupt flag\r Clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: UPDC
|
|
description: "Update Interrupt flag\r Clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT1C
|
|
description: "Capture1 Interrupt flag\r Clear"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT2C
|
|
description: "Capture2 Interrupt flag\r Clear"
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET1xC
|
|
description: Output 1 Set flag Clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx1C
|
|
description: Output 1 Reset flag Clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET2xC
|
|
description: Output 2 Set flag Clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx2C
|
|
description: Output 2 Reset flag Clear
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTC
|
|
description: Reset Interrupt flag Clear
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: DLYPRTC
|
|
description: "Delayed Protection Flag\r Clear"
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
fieldset/TIMDISR:
|
|
description: "Timerx Interrupt Status\r Register"
|
|
fields:
|
|
- name: CMP1
|
|
description: Compare 1 Interrupt Flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP2
|
|
description: Compare 2 Interrupt Flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP3
|
|
description: Compare 3 Interrupt Flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP4
|
|
description: Compare 4 Interrupt Flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: REP
|
|
description: Repetition Interrupt Flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: UPD
|
|
description: Update Interrupt Flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT1
|
|
description: Capture1 Interrupt Flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT2
|
|
description: Capture2 Interrupt Flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx1
|
|
description: "Output 1 Set Interrupt\r Flag"
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx1
|
|
description: "Output 1 Reset Interrupt\r Flag"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx2
|
|
description: "Output 2 Set Interrupt\r Flag"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx2
|
|
description: "Output 2 Reset Interrupt\r Flag"
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RST
|
|
description: Reset Interrupt Flag
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: DLYPRT
|
|
description: Delayed Protection Flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_read: TIMDISR_DLYPRT
|
|
- name: CPPSTAT
|
|
description: Current Push Pull Status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum_read: CPPSTAT
|
|
- name: IPPSTAT
|
|
description: Idle Push Pull Status
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum_read: IPPSTAT
|
|
- name: O1STAT
|
|
description: Output 1 State
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O2STAT
|
|
description: Output 2 State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O1CPY
|
|
description: Output 1 Copy
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
- name: O2CPY
|
|
description: Output 2 Copy
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
fieldset/TIMECR:
|
|
description: Timerx Control Register
|
|
fields:
|
|
- name: CKPSCx
|
|
description: "HRTIM Timer x Clock\r prescaler"
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
- name: CONT
|
|
description: Continuous mode
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum: CONT
|
|
- name: RETRIG
|
|
description: Re-triggerable mode
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: HALF
|
|
description: Half mode enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: PSHPLL
|
|
description: Push-Pull mode enable
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: SYNCRSTx
|
|
description: "Synchronization Resets Timer\r x"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum: SYNCRSTx
|
|
- name: SYNCSTRTx
|
|
description: "Synchronization Starts Timer\r x"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum: SYNCSTRTx
|
|
- name: DELCMP2
|
|
description: Delayed CMP2 mode
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
enum: DELCMP2
|
|
- name: DELCMP4
|
|
description: Delayed CMP4 mode
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
enum: DELCMP4
|
|
- name: TxREPU
|
|
description: Timer x Repetition update
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TxRSTU
|
|
description: Timerx reset update
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TBU
|
|
description: TBU
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: TCU
|
|
description: TCU
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: TDU
|
|
description: TDU
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: TEU
|
|
description: TEU
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: MSTU
|
|
description: Master Timer update
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: DACSYNC
|
|
description: AC Synchronization
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
enum: DACSYNC
|
|
- name: PREEN
|
|
description: Preload enable
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: UPDGAT
|
|
description: Update Gating
|
|
bit_offset: 28
|
|
bit_size: 4
|
|
enum: UPDGAT
|
|
fieldset/TIMEDIER:
|
|
description: TIMxDIER5
|
|
fields:
|
|
- name: CMP1IE
|
|
description: CMP1IE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: CMP2IE
|
|
description: CMP2IE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: CMP3IE
|
|
description: CMP3IE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: CMP4IE
|
|
description: CMP4IE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: REPIE
|
|
description: REPIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: UPDIE
|
|
description: UPDIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: CPT1IE
|
|
description: CPT1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: CPT2IE
|
|
description: CPT2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SETx1IE
|
|
description: SET1xIE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: RSTx1IE
|
|
description: RSTx1IE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: SETx2IE
|
|
description: SETx2IE
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: RSTx2IE
|
|
description: RSTx2IE
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: RSTIE
|
|
description: RSTIE
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: DLYPRTIE
|
|
description: DLYPRTIE
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: CMP1DE
|
|
description: CMP1DE
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: CMP2DE
|
|
description: CMP2DE
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: CMP3DE
|
|
description: CMP3DE
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CMP4DE
|
|
description: CMP4DE
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: REPDE
|
|
description: REPDE
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: UPDDE
|
|
description: UPDDE
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: CPT1DE
|
|
description: CPT1DE
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: CPT2DE
|
|
description: CPT2DE
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: SETx1DE
|
|
description: SET1xDE
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: RSTx1DE
|
|
description: RSTx1DE
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: SETx2DE
|
|
description: SETx2DE
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: RSTx2DE
|
|
description: RSTx2DE
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: RSTDE
|
|
description: RSTDE
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: DLYPRTDE
|
|
description: DLYPRTDE
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
fieldset/TIMEICR:
|
|
description: "Timerx Interrupt Clear\r Register"
|
|
fields:
|
|
- name: CMP1C
|
|
description: "Compare 1 Interrupt flag\r Clear"
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP2C
|
|
description: "Compare 2 Interrupt flag\r Clear"
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP3C
|
|
description: "Compare 3 Interrupt flag\r Clear"
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CMP4C
|
|
description: "Compare 4 Interrupt flag\r Clear"
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: REPC
|
|
description: "Repetition Interrupt flag\r Clear"
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: UPDC
|
|
description: "Update Interrupt flag\r Clear"
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT1C
|
|
description: "Capture1 Interrupt flag\r Clear"
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: CPT2C
|
|
description: "Capture2 Interrupt flag\r Clear"
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET1xC
|
|
description: Output 1 Set flag Clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx1C
|
|
description: Output 1 Reset flag Clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: SET2xC
|
|
description: Output 2 Set flag Clear
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTx2C
|
|
description: Output 2 Reset flag Clear
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: RSTC
|
|
description: Reset Interrupt flag Clear
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
- name: DLYPRTC
|
|
description: "Delayed Protection Flag\r Clear"
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_write: CMP1C
|
|
fieldset/TIMEISR:
|
|
description: "Timerx Interrupt Status\r Register"
|
|
fields:
|
|
- name: CMP1
|
|
description: Compare 1 Interrupt Flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP2
|
|
description: Compare 2 Interrupt Flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP3
|
|
description: Compare 3 Interrupt Flag
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CMP4
|
|
description: Compare 4 Interrupt Flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: REP
|
|
description: Repetition Interrupt Flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: UPD
|
|
description: Update Interrupt Flag
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT1
|
|
description: Capture1 Interrupt Flag
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: CPT2
|
|
description: Capture2 Interrupt Flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx1
|
|
description: "Output 1 Set Interrupt\r Flag"
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx1
|
|
description: "Output 1 Reset Interrupt\r Flag"
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: SETx2
|
|
description: "Output 2 Set Interrupt\r Flag"
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RSTx2
|
|
description: "Output 2 Reset Interrupt\r Flag"
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: RST
|
|
description: Reset Interrupt Flag
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
enum_read: EVENT
|
|
- name: DLYPRT
|
|
description: Delayed Protection Flag
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
enum_read: TIMEISR_DLYPRT
|
|
- name: CPPSTAT
|
|
description: Current Push Pull Status
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
enum_read: CPPSTAT
|
|
- name: IPPSTAT
|
|
description: Idle Push Pull Status
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
enum_read: IPPSTAT
|
|
- name: O1STAT
|
|
description: Output 1 State
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O2STAT
|
|
description: Output 2 State
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
enum_read: O1STAT
|
|
- name: O1CPY
|
|
description: Output 1 Copy
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
- name: O2CPY
|
|
description: Output 2 Copy
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
enum_read: O1CPY
|
|
enum/BRSTDMA:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Independent
|
|
description: Update done independently from the DMA burst transfer completion
|
|
value: 0
|
|
- name: Completion
|
|
description: Update done when the DMA burst transfer is completed
|
|
value: 1
|
|
- name: Rollover
|
|
description: Update done on master timer roll-over following a DMA burst transfer completion
|
|
value: 2
|
|
enum/CMP1C:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clears associated flag in ISR register
|
|
value: 1
|
|
enum/CMP2:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer X compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon timer X compare Z event
|
|
value: 1
|
|
enum/CONT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: SingleShot
|
|
description: The timer operates in single-shot mode and stops when it reaches the MPER value
|
|
value: 0
|
|
- name: Continuous
|
|
description: The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value
|
|
value: 1
|
|
enum/CPPSTAT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Output1Active
|
|
description: Signal applied on output 1 and output 2 forced inactive
|
|
value: 0
|
|
- name: Output2Active
|
|
description: Signal applied on output 2 and output 1 forced inactive
|
|
value: 1
|
|
enum/CPTXXCR_XXXXX:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: TriggerCapture
|
|
description: Timer event triggers capture
|
|
value: 1
|
|
enum/DACSYNC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: No DAC trigger generated
|
|
value: 0
|
|
- name: DACSync1
|
|
description: Trigger generated on DACSync1
|
|
value: 1
|
|
- name: DACSync2
|
|
description: Trigger generated on DACSync2
|
|
value: 2
|
|
- name: DACSync3
|
|
description: Trigger generated on DACSync3
|
|
value: 3
|
|
enum/DELCMP2:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Standard
|
|
description: CMP2 register is always active (standard compare mode)
|
|
value: 0
|
|
- name: Capture1
|
|
description: CMP2 is recomputed and is active following a capture 1 event
|
|
value: 1
|
|
- name: Capture1_Compare1
|
|
description: CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match
|
|
value: 2
|
|
- name: Capture1_Compare3
|
|
description: CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match
|
|
value: 3
|
|
enum/DELCMP4:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Standard
|
|
description: CMP4 register is always active (standard compare mode)
|
|
value: 0
|
|
- name: Capture2
|
|
description: CMP4 is recomputed and is active following a capture 2 event
|
|
value: 1
|
|
- name: Capture2_Compare1
|
|
description: CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match
|
|
value: 2
|
|
- name: Capture_Compare3
|
|
description: CMP4 is recomputed and is active following a capture event or a Compare 3 match
|
|
value: 3
|
|
enum/EE1FLTR:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Disabled
|
|
description: No filtering
|
|
value: 0
|
|
- name: BlankResetToCompare1
|
|
description: Blanking from counter reset/roll-over to Compare 1
|
|
value: 1
|
|
- name: BlankResetToCompare2
|
|
description: Blanking from counter reset/roll-over to Compare 2
|
|
value: 2
|
|
- name: BlankResetToCompare3
|
|
description: Blanking from counter reset/roll-over to Compare 3
|
|
value: 3
|
|
- name: BlankResetToCompare4
|
|
description: Blanking from counter reset/roll-over to Compare 4
|
|
value: 4
|
|
- name: BlankTIMFLTR1
|
|
description: "Blanking from another timing unit: TIMFLTR1 source"
|
|
value: 5
|
|
- name: BlankTIMFLTR2
|
|
description: "Blanking from another timing unit: TIMFLTR2 source"
|
|
value: 6
|
|
- name: BlankTIMFLTR3
|
|
description: "Blanking from another timing unit: TIMFLTR3 source"
|
|
value: 7
|
|
- name: BlankTIMFLTR4
|
|
description: "Blanking from another timing unit: TIMFLTR4 source"
|
|
value: 8
|
|
- name: BlankTIMFLTR5
|
|
description: "Blanking from another timing unit: TIMFLTR5 source"
|
|
value: 9
|
|
- name: BlankTIMFLTR6
|
|
description: "Blanking from another timing unit: TIMFLTR6 source"
|
|
value: 10
|
|
- name: BlankTIMFLTR7
|
|
description: "Blanking from another timing unit: TIMFLTR7 source"
|
|
value: 11
|
|
- name: BlankTIMFLTR8
|
|
description: "Blanking from another timing unit: TIMFLTR8 source"
|
|
value: 12
|
|
- name: WindowResetToCompare2
|
|
description: Windowing from counter reset/roll-over to compare 2
|
|
value: 13
|
|
- name: WindowResetToCompare3
|
|
description: Windowing from counter reset/roll-over to compare 3
|
|
value: 14
|
|
- name: WindowTIMWIN
|
|
description: "Windowing from another timing unit: TIMWIN source"
|
|
value: 15
|
|
enum/EE6FLTR:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Disabled
|
|
description: No filtering
|
|
value: 0
|
|
- name: BlankResetToCompare1
|
|
description: Blanking from counter reset/roll-over to Compare 1
|
|
value: 1
|
|
- name: BlankResetToCompare2
|
|
description: Blanking from counter reset/roll-over to Compare 2
|
|
value: 2
|
|
- name: BlankResetToCompare3
|
|
description: Blanking from counter reset/roll-over to Compare 3
|
|
value: 3
|
|
- name: BlankResetToCompare4
|
|
description: Blanking from counter reset/roll-over to Compare 4
|
|
value: 4
|
|
- name: BlankTIMFLTR1
|
|
description: "Blanking from another timing unit: TIMFLTR1 source"
|
|
value: 5
|
|
- name: BlankTIMFLTR2
|
|
description: "Blanking from another timing unit: TIMFLTR2 source"
|
|
value: 6
|
|
- name: BlankTIMFLTR3
|
|
description: "Blanking from another timing unit: TIMFLTR3 source"
|
|
value: 7
|
|
- name: BlankTIMFLTR4
|
|
description: "Blanking from another timing unit: TIMFLTR4 source"
|
|
value: 8
|
|
- name: BlankTIMFLTR5
|
|
description: "Blanking from another timing unit: TIMFLTR5 source"
|
|
value: 9
|
|
- name: BlankTIMFLTR6
|
|
description: "Blanking from another timing unit: TIMFLTR6 source"
|
|
value: 10
|
|
- name: BlankTIMFLTR7
|
|
description: "Blanking from another timing unit: TIMFLTR7 source"
|
|
value: 11
|
|
- name: BlankTIMFLTR8
|
|
description: "Blanking from another timing unit: TIMFLTR8 source"
|
|
value: 12
|
|
- name: WindowResetToCompare2
|
|
description: Windowing from counter reset/roll-over to compare 2
|
|
value: 13
|
|
- name: WindowResetToCompare3
|
|
description: Windowing from counter reset/roll-over to compare 3
|
|
value: 14
|
|
- name: WindowTIMWIN
|
|
description: "Windowing from another timing unit: TIMWIN source"
|
|
value: 15
|
|
enum/EFFECT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetInactive
|
|
description: Timer event forces the output to its inactive state
|
|
value: 1
|
|
enum/EVENT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEvent
|
|
description: No compare interrupt occurred
|
|
value: 0
|
|
- name: Event
|
|
description: Compare interrupt occurred
|
|
value: 1
|
|
enum/FAULT1:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: "No action: the output is not affected by the fault input and stays in run mode"
|
|
value: 0
|
|
- name: SetActive
|
|
description: Output goes to active state after a fault event
|
|
value: 1
|
|
- name: SetInactive
|
|
description: Output goes to inactive state after a fault event
|
|
value: 2
|
|
- name: SetHighZ
|
|
description: Output goes to high-z state after a fault event
|
|
value: 3
|
|
enum/FLT1EN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Ignored
|
|
description: Fault input ignored
|
|
value: 0
|
|
- name: Active
|
|
description: Fault input is active and can disable HRTIM outputs
|
|
value: 1
|
|
enum/IDLEM1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: "No action: the output is not affected by the burst mode operation"
|
|
value: 0
|
|
- name: SetIdle
|
|
description: The output is in idle state when requested by the burst mode controller
|
|
value: 1
|
|
enum/IDLES1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Output idle state is inactive
|
|
value: 0
|
|
- name: Active
|
|
description: Output idle state is active
|
|
value: 1
|
|
enum/IPPSTAT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Output1Active
|
|
description: Protection occurred when the output 1 was active and output 2 forced inactive
|
|
value: 0
|
|
- name: Output2Active
|
|
description: Protection occurred when the output 2 was active and output 1 forced inactive
|
|
value: 1
|
|
enum/LOCKED:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Unlocked
|
|
description: Bits are writeable
|
|
value: 0
|
|
- name: Locked
|
|
description: Bits are read-only
|
|
value: 1
|
|
enum/MCMP1C:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: Clears flag in MISR register
|
|
value: 1
|
|
enum/O1CPY:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Output is inactive
|
|
value: 0
|
|
- name: Active
|
|
description: Output is active
|
|
value: 1
|
|
enum/O1STAT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Output was inactive
|
|
value: 0
|
|
- name: Active
|
|
description: Output was active
|
|
value: 1
|
|
enum/OUTAR_DLYPRT:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Output1_EE6
|
|
description: Output 1 delayed idle on external event 6
|
|
value: 0
|
|
- name: Output2_EE6
|
|
description: Output 2 delayed idle on external event 6
|
|
value: 1
|
|
- name: Output1_2_EE6
|
|
description: Output 1 and 2 delayed idle on external event 6
|
|
value: 2
|
|
- name: Balanced_EE6
|
|
description: Balanced idle on external event 6
|
|
value: 3
|
|
- name: Output1_EE7
|
|
description: Output 1 delayed idle on external event 7
|
|
value: 4
|
|
- name: Output2_EE7
|
|
description: Output 2 delayed idle on external event 7
|
|
value: 5
|
|
- name: Output1_2_EE7
|
|
description: Output 1 and 2 delayed idle on external event 7
|
|
value: 6
|
|
- name: Balanced_EE7
|
|
description: Balanced idle on external event 7
|
|
value: 7
|
|
enum/OUTBR_DLYPRT:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Output1_EE6
|
|
description: Output 1 delayed idle on external event 6
|
|
value: 0
|
|
- name: Output2_EE6
|
|
description: Output 2 delayed idle on external event 6
|
|
value: 1
|
|
- name: Output1_2_EE6
|
|
description: Output 1 and 2 delayed idle on external event 6
|
|
value: 2
|
|
- name: Balanced_EE6
|
|
description: Balanced idle on external event 6
|
|
value: 3
|
|
- name: Output1_EE7
|
|
description: Output 1 delayed idle on external event 7
|
|
value: 4
|
|
- name: Output2_EE7
|
|
description: Output 2 delayed idle on external event 7
|
|
value: 5
|
|
- name: Output1_2_EE7
|
|
description: Output 1 and 2 delayed idle on external event 7
|
|
value: 6
|
|
- name: Balanced_EE7
|
|
description: Balanced idle on external event 7
|
|
value: 7
|
|
enum/OUTCR_DLYPRT:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Output1_EE6
|
|
description: Output 1 delayed idle on external event 6
|
|
value: 0
|
|
- name: Output2_EE6
|
|
description: Output 2 delayed idle on external event 6
|
|
value: 1
|
|
- name: Output1_2_EE6
|
|
description: Output 1 and 2 delayed idle on external event 6
|
|
value: 2
|
|
- name: Balanced_EE6
|
|
description: Balanced idle on external event 6
|
|
value: 3
|
|
- name: Output1_EE7
|
|
description: Output 1 delayed idle on external event 7
|
|
value: 4
|
|
- name: Output2_EE7
|
|
description: Output 2 delayed idle on external event 7
|
|
value: 5
|
|
- name: Output1_2_EE7
|
|
description: Output 1 and 2 delayed idle on external event 7
|
|
value: 6
|
|
- name: Balanced_EE7
|
|
description: Balanced idle on external event 7
|
|
value: 7
|
|
enum/OUTDR_DLYPRT:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Output1_EE8
|
|
description: Output 1 delayed idle on external event 8
|
|
value: 0
|
|
- name: Output2_EE8
|
|
description: Output 2 delayed idle on external event 8
|
|
value: 1
|
|
- name: Output1_2_EE8
|
|
description: Output 1 and 2 delayed idle on external event 8
|
|
value: 2
|
|
- name: Balanced_EE8
|
|
description: Balanced idle on external event 8
|
|
value: 3
|
|
- name: Output1_EE9
|
|
description: Output 1 delayed idle on external event 9
|
|
value: 4
|
|
- name: Output2_EE9
|
|
description: Output 2 delayed idle on external event 9
|
|
value: 5
|
|
- name: Output1_2_EE9
|
|
description: Output 1 and 2 delayed idle on external event 9
|
|
value: 6
|
|
- name: Balanced_EE9
|
|
description: Balanced idle on external event 9
|
|
value: 7
|
|
enum/OUTER_DLYPRT:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Output1_EE8
|
|
description: Output 1 delayed idle on external event 8
|
|
value: 0
|
|
- name: Output2_EE8
|
|
description: Output 2 delayed idle on external event 8
|
|
value: 1
|
|
- name: Output1_2_EE8
|
|
description: Output 1 and 2 delayed idle on external event 8
|
|
value: 2
|
|
- name: Balanced_EE8
|
|
description: Balanced idle on external event 8
|
|
value: 3
|
|
- name: Output1_EE9
|
|
description: Output 1 delayed idle on external event 9
|
|
value: 4
|
|
- name: Output2_EE9
|
|
description: Output 2 delayed idle on external event 9
|
|
value: 5
|
|
- name: Output1_2_EE9
|
|
description: Output 1 and 2 delayed idle on external event 9
|
|
value: 6
|
|
- name: Balanced_EE9
|
|
description: Balanced idle on external event 9
|
|
value: 7
|
|
enum/POL1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: ActiveHigh
|
|
description: Positive polarity (output active high)
|
|
value: 0
|
|
- name: ActiveLow
|
|
description: Negative polarity (output active low)
|
|
value: 1
|
|
enum/RSTAR_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event Z has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon external event Z
|
|
value: 1
|
|
enum/RSTAR_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer compare Z event
|
|
value: 1
|
|
enum/RSTAR_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer period event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer period event
|
|
value: 1
|
|
enum/RSTBR_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event Z has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon external event Z
|
|
value: 1
|
|
enum/RSTBR_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer compare Z event
|
|
value: 1
|
|
enum/RSTBR_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer period event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer period event
|
|
value: 1
|
|
enum/RSTCR_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event Z has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon external event Z
|
|
value: 1
|
|
enum/RSTCR_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer compare Z event
|
|
value: 1
|
|
enum/RSTCR_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer period event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer period event
|
|
value: 1
|
|
enum/RSTDR_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event Z has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon external event Z
|
|
value: 1
|
|
enum/RSTDR_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer compare Z event
|
|
value: 1
|
|
enum/RSTDR_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer period event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer period event
|
|
value: 1
|
|
enum/RSTER_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event Z has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon external event Z
|
|
value: 1
|
|
enum/RSTER_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer compare Z event
|
|
value: 1
|
|
enum/RSTER_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer period event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon master timer period event
|
|
value: 1
|
|
enum/SDTFx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Positive
|
|
description: Positive deadtime on falling edge
|
|
value: 0
|
|
- name: Negative
|
|
description: Negative deadtime on falling edge
|
|
value: 1
|
|
enum/SDTRx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Positive
|
|
description: Positive deadtime on rising edge
|
|
value: 0
|
|
- name: Negative
|
|
description: Negative deadtime on rising edge
|
|
value: 1
|
|
enum/SETA1R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETA1R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETA1R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETA1R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETA1R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETA1R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETA1R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETA1R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETA1R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETA2R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETA2R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETB1R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETB1R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETB2R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETB2R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETC1R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETC1R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETC2R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETC2R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETD1R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETD1R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETD2R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETD2R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETE1R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETE1R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_CMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_EXTEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: External event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: External event forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_MSTCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer compare event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer compare event forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_MSTPER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Master timer counter roll-over/reset has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Master timer counter roll-over/reset forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_PER:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer period event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer period event forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_RESYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer reset event coming solely from software or SYNC input event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer reset event coming solely from software or SYNC input event forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_SST:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: No effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Force output to its active state
|
|
value: 1
|
|
enum/SETE2R_TIMEVNT1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Timer event forces the output to its active state
|
|
value: 1
|
|
enum/SETE2R_UPDATE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Register update event has no effect
|
|
value: 0
|
|
- name: SetActive
|
|
description: Register update event forces the output to its active state
|
|
value: 1
|
|
enum/SYNCIN:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: Disabled. HRTIM is not synchronized and runs in standalone mode
|
|
value: 0
|
|
- name: Internal
|
|
description: "Internal event: the HRTIM is synchronized with the on-chip timer"
|
|
value: 2
|
|
- name: External
|
|
description: "External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM"
|
|
value: 3
|
|
enum/SYNCOUT:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Disabled
|
|
description: Disabled
|
|
value: 0
|
|
- name: PositivePulse
|
|
description: Positive pulse on SCOUT output (16x f_HRTIM clock cycles)
|
|
value: 2
|
|
- name: NegativePulse
|
|
description: Negative pulse on SCOUT output (16x f_HRTIM clock cycles)
|
|
value: 3
|
|
enum/SYNCRSTx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Synchronization event has no effect on Timer x
|
|
value: 0
|
|
- name: Reset
|
|
description: Synchronization event resets Timer x
|
|
value: 1
|
|
enum/SYNCSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: MasterStart
|
|
description: Master timer Start
|
|
value: 0
|
|
- name: MasterCompare1
|
|
description: Master timer Compare 1 event
|
|
value: 1
|
|
- name: TimerAStart
|
|
description: Timer A start/reset
|
|
value: 2
|
|
- name: TimerACompare1
|
|
description: Timer A Compare 1 event
|
|
value: 3
|
|
enum/SYNCSTRTx:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Synchronization event has no effect on Timer x
|
|
value: 0
|
|
- name: Start
|
|
description: Synchronization event starts Timer x
|
|
value: 1
|
|
enum/TIMACMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer Y compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon timer Y compare Z event
|
|
value: 1
|
|
enum/TIMAISR_DLYPRT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Not in delayed idle or balanced idle mode
|
|
value: 0
|
|
- name: Active
|
|
description: Delayed idle or balanced idle mode entry
|
|
value: 1
|
|
enum/TIMBCMP1:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Timer Y compare Z event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon timer Y compare Z event
|
|
value: 1
|
|
enum/TIMBISR_DLYPRT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Not in delayed idle or balanced idle mode
|
|
value: 0
|
|
- name: Active
|
|
description: Delayed idle or balanced idle mode entry
|
|
value: 1
|
|
enum/TIMCISR_DLYPRT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Not in delayed idle or balanced idle mode
|
|
value: 0
|
|
- name: Active
|
|
description: Delayed idle or balanced idle mode entry
|
|
value: 1
|
|
enum/TIMDISR_DLYPRT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Not in delayed idle or balanced idle mode
|
|
value: 0
|
|
- name: Active
|
|
description: Delayed idle or balanced idle mode entry
|
|
value: 1
|
|
enum/TIMEISR_DLYPRT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Inactive
|
|
description: Not in delayed idle or balanced idle mode
|
|
value: 0
|
|
- name: Active
|
|
description: Delayed idle or balanced idle mode entry
|
|
value: 1
|
|
enum/UPDGAT:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Independent
|
|
description: Update occurs independently from the DMA burst transfer
|
|
value: 0
|
|
- name: DMABurst
|
|
description: Update occurs when the DMA burst transfer is completed
|
|
value: 1
|
|
- name: DMABurst_Update
|
|
description: Update occurs on the update event following DMA burst transfer completion
|
|
value: 2
|
|
- name: Input1
|
|
description: Update occurs on a rising edge of HRTIM update enable input 1
|
|
value: 3
|
|
- name: Input2
|
|
description: Update occurs on a rising edge of HRTIM update enable input 2
|
|
value: 4
|
|
- name: Input3
|
|
description: Update occurs on a rising edge of HRTIM update enable input 3
|
|
value: 5
|
|
- name: Input1_Update
|
|
description: Update occurs on the update event following a rising edge of HRTIM update enable input 1
|
|
value: 6
|
|
- name: Input2_Update
|
|
description: Update occurs on the update event following a rising edge of HRTIM update enable input 2
|
|
value: 7
|
|
- name: Input3_Update
|
|
description: Update occurs on the update event following a rising edge of HRTIM update enable input 3
|
|
value: 8
|
|
enum/UPDT:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NoEffect
|
|
description: Update event has no effect
|
|
value: 0
|
|
- name: ResetCounter
|
|
description: Timer X counter is reset upon update event
|
|
value: 1
|