308 lines
12 KiB
YAML
308 lines
12 KiB
YAML
block/ADC_COMMON:
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description: ADC common registers
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items:
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- name: CSR
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description: common status register
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byte_offset: 0
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fieldset: CSR
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- name: CCR
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description: common control register
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byte_offset: 8
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fieldset: CCR
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- name: CDR
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description: common regular data register for dual mode
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byte_offset: 12
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fieldset: CDR
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- name: HWCFGR0
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description: hardware configuration register
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byte_offset: 240
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fieldset: HWCFGR0
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- name: VERR
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description: version register
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byte_offset: 244
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fieldset: VERR
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- name: IPDR
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description: identification register
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byte_offset: 248
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- name: SIDR
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description: size identification register
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byte_offset: 252
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fieldset/CCR:
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description: common control register
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fields:
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- name: DUAL
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description: 'Dual ADC mode selection These bits are written by software to select the operating mode. 0 value means Independent Mode. Values 00001 to 01001 means Dual mode, master and slave ADCs are working together. All other combinations are reserved and must not be programmed Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 0
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bit_size: 5
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enum: DUAL
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- name: DELAY
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description: 'Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to for the value of ADC resolution versus DELAY bits values. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 8
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bit_size: 4
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- name: DMACFG
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description: 'DMA configuration (for dual ADC mode) This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 13
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bit_size: 1
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enum: DMACFG
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- name: MDMA
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description: 'Direct memory access mode for dual ADC mode This bitfield is set and cleared by software. Refer to the DMA controller section for more details. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).'
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bit_offset: 14
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bit_size: 2
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enum: MDMA
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- name: CKMODE
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description: 'ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).'
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bit_offset: 16
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bit_size: 2
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enum: CKMODE
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- name: PRESC
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description: 'ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.'
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bit_offset: 18
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bit_size: 4
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enum: PRESC
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- name: VREFEN
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description: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel
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bit_offset: 22
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bit_size: 1
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- name: TSEN
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description: VSENSE enable This bit is set and cleared by software to control VSENSE
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bit_offset: 23
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bit_size: 1
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- name: VBATEN
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description: VBAT enable This bit is set and cleared by software to control
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bit_offset: 24
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bit_size: 1
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fieldset/CDR:
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description: common regular data register for dual mode
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fields:
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- name: RDATA_MST
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description: Regular data of the master ADC. In dual mode, these bits contain the regular data of the master ADC. Refer to . The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)) In MDMA = 0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains MST_ADC_DR[7:0].
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bit_offset: 0
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bit_size: 16
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- name: RDATA_SLV
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description: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC. Refer to Dual ADC modes. The data alignment is applied as described in offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN)).
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bit_offset: 16
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bit_size: 16
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fieldset/CSR:
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description: common status register
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fields:
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- name: ADRDY_MST
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description: Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
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bit_offset: 0
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bit_size: 1
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- name: EOSMP_MST
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description: End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
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bit_offset: 1
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bit_size: 1
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- name: EOC_MST
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description: End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
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bit_offset: 2
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bit_size: 1
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- name: EOS_MST
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description: End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
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bit_offset: 3
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bit_size: 1
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- name: OVR_MST
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description: Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
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bit_offset: 4
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bit_size: 1
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- name: JEOC_MST
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description: End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
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bit_offset: 5
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bit_size: 1
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- name: JEOS_MST
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description: End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
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bit_offset: 6
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bit_size: 1
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- name: AWD_MST
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description: Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
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bit_offset: 7
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bit_size: 1
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array:
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len: 3
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stride: 1
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- name: JQOVF_MST
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description: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
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bit_offset: 10
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bit_size: 1
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- name: ADRDY_SLV
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description: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
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bit_offset: 16
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bit_size: 1
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- name: EOSMP_SLV
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description: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register.
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bit_offset: 17
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bit_size: 1
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- name: EOC_SLV
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description: End of regular conversion of the slave ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
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bit_offset: 18
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bit_size: 1
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- name: EOS_SLV
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description: End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
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bit_offset: 19
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bit_size: 1
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- name: OVR_SLV
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description: Overrun flag of the slave ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
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bit_offset: 20
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bit_size: 1
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- name: JEOC_SLV
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description: End of injected conversion flag of the slave ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
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bit_offset: 21
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bit_size: 1
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- name: JEOS_SLV
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description: End of injected sequence flag of the slave ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
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bit_offset: 22
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bit_size: 1
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- name: AWD_SLV
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description: Analog watchdog 1 flag of the slave ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
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bit_offset: 23
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bit_size: 1
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array:
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len: 3
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stride: 1
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- name: JQOVF_SLV
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description: Injected Context Queue Overflow flag of the slave ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
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bit_offset: 26
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bit_size: 1
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fieldset/HWCFGR0:
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description: hardware configuration register
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fields:
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- name: ADCNUM
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description: Number of ADCs implemented
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bit_offset: 0
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bit_size: 4
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- name: MULPIPE
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description: Number of pipeline stages
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bit_offset: 4
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bit_size: 4
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- name: OPBITS
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description: 'Number of option bits 0002: 2 option bits implemented in the ADC option register (ADC_OR) at address offset 0xC8.'
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bit_offset: 8
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bit_size: 4
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- name: IDLEVALUE
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description: Idle value for non-selected channels
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bit_offset: 12
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bit_size: 4
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enum: IDLEVALUE
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fieldset/VERR:
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description: version register
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fields:
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- name: MINREV
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description: 'Minor revision These bits returns the ADC IP minor revision 0002: Major revision = X.2.'
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bit_offset: 0
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bit_size: 4
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- name: MAJREV
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description: Major revision These bits returns the ADC IP major revision
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bit_offset: 4
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bit_size: 4
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enum/CKMODE:
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bit_size: 2
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variants:
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- name: Asynchronous
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description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
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value: 0
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- name: SyncDiv1
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description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
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value: 1
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- name: SyncDiv2
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description: Use AHB clock rcc_hclk3 divided by 2
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value: 2
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- name: SyncDiv4
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description: Use AHB clock rcc_hclk3 divided by 4
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value: 3
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enum/DMACFG:
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bit_size: 1
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variants:
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- name: OneShot
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description: DMA One Shot mode selected
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value: 0
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- name: Circular
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description: DMA Circular mode selected
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value: 1
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enum/DUAL:
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bit_size: 5
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variants:
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- name: Independent
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description: Independent mode
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value: 0
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- name: DualRJ
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description: Dual, combined regular simultaneous + injected simultaneous mode
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value: 1
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- name: DualRA
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description: Dual, combined regular simultaneous + alternate trigger mode
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value: 2
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- name: DualIJ
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description: Dual, combined interleaved mode + injected simultaneous mode
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value: 3
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- name: DualJ
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description: Dual, injected simultaneous mode only
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value: 5
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- name: DualR
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description: Dual, regular simultaneous mode only
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value: 6
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- name: DualI
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description: Dual, interleaved mode only
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value: 7
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- name: DualA
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description: Dual, alternate trigger mode only
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value: 9
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enum/IDLEVALUE:
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bit_size: 4
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variants:
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- name: H13
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description: Dummy channel selection is 0x13
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value: 0
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- name: H1F
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description: Dummy channel selection is 0x1F
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value: 1
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enum/MDMA:
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bit_size: 2
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variants:
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- name: NoPack
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description: Without data packing, CDR/CDR2 not used
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value: 0
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- name: Format32to10
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description: CDR formatted for 32-bit down to 10-bit resolution
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value: 2
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- name: Format8
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description: CDR formatted for 8-bit resolution
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value: 3
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enum/PRESC:
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bit_size: 4
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variants:
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- name: Div1
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description: adc_ker_ck_input not divided
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value: 0
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- name: Div2
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description: adc_ker_ck_input divided by 2
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value: 1
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- name: Div4
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description: adc_ker_ck_input divided by 4
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value: 2
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- name: Div6
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description: adc_ker_ck_input divided by 6
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value: 3
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- name: Div8
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description: adc_ker_ck_input divided by 8
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value: 4
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- name: Div10
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description: adc_ker_ck_input divided by 10
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value: 5
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- name: Div12
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description: adc_ker_ck_input divided by 12
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value: 6
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- name: Div16
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description: adc_ker_ck_input divided by 16
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value: 7
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- name: Div32
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description: adc_ker_ck_input divided by 32
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value: 8
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- name: Div64
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description: adc_ker_ck_input divided by 64
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value: 9
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- name: Div128
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description: adc_ker_ck_input divided by 128
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value: 10
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- name: Div256
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description: adc_ker_ck_input divided by 256
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value: 11
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