2180 lines
52 KiB
YAML
2180 lines
52 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- byte_offset: 0
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description: clock control register
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fieldset: CR
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name: CR
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- access: Read
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byte_offset: 8
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description: RCC Clock Recovery RC Register
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fieldset: CRRCR
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name: CRRCR
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- byte_offset: 16
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description: RCC Clock Configuration Register
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fieldset: CFGR
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name: CFGR
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- byte_offset: 24
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description: RCC Domain 1 Clock Configuration Register
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fieldset: D1CFGR
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name: D1CFGR
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- byte_offset: 28
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description: RCC Domain 2 Clock Configuration Register
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fieldset: D2CFGR
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name: D2CFGR
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- byte_offset: 32
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description: RCC Domain 3 Clock Configuration Register
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fieldset: D3CFGR
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name: D3CFGR
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- byte_offset: 40
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description: RCC PLLs Clock Source Selection Register
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fieldset: PLLCKSELR
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name: PLLCKSELR
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- byte_offset: 44
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description: RCC PLLs Configuration Register
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fieldset: PLLCFGR
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name: PLLCFGR
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- byte_offset: 48
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description: RCC PLL1 Dividers Configuration Register
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fieldset: PLL1DIVR
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name: PLL1DIVR
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- byte_offset: 52
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description: RCC PLL1 Fractional Divider Register
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fieldset: PLL1FRACR
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name: PLL1FRACR
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- byte_offset: 56
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description: RCC PLL2 Dividers Configuration Register
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fieldset: PLL2DIVR
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name: PLL2DIVR
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- byte_offset: 60
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description: RCC PLL2 Fractional Divider Register
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fieldset: PLL2FRACR
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name: PLL2FRACR
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- byte_offset: 64
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description: RCC PLL3 Dividers Configuration Register
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fieldset: PLL3DIVR
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name: PLL3DIVR
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- byte_offset: 68
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description: RCC PLL3 Fractional Divider Register
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fieldset: PLL3FRACR
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name: PLL3FRACR
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- byte_offset: 96
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description: RCC Clock Source Interrupt Enable Register
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fieldset: CIER
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name: CIER
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- access: Read
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byte_offset: 100
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description: RCC Clock Source Interrupt Flag Register
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fieldset: CIFR
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name: CIFR
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- byte_offset: 104
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description: RCC Clock Source Interrupt Clear Register
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fieldset: CICR
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name: CICR
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- byte_offset: 112
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description: RCC Backup Domain Control Register
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fieldset: BDCR
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name: BDCR
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- byte_offset: 116
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description: RCC Clock Control and Status Register
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fieldset: CSR
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name: CSR
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- byte_offset: 124
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description: RCC AHB3 Reset Register
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fieldset: AHB3RSTR
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name: AHB3RSTR
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- byte_offset: 128
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description: RCC AHB1 Peripheral Reset Register
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fieldset: AHB1RSTR
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name: AHB1RSTR
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- byte_offset: 132
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description: RCC AHB2 Peripheral Reset Register
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fieldset: AHB2RSTR
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name: AHB2RSTR
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- byte_offset: 136
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description: RCC AHB4 Peripheral Reset Register
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fieldset: AHB4RSTR
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name: AHB4RSTR
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- byte_offset: 140
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description: RCC APB3 Peripheral Reset Register
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fieldset: APB3RSTR
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name: APB3RSTR
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- byte_offset: 144
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description: RCC APB1 Peripheral Reset Register
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fieldset: APB1LRSTR
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name: APB1LRSTR
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- byte_offset: 148
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description: RCC APB1 Peripheral Reset Register
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fieldset: APB1HRSTR
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name: APB1HRSTR
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- byte_offset: 152
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description: RCC APB2 Peripheral Reset Register
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fieldset: APB2RSTR
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name: APB2RSTR
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- byte_offset: 156
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description: RCC APB4 Peripheral Reset Register
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fieldset: APB4RSTR
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name: APB4RSTR
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- byte_offset: 160
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description: Global Control Register
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fieldset: GCR
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name: GCR
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- byte_offset: 168
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description: RCC D3 Autonomous mode Register
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fieldset: D3AMR
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name: D3AMR
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- byte_offset: 304
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description: RCC Reset Status Register
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fieldset: C1_RSR
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name: C1_RSR
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enum/ADCSEL:
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bit_size: 2
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enum/CECSEL:
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bit_size: 2
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enum/CKPERSEL:
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bit_size: 2
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enum/DFSDMSEL:
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bit_size: 1
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enum/DIVP:
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bit_size: 7
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enum/DPPRE:
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bit_size: 3
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enum/FDCANSEL:
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bit_size: 2
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enum/FMCSEL:
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bit_size: 2
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enum/HPRE:
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bit_size: 4
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enum/HRTIMSEL:
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bit_size: 1
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enum/HSEBYP:
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bit_size: 1
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enum/HSIDIV:
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bit_size: 2
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enum/HSIDIVFR:
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bit_size: 1
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enum/HSION:
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bit_size: 1
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enum/HSIRDYR:
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bit_size: 1
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enum/I2C123SEL:
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bit_size: 2
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enum/I2C4SEL:
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bit_size: 2
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enum/LPTIM1SEL:
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bit_size: 3
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enum/LPTIM2SEL:
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bit_size: 3
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enum/LPUARTSEL:
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bit_size: 3
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enum/LSEBYP:
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bit_size: 1
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enum/LSECSSDR:
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bit_size: 1
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enum/LSECSSON:
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bit_size: 1
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enum/LSEDRV:
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bit_size: 2
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enum/LSEON:
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bit_size: 1
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enum/LSERDYR:
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bit_size: 1
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enum/LSION:
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bit_size: 1
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enum/LSIRDYC:
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bit_size: 1
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enum/LSIRDYIE:
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bit_size: 1
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enum/LSIRDYR:
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bit_size: 1
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enum/MCO1:
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bit_size: 3
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enum/MCO2:
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bit_size: 3
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enum/PLLRGE:
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bit_size: 2
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enum/PLLSRC:
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bit_size: 2
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enum/PLLVCOSEL:
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bit_size: 1
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enum/RNGSEL:
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bit_size: 2
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enum/RTCSEL:
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bit_size: 2
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enum/SAIASEL:
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bit_size: 3
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enum/SAISEL:
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bit_size: 3
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enum/SDMMCSEL:
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bit_size: 1
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enum/SPI45SEL:
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bit_size: 3
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enum/SPI6SEL:
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bit_size: 3
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enum/STOPWUCK:
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bit_size: 1
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enum/SW:
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bit_size: 3
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enum/SWPSEL:
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bit_size: 1
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enum/SWSR:
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bit_size: 3
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enum/TIMPRE:
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bit_size: 1
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enum/USART234578SEL:
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bit_size: 3
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enum/USBSEL:
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bit_size: 2
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enum/WWRSC:
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bit_size: 1
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fieldset/AHB1ENR:
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description: RCC AHB1 Clock Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA1 Clock Enable
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name: DMA1EN
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- bit_offset: 1
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bit_size: 1
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description: DMA2 Clock Enable
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name: DMA2EN
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- bit_offset: 5
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bit_size: 1
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description: ADC1/2 Peripheral Clocks Enable
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name: ADC12EN
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- bit_offset: 15
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bit_size: 1
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description: Ethernet MAC bus interface Clock Enable
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name: ETH1MACEN
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- bit_offset: 16
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bit_size: 1
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description: Ethernet Transmission Clock Enable
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name: ETH1TXEN
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- bit_offset: 17
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bit_size: 1
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description: Ethernet Reception Clock Enable
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name: ETH1RXEN
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- bit_offset: 25
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bit_size: 1
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description: USB1OTG Peripheral Clocks Enable
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name: USB1OTGEN
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- bit_offset: 26
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bit_size: 1
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description: USB_PHY1 Clocks Enable
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name: USB1ULPIEN
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fieldset/AHB1LPENR:
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description: RCC AHB1 Sleep Clock Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA1 Clock Enable During CSleep Mode
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name: DMA1LPEN
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- bit_offset: 1
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bit_size: 1
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description: DMA2 Clock Enable During CSleep Mode
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name: DMA2LPEN
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- bit_offset: 5
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bit_size: 1
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description: ADC1/2 Peripheral Clocks Enable During CSleep Mode
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name: ADC12LPEN
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- bit_offset: 15
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bit_size: 1
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description: Ethernet MAC bus interface Clock Enable During CSleep Mode
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name: ETH1MACLPEN
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- bit_offset: 16
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bit_size: 1
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description: Ethernet Transmission Clock Enable During CSleep Mode
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name: ETH1TXLPEN
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- bit_offset: 17
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bit_size: 1
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description: Ethernet Reception Clock Enable During CSleep Mode
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name: ETH1RXLPEN
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- bit_offset: 25
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bit_size: 1
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description: USB1OTG peripheral clock enable during CSleep mode
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name: USB1OTGLPEN
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fieldset/AHB1RSTR:
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description: RCC AHB1 Peripheral Reset Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA1 block reset
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name: DMA1RST
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- bit_offset: 1
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bit_size: 1
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description: DMA2 block reset
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name: DMA2RST
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- bit_offset: 5
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bit_size: 1
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description: ADC1&2 block reset
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name: ADC12RST
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- bit_offset: 15
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bit_size: 1
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description: ETH1MAC block reset
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name: ETH1MACRST
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- bit_offset: 25
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bit_size: 1
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description: USB1OTG block reset
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name: USB1OTGRST
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- bit_offset: 27
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bit_size: 1
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description: USB2OTG block reset
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name: USB2OTGRST
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fieldset/AHB2ENR:
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description: RCC AHB2 Clock Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DCMI peripheral clock
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name: DCMIEN
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- bit_offset: 4
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bit_size: 1
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description: CRYPT peripheral clock enable
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name: CRYPTEN
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- bit_offset: 5
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bit_size: 1
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description: HASH peripheral clock enable
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name: HASHEN
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- bit_offset: 6
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bit_size: 1
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description: RNG peripheral clocks enable
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name: RNGEN
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- bit_offset: 9
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bit_size: 1
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description: SDMMC2 and SDMMC2 delay clock enable
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name: SDMMC2EN
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- bit_offset: 29
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bit_size: 1
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description: SRAM1 block enable
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name: SRAM1EN
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- bit_offset: 30
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bit_size: 1
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description: SRAM2 block enable
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name: SRAM2EN
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- bit_offset: 31
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bit_size: 1
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description: SRAM3 block enable
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name: SRAM3EN
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fieldset/AHB2LPENR:
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description: RCC AHB2 Sleep Clock Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DCMI peripheral clock enable during csleep mode
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name: DCMILPEN
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- bit_offset: 4
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bit_size: 1
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description: CRYPT peripheral clock enable during CSleep mode
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name: CRYPTLPEN
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- bit_offset: 5
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bit_size: 1
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description: HASH peripheral clock enable during CSleep mode
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name: HASHLPEN
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- bit_offset: 6
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bit_size: 1
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description: RNG peripheral clock enable during CSleep mode
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name: RNGLPEN
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- bit_offset: 9
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bit_size: 1
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description: SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode
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name: SDMMC2LPEN
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- bit_offset: 29
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bit_size: 1
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description: SRAM1 Clock Enable During CSleep Mode
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name: SRAM1LPEN
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- bit_offset: 30
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bit_size: 1
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description: SRAM2 Clock Enable During CSleep Mode
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name: SRAM2LPEN
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- bit_offset: 31
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bit_size: 1
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description: SRAM3 Clock Enable During CSleep Mode
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name: SRAM3LPEN
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fieldset/AHB2RSTR:
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description: RCC AHB2 Peripheral Reset Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: CAMITF block reset
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name: CAMITFRST
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- bit_offset: 4
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bit_size: 1
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description: Cryptography block reset
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name: CRYPTRST
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- bit_offset: 5
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bit_size: 1
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description: Hash block reset
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name: HASHRST
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- bit_offset: 6
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bit_size: 1
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description: Random Number Generator block reset
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name: RNGRST
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- bit_offset: 9
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bit_size: 1
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description: SDMMC2 and SDMMC2 Delay block reset
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name: SDMMC2RST
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fieldset/AHB3ENR:
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description: RCC AHB3 Clock Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: MDMA Peripheral Clock Enable
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name: MDMAEN
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- bit_offset: 4
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bit_size: 1
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description: DMA2D Peripheral Clock Enable
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name: DMA2DEN
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- bit_offset: 5
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bit_size: 1
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description: JPGDEC Peripheral Clock Enable
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name: JPGDECEN
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- bit_offset: 12
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bit_size: 1
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description: FMC Peripheral Clocks Enable
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name: FMCEN
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- bit_offset: 14
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bit_size: 1
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description: QUADSPI and QUADSPI Delay Clock Enable
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name: QSPIEN
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- bit_offset: 16
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bit_size: 1
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description: SDMMC1 and SDMMC1 Delay Clock Enable
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name: SDMMC1EN
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fieldset/AHB3LPENR:
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description: RCC AHB3 Sleep Clock Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: MDMA Clock Enable During CSleep Mode
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name: MDMALPEN
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- bit_offset: 4
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bit_size: 1
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description: DMA2D Clock Enable During CSleep Mode
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name: DMA2DLPEN
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- bit_offset: 5
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bit_size: 1
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description: JPGDEC Clock Enable During CSleep Mode
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name: JPGDECLPEN
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- bit_offset: 12
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bit_size: 1
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description: FMC Peripheral Clocks Enable During CSleep Mode
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name: FMCLPEN
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- bit_offset: 14
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bit_size: 1
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description: QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode
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name: QSPILPEN
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- bit_offset: 16
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bit_size: 1
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description: SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode
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name: SDMMC1LPEN
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- bit_offset: 28
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bit_size: 1
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description: D1DTCM1 Block Clock Enable During CSleep mode
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name: D1DTCM1LPEN
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- bit_offset: 29
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bit_size: 1
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description: D1 DTCM2 Block Clock Enable During CSleep mode
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name: DTCM2LPEN
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- bit_offset: 30
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bit_size: 1
|
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description: D1ITCM Block Clock Enable During CSleep mode
|
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name: ITCMLPEN
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- bit_offset: 31
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bit_size: 1
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description: AXISRAM Block Clock Enable During CSleep mode
|
|
name: AXISRAMLPEN
|
|
fieldset/AHB3RSTR:
|
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description: RCC AHB3 Reset Register
|
|
fields:
|
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- bit_offset: 0
|
|
bit_size: 1
|
|
description: MDMA block reset
|
|
name: MDMARST
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: DMA2D block reset
|
|
name: DMA2DRST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: JPGDEC block reset
|
|
name: JPGDECRST
|
|
- bit_offset: 12
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|
bit_size: 1
|
|
description: FMC block reset
|
|
name: FMCRST
|
|
- bit_offset: 14
|
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bit_size: 1
|
|
description: QUADSPI and QUADSPI delay block reset
|
|
name: QSPIRST
|
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- bit_offset: 16
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bit_size: 1
|
|
description: SDMMC1 and SDMMC1 delay block reset
|
|
name: SDMMC1RST
|
|
- bit_offset: 31
|
|
bit_size: 1
|
|
description: CPU reset
|
|
name: CPURST
|
|
fieldset/AHB4ENR:
|
|
description: RCC AHB4 Clock Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOAEN
|
|
- bit_offset: 1
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bit_size: 1
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|
description: 0GPIO peripheral clock enable
|
|
name: GPIOBEN
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOCEN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIODEN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOEEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOFEN
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOGEN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOHEN
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOIEN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOJEN
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: 0GPIO peripheral clock enable
|
|
name: GPIOKEN
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: CRC peripheral clock enable
|
|
name: CRCEN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: BDMA and DMAMUX2 Clock Enable
|
|
name: BDMAEN
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: ADC3 Peripheral Clocks Enable
|
|
name: ADC3EN
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: HSEM peripheral clock enable
|
|
name: HSEMEN
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: Backup RAM Clock Enable
|
|
name: BKPRAMEN
|
|
fieldset/AHB4LPENR:
|
|
description: RCC AHB4 Sleep Clock Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOALPEN
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOBLPEN
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOCLPEN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIODLPEN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOELPEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOFLPEN
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOGLPEN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOHLPEN
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOILPEN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOJLPEN
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: GPIO peripheral clock enable during CSleep mode
|
|
name: GPIOKLPEN
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: CRC peripheral clock enable during CSleep mode
|
|
name: CRCLPEN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: BDMA Clock Enable During CSleep Mode
|
|
name: BDMALPEN
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: ADC3 Peripheral Clocks Enable During CSleep Mode
|
|
name: ADC3LPEN
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: Backup RAM Clock Enable During CSleep Mode
|
|
name: BKPRAMLPEN
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: SRAM4 Clock Enable During CSleep Mode
|
|
name: SRAM4LPEN
|
|
fieldset/AHB4RSTR:
|
|
description: RCC AHB4 Peripheral Reset Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOARST
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOBRST
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOCRST
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIODRST
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOERST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOFRST
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOGRST
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOHRST
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOIRST
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOJRST
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: GPIO block reset
|
|
name: GPIOKRST
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: CRC block reset
|
|
name: CRCRST
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: BDMA block reset
|
|
name: BDMARST
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: ADC3 block reset
|
|
name: ADC3RST
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: HSEM block reset
|
|
name: HSEMRST
|
|
fieldset/APB1HENR:
|
|
description: RCC APB1 Clock Register
|
|
fields:
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Clock Recovery System peripheral clock enable
|
|
name: CRSEN
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: SWPMI Peripheral Clocks Enable
|
|
name: SWPEN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: OPAMP peripheral clock enable
|
|
name: OPAMPEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: MDIOS peripheral clock enable
|
|
name: MDIOSEN
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: FDCAN Peripheral Clocks Enable
|
|
name: FDCANEN
|
|
fieldset/APB1HLPENR:
|
|
description: RCC APB1 High Sleep Clock Register
|
|
fields:
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Clock Recovery System peripheral clock enable during CSleep mode
|
|
name: CRSLPEN
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: SWPMI Peripheral Clocks Enable During CSleep Mode
|
|
name: SWPLPEN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: OPAMP peripheral clock enable during CSleep mode
|
|
name: OPAMPLPEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: MDIOS peripheral clock enable during CSleep mode
|
|
name: MDIOSLPEN
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: FDCAN Peripheral Clocks Enable During CSleep Mode
|
|
name: FDCANLPEN
|
|
fieldset/APB1HRSTR:
|
|
description: RCC APB1 Peripheral Reset Register
|
|
fields:
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Clock Recovery System reset
|
|
name: CRSRST
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: SWPMI block reset
|
|
name: SWPRST
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: OPAMP block reset
|
|
name: OPAMPRST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: MDIOS block reset
|
|
name: MDIOSRST
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: FDCAN block reset
|
|
name: FDCANRST
|
|
fieldset/APB1LENR:
|
|
description: RCC APB1 Clock Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM2EN
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM3EN
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM4EN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM5EN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM6EN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM7EN
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM12EN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM13EN
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: TIM peripheral clock enable
|
|
name: TIM14EN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LPTIM1 Peripheral Clocks Enable
|
|
name: LPTIM1EN
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: SPI2 Peripheral Clocks Enable
|
|
name: SPI2EN
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: SPI3 Peripheral Clocks Enable
|
|
name: SPI3EN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: SPDIFRX Peripheral Clocks Enable
|
|
name: SPDIFRXEN
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: USART2 Peripheral Clocks Enable
|
|
name: USART2EN
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: USART3 Peripheral Clocks Enable
|
|
name: USART3EN
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: UART4 Peripheral Clocks Enable
|
|
name: UART4EN
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: UART5 Peripheral Clocks Enable
|
|
name: UART5EN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: I2C1 Peripheral Clocks Enable
|
|
name: I2C1EN
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: I2C2 Peripheral Clocks Enable
|
|
name: I2C2EN
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: I2C3 Peripheral Clocks Enable
|
|
name: I2C3EN
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: HDMI-CEC peripheral clock enable
|
|
name: CECEN
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: UART7 Peripheral Clocks Enable
|
|
name: UART7EN
|
|
- bit_offset: 31
|
|
bit_size: 1
|
|
description: UART8 Peripheral Clocks Enable
|
|
name: UART8EN
|
|
fieldset/APB1LLPENR:
|
|
description: RCC APB1 Low Sleep Clock Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: TIM2 peripheral clock enable during CSleep mode
|
|
name: TIM2LPEN
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: TIM3 peripheral clock enable during CSleep mode
|
|
name: TIM3LPEN
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: TIM4 peripheral clock enable during CSleep mode
|
|
name: TIM4LPEN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: TIM5 peripheral clock enable during CSleep mode
|
|
name: TIM5LPEN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: TIM6 peripheral clock enable during CSleep mode
|
|
name: TIM6LPEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: TIM7 peripheral clock enable during CSleep mode
|
|
name: TIM7LPEN
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: TIM12 peripheral clock enable during CSleep mode
|
|
name: TIM12LPEN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: TIM13 peripheral clock enable during CSleep mode
|
|
name: TIM13LPEN
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: TIM14 peripheral clock enable during CSleep mode
|
|
name: TIM14LPEN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LPTIM1 Peripheral Clocks Enable During CSleep Mode
|
|
name: LPTIM1LPEN
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: SPI2 Peripheral Clocks Enable During CSleep Mode
|
|
name: SPI2LPEN
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: SPI3 Peripheral Clocks Enable During CSleep Mode
|
|
name: SPI3LPEN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: SPDIFRX Peripheral Clocks Enable During CSleep Mode
|
|
name: SPDIFRXLPEN
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: USART2 Peripheral Clocks Enable During CSleep Mode
|
|
name: USART2LPEN
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: USART3 Peripheral Clocks Enable During CSleep Mode
|
|
name: USART3LPEN
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: UART4 Peripheral Clocks Enable During CSleep Mode
|
|
name: UART4LPEN
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: UART5 Peripheral Clocks Enable During CSleep Mode
|
|
name: UART5LPEN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: I2C1 Peripheral Clocks Enable During CSleep Mode
|
|
name: I2C1LPEN
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: I2C2 Peripheral Clocks Enable During CSleep Mode
|
|
name: I2C2LPEN
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: I2C3 Peripheral Clocks Enable During CSleep Mode
|
|
name: I2C3LPEN
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: HDMI-CEC Peripheral Clocks Enable During CSleep Mode
|
|
name: CECLPEN
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: UART7 Peripheral Clocks Enable During CSleep Mode
|
|
name: UART7LPEN
|
|
- bit_offset: 31
|
|
bit_size: 1
|
|
description: UART8 Peripheral Clocks Enable During CSleep Mode
|
|
name: UART8LPEN
|
|
fieldset/APB1LRSTR:
|
|
description: RCC APB1 Peripheral Reset Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM2RST
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM3RST
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM4RST
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM5RST
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM6RST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM7RST
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM12RST
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM13RST
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: TIM14RST
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: TIM block reset
|
|
name: LPTIM1RST
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: SPI2 block reset
|
|
name: SPI2RST
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: SPI3 block reset
|
|
name: SPI3RST
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: SPDIFRX block reset
|
|
name: SPDIFRXRST
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: USART2 block reset
|
|
name: USART2RST
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: USART3 block reset
|
|
name: USART3RST
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: UART4 block reset
|
|
name: UART4RST
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: UART5 block reset
|
|
name: UART5RST
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: I2C1 block reset
|
|
name: I2C1RST
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: I2C2 block reset
|
|
name: I2C2RST
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: I2C3 block reset
|
|
name: I2C3RST
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: HDMI-CEC block reset
|
|
name: CECRST
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: UART7 block reset
|
|
name: UART7RST
|
|
- bit_offset: 31
|
|
bit_size: 1
|
|
description: UART8 block reset
|
|
name: UART8RST
|
|
fieldset/APB2ENR:
|
|
description: RCC APB2 Clock Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: TIM1 peripheral clock enable
|
|
name: TIM1EN
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: TIM8 peripheral clock enable
|
|
name: TIM8EN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: USART1 Peripheral Clocks Enable
|
|
name: USART1EN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: USART6 Peripheral Clocks Enable
|
|
name: USART6EN
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: SPI1 Peripheral Clocks Enable
|
|
name: SPI1EN
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: SPI4 Peripheral Clocks Enable
|
|
name: SPI4EN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: TIM15 peripheral clock enable
|
|
name: TIM15EN
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: TIM16 peripheral clock enable
|
|
name: TIM16EN
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: TIM17 peripheral clock enable
|
|
name: TIM17EN
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: SPI5 Peripheral Clocks Enable
|
|
name: SPI5EN
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: SAI1 Peripheral Clocks Enable
|
|
name: SAI1EN
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: SAI2 Peripheral Clocks Enable
|
|
name: SAI2EN
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: SAI3 Peripheral Clocks Enable
|
|
name: SAI3EN
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: DFSDM1 Peripheral Clocks Enable
|
|
name: DFSDM1EN
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: HRTIM peripheral clock enable
|
|
name: HRTIMEN
|
|
fieldset/APB2LPENR:
|
|
description: RCC APB2 Sleep Clock Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: TIM1 peripheral clock enable during CSleep mode
|
|
name: TIM1LPEN
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: TIM8 peripheral clock enable during CSleep mode
|
|
name: TIM8LPEN
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: USART1 Peripheral Clocks Enable During CSleep Mode
|
|
name: USART1LPEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: USART6 Peripheral Clocks Enable During CSleep Mode
|
|
name: USART6LPEN
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: SPI1 Peripheral Clocks Enable During CSleep Mode
|
|
name: SPI1LPEN
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: SPI4 Peripheral Clocks Enable During CSleep Mode
|
|
name: SPI4LPEN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: TIM15 peripheral clock enable during CSleep mode
|
|
name: TIM15LPEN
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: TIM16 peripheral clock enable during CSleep mode
|
|
name: TIM16LPEN
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: TIM17 peripheral clock enable during CSleep mode
|
|
name: TIM17LPEN
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: SPI5 Peripheral Clocks Enable During CSleep Mode
|
|
name: SPI5LPEN
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: SAI1 Peripheral Clocks Enable During CSleep Mode
|
|
name: SAI1LPEN
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: SAI2 Peripheral Clocks Enable During CSleep Mode
|
|
name: SAI2LPEN
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: SAI3 Peripheral Clocks Enable During CSleep Mode
|
|
name: SAI3LPEN
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: DFSDM1 Peripheral Clocks Enable During CSleep Mode
|
|
name: DFSDM1LPEN
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: HRTIM peripheral clock enable during CSleep mode
|
|
name: HRTIMLPEN
|
|
fieldset/APB2RSTR:
|
|
description: RCC APB2 Peripheral Reset Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: TIM1 block reset
|
|
name: TIM1RST
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: TIM8 block reset
|
|
name: TIM8RST
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: USART1 block reset
|
|
name: USART1RST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: USART6 block reset
|
|
name: USART6RST
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: SPI1 block reset
|
|
name: SPI1RST
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: SPI4 block reset
|
|
name: SPI4RST
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: TIM15 block reset
|
|
name: TIM15RST
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: TIM16 block reset
|
|
name: TIM16RST
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: TIM17 block reset
|
|
name: TIM17RST
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: SPI5 block reset
|
|
name: SPI5RST
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: SAI1 block reset
|
|
name: SAI1RST
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: SAI2 block reset
|
|
name: SAI2RST
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: SAI3 block reset
|
|
name: SAI3RST
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: DFSDM1 block reset
|
|
name: DFSDM1RST
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: HRTIM block reset
|
|
name: HRTIMRST
|
|
fieldset/APB3ENR:
|
|
description: RCC APB3 Clock Register
|
|
fields:
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: LTDC peripheral clock enable
|
|
name: LTDCEN
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: WWDG1 Clock Enable
|
|
name: WWDG1EN
|
|
fieldset/APB3LPENR:
|
|
description: RCC APB3 Sleep Clock Register
|
|
fields:
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: LTDC peripheral clock enable during CSleep mode
|
|
name: LTDCLPEN
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: WWDG1 Clock Enable During CSleep Mode
|
|
name: WWDG1LPEN
|
|
fieldset/APB3RSTR:
|
|
description: RCC APB3 Peripheral Reset Register
|
|
fields:
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: LTDC block reset
|
|
name: LTDCRST
|
|
fieldset/APB4ENR:
|
|
description: RCC APB4 Clock Register
|
|
fields:
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: SYSCFG peripheral clock enable
|
|
name: SYSCFGEN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: LPUART1 Peripheral Clocks Enable
|
|
name: LPUART1EN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: SPI6 Peripheral Clocks Enable
|
|
name: SPI6EN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: I2C4 Peripheral Clocks Enable
|
|
name: I2C4EN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LPTIM2 Peripheral Clocks Enable
|
|
name: LPTIM2EN
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: LPTIM3 Peripheral Clocks Enable
|
|
name: LPTIM3EN
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: COMP1/2 peripheral clock enable
|
|
name: COMP12EN
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: VREF peripheral clock enable
|
|
name: VREFEN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: RTC APB Clock Enable
|
|
name: RTCAPBEN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: SAI4 Peripheral Clocks Enable
|
|
name: SAI4EN
|
|
fieldset/APB4LPENR:
|
|
description: RCC APB4 Sleep Clock Register
|
|
fields:
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: SYSCFG peripheral clock enable during CSleep mode
|
|
name: SYSCFGLPEN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: LPUART1 Peripheral Clocks Enable During CSleep Mode
|
|
name: LPUART1LPEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: SPI6 Peripheral Clocks Enable During CSleep Mode
|
|
name: SPI6LPEN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: I2C4 Peripheral Clocks Enable During CSleep Mode
|
|
name: I2C4LPEN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LPTIM2 Peripheral Clocks Enable During CSleep Mode
|
|
name: LPTIM2LPEN
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: LPTIM3 Peripheral Clocks Enable During CSleep Mode
|
|
name: LPTIM3LPEN
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: COMP1/2 peripheral clock enable during CSleep mode
|
|
name: COMP12LPEN
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: VREF peripheral clock enable during CSleep mode
|
|
name: VREFLPEN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: RTC APB Clock Enable During CSleep Mode
|
|
name: RTCAPBLPEN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: SAI4 Peripheral Clocks Enable During CSleep Mode
|
|
name: SAI4LPEN
|
|
fieldset/APB4RSTR:
|
|
description: RCC APB4 Peripheral Reset Register
|
|
fields:
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: SYSCFG block reset
|
|
name: SYSCFGRST
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: LPUART1 block reset
|
|
name: LPUART1RST
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: SPI6 block reset
|
|
name: SPI6RST
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: I2C4 block reset
|
|
name: I2C4RST
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LPTIM2 block reset
|
|
name: LPTIM2RST
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: LPTIM3 block reset
|
|
name: LPTIM3RST
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: COMP12 Blocks Reset
|
|
name: COMP12RST
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: VREF block reset
|
|
name: VREFRST
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: SAI4 block reset
|
|
name: SAI4RST
|
|
fieldset/BDCR:
|
|
description: RCC Backup Domain Control Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: LSE oscillator enabled
|
|
enum: LSEON
|
|
name: LSEON
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: LSE oscillator ready
|
|
enum_read: LSERDYR
|
|
name: LSERDY
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: LSE oscillator bypass
|
|
enum: LSEBYP
|
|
name: LSEBYP
|
|
- bit_offset: 3
|
|
bit_size: 2
|
|
description: LSE oscillator driving capability
|
|
enum: LSEDRV
|
|
name: LSEDRV
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: LSE clock security system enable
|
|
enum: LSECSSON
|
|
name: LSECSSON
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: LSE clock security system failure detection
|
|
enum_read: LSECSSDR
|
|
name: LSECSSD
|
|
- bit_offset: 8
|
|
bit_size: 2
|
|
description: RTC clock source selection
|
|
enum: RTCSEL
|
|
name: RTCSEL
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: RTC clock enable
|
|
name: RTCEN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: VSwitch domain software reset
|
|
name: BDRST
|
|
fieldset/C1_RSR:
|
|
description: RCC Reset Status Register
|
|
fields:
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: Remove reset flag
|
|
enum: RMVF
|
|
name: RMVF
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: CPU reset flag
|
|
enum_read: CPURSTFR
|
|
name: CPURSTF
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: D1 domain power switch reset flag
|
|
enum_read: CPURSTFR
|
|
name: D1RSTF
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: D2 domain power switch reset flag
|
|
enum_read: CPURSTFR
|
|
name: D2RSTF
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: BOR reset flag
|
|
enum_read: CPURSTFR
|
|
name: BORRSTF
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: Pin reset flag (NRST)
|
|
enum_read: CPURSTFR
|
|
name: PINRSTF
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: POR/PDR reset flag
|
|
enum_read: CPURSTFR
|
|
name: PORRSTF
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: System reset from CPU reset flag
|
|
enum_read: CPURSTFR
|
|
name: SFTRSTF
|
|
- bit_offset: 26
|
|
bit_size: 1
|
|
description: Independent Watchdog reset flag
|
|
enum_read: CPURSTFR
|
|
name: IWDG1RSTF
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: Window Watchdog reset flag
|
|
enum_read: CPURSTFR
|
|
name: WWDG1RSTF
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: Reset due to illegal D1 DStandby or CPU CStop flag
|
|
enum_read: CPURSTFR
|
|
name: LPWRRSTF
|
|
fieldset/CFGR:
|
|
description: RCC Clock Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 3
|
|
description: System clock switch
|
|
enum: SW
|
|
name: SW
|
|
- bit_offset: 3
|
|
bit_size: 3
|
|
description: System clock switch status
|
|
enum_read: SWSR
|
|
name: SWS
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: System clock selection after a wake up from system Stop
|
|
enum: STOPWUCK
|
|
name: STOPWUCK
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: Kernel clock selection after a wake up from system Stop
|
|
enum: STOPWUCK
|
|
name: STOPKERWUCK
|
|
- bit_offset: 8
|
|
bit_size: 6
|
|
description: HSE division factor for RTC clock
|
|
name: RTCPRE
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: High Resolution Timer clock prescaler selection
|
|
enum: HRTIMSEL
|
|
name: HRTIMSEL
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: Timers clocks prescaler selection
|
|
enum: TIMPRE
|
|
name: TIMPRE
|
|
- bit_offset: 18
|
|
bit_size: 4
|
|
description: MCO1 prescaler
|
|
name: MCO1PRE
|
|
- array:
|
|
len: 2
|
|
stride: 7
|
|
bit_offset: 22
|
|
bit_size: 3
|
|
description: Micro-controller clock output 1
|
|
enum: MCO1
|
|
name: MCO
|
|
- bit_offset: 25
|
|
bit_size: 4
|
|
description: MCO2 prescaler
|
|
name: MCO2PRE
|
|
fieldset/CICR:
|
|
description: RCC Clock Source Interrupt Clear Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: LSI ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: LSIRDYC
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: LSE ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: LSERDYC
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: HSI ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: HSIRDYC
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: HSE ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: HSERDYC
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: CSI ready Interrupt Clear
|
|
name: HSE_ready_Interrupt_Clear
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: RC48 ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: HSI48RDYC
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: PLL1 ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: PLL1RDYC
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: PLL2 ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: PLL2RDYC
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: PLL3 ready Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: PLL3RDYC
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LSE clock security system Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: LSECSSC
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: HSE clock security system Interrupt Clear
|
|
enum: LSIRDYC
|
|
name: HSECSSC
|
|
fieldset/CIER:
|
|
description: RCC Clock Source Interrupt Enable Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: LSI ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: LSIRDYIE
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: LSE ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: LSERDYIE
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: HSI ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: HSIRDYIE
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: HSE ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: HSERDYIE
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: CSI ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: CSIRDYIE
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: RC48 ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: HSI48RDYIE
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: PLL1 ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: PLL1RDYIE
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: PLL2 ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: PLL2RDYIE
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: PLL3 ready Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: PLL3RDYIE
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LSE clock security system Interrupt Enable
|
|
enum: LSIRDYIE
|
|
name: LSECSSIE
|
|
fieldset/CIFR:
|
|
description: RCC Clock Source Interrupt Flag Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: LSI ready Interrupt Flag
|
|
name: LSIRDYF
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: LSE ready Interrupt Flag
|
|
name: LSERDYF
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: HSI ready Interrupt Flag
|
|
name: HSIRDYF
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: HSE ready Interrupt Flag
|
|
name: HSERDYF
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: CSI ready Interrupt Flag
|
|
name: CSIRDY
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: RC48 ready Interrupt Flag
|
|
name: HSI48RDYF
|
|
- bit_offset: 6
|
|
bit_size: 1
|
|
description: PLL1 ready Interrupt Flag
|
|
name: PLL1RDYF
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: PLL2 ready Interrupt Flag
|
|
name: PLL2RDYF
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: PLL3 ready Interrupt Flag
|
|
name: PLL3RDYF
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LSE clock security system Interrupt Flag
|
|
name: LSECSSF
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: HSE clock security system Interrupt Flag
|
|
name: HSECSSF
|
|
fieldset/CR:
|
|
description: clock control register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Internal high-speed clock enable
|
|
enum: HSION
|
|
name: HSION
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: High Speed Internal clock enable in Stop mode
|
|
enum: HSION
|
|
name: HSIKERON
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: HSI clock ready flag
|
|
enum_read: HSIRDYR
|
|
name: HSIRDY
|
|
- bit_offset: 3
|
|
bit_size: 2
|
|
description: HSI clock divider
|
|
enum: HSIDIV
|
|
name: HSIDIV
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: HSI divider flag
|
|
enum_read: HSIDIVFR
|
|
name: HSIDIVF
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: CSI clock enable
|
|
enum: HSION
|
|
name: CSION
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: CSI clock ready flag
|
|
enum_read: HSIRDYR
|
|
name: CSIRDY
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: CSI clock enable in Stop mode
|
|
enum: HSION
|
|
name: CSIKERON
|
|
- bit_offset: 12
|
|
bit_size: 1
|
|
description: RC48 clock enable
|
|
enum: HSION
|
|
name: HSI48ON
|
|
- bit_offset: 13
|
|
bit_size: 1
|
|
description: RC48 clock ready flag
|
|
enum_read: HSIRDYR
|
|
name: HSI48RDY
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: D1 domain clocks ready flag
|
|
enum_read: HSIRDYR
|
|
name: D1CKRDY
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: D2 domain clocks ready flag
|
|
enum_read: HSIRDYR
|
|
name: D2CKRDY
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: HSE clock enable
|
|
enum: HSION
|
|
name: HSEON
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: HSE clock ready flag
|
|
enum_read: HSIRDYR
|
|
name: HSERDY
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: HSE clock bypass
|
|
enum: HSEBYP
|
|
name: HSEBYP
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: HSE Clock Security System enable
|
|
enum: HSION
|
|
name: HSECSSON
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: PLL1 enable
|
|
enum: HSION
|
|
name: PLL1ON
|
|
- bit_offset: 25
|
|
bit_size: 1
|
|
description: PLL1 clock ready flag
|
|
enum_read: HSIRDYR
|
|
name: PLL1RDY
|
|
- bit_offset: 26
|
|
bit_size: 1
|
|
description: PLL2 enable
|
|
enum: HSION
|
|
name: PLL2ON
|
|
- bit_offset: 27
|
|
bit_size: 1
|
|
description: PLL2 clock ready flag
|
|
enum_read: HSIRDYR
|
|
name: PLL2RDY
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: PLL3 enable
|
|
enum: HSION
|
|
name: PLL3ON
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: PLL3 clock ready flag
|
|
enum_read: HSIRDYR
|
|
name: PLL3RDY
|
|
fieldset/CRRCR:
|
|
description: RCC Clock Recovery RC Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 10
|
|
description: Internal RC 48 MHz clock calibration
|
|
name: HSI48CAL
|
|
fieldset/CSR:
|
|
description: RCC Clock Control and Status Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: LSI oscillator enable
|
|
enum: LSION
|
|
name: LSION
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: LSI oscillator ready
|
|
enum_read: LSIRDYR
|
|
name: LSIRDY
|
|
fieldset/D1CFGR:
|
|
description: RCC Domain 1 Clock Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 4
|
|
description: D1 domain AHB prescaler
|
|
enum: HPRE
|
|
name: HPRE
|
|
- bit_offset: 4
|
|
bit_size: 3
|
|
description: D1 domain APB3 prescaler
|
|
enum: DPPRE
|
|
name: D1PPRE
|
|
- bit_offset: 8
|
|
bit_size: 4
|
|
description: D1 domain Core prescaler
|
|
enum: HPRE
|
|
name: D1CPRE
|
|
fieldset/D2CFGR:
|
|
description: RCC Domain 2 Clock Configuration Register
|
|
fields:
|
|
- bit_offset: 4
|
|
bit_size: 3
|
|
description: D2 domain APB1 prescaler
|
|
enum: DPPRE
|
|
name: D2PPRE1
|
|
- bit_offset: 8
|
|
bit_size: 3
|
|
description: D2 domain APB2 prescaler
|
|
enum: DPPRE
|
|
name: D2PPRE2
|
|
fieldset/D3AMR:
|
|
description: RCC D3 Autonomous mode Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: BDMA and DMAMUX Autonomous mode enable
|
|
name: BDMAAMEN
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: LPUART1 Autonomous mode enable
|
|
name: LPUART1AMEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: SPI6 Autonomous mode enable
|
|
name: SPI6AMEN
|
|
- bit_offset: 7
|
|
bit_size: 1
|
|
description: I2C4 Autonomous mode enable
|
|
name: I2C4AMEN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: LPTIM2 Autonomous mode enable
|
|
name: LPTIM2AMEN
|
|
- bit_offset: 10
|
|
bit_size: 1
|
|
description: LPTIM3 Autonomous mode enable
|
|
name: LPTIM3AMEN
|
|
- bit_offset: 14
|
|
bit_size: 1
|
|
description: COMP12 Autonomous mode enable
|
|
name: COMP12AMEN
|
|
- bit_offset: 15
|
|
bit_size: 1
|
|
description: VREF Autonomous mode enable
|
|
name: VREFAMEN
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: RTC Autonomous mode enable
|
|
name: RTCAMEN
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: CRC Autonomous mode enable
|
|
name: CRCAMEN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: SAI4 Autonomous mode enable
|
|
name: SAI4AMEN
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: ADC3 Autonomous mode enable
|
|
name: ADC3AMEN
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: SRAM4 Autonomous mode enable
|
|
name: SRAM4AMEN
|
|
fieldset/D3CFGR:
|
|
description: RCC Domain 3 Clock Configuration Register
|
|
fields:
|
|
- bit_offset: 4
|
|
bit_size: 3
|
|
description: D3 domain APB4 prescaler
|
|
enum: DPPRE
|
|
name: D3PPRE
|
|
fieldset/GCR:
|
|
description: RCC Global Control Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: WWDG1 reset scope control
|
|
enum: WWRSC
|
|
name: WW1RSC
|
|
fieldset/PLL1DIVR:
|
|
description: RCC PLL1 Dividers Configuration Register
|
|
fields:
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
description: Multiplication factor for PLL1 VCO
|
|
name: DIVN
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 9
|
|
bit_size: 7
|
|
description: PLL1 DIVP division factor
|
|
enum: DIVP
|
|
name: DIVP
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
description: PLL1 DIVQ division factor
|
|
name: DIVQ
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
description: PLL1 DIVR division factor
|
|
name: DIVR
|
|
fieldset/PLL1FRACR:
|
|
description: RCC PLL1 Fractional Divider Register
|
|
fields:
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 3
|
|
bit_size: 13
|
|
description: Fractional part of the multiplication factor for PLL1 VCO
|
|
name: FRACN
|
|
fieldset/PLL2DIVR:
|
|
description: RCC PLL2 Dividers Configuration Register
|
|
fields:
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
description: Multiplication factor for PLL1 VCO
|
|
name: DIVN
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 9
|
|
bit_size: 7
|
|
description: PLL1 DIVP division factor
|
|
name: DIVP
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
description: PLL1 DIVQ division factor
|
|
name: DIVQ
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
description: PLL1 DIVR division factor
|
|
name: DIVR
|
|
fieldset/PLL2FRACR:
|
|
description: RCC PLL2 Fractional Divider Register
|
|
fields:
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 3
|
|
bit_size: 13
|
|
description: Fractional part of the multiplication factor for PLL VCO
|
|
name: FRACN
|
|
fieldset/PLL3DIVR:
|
|
description: RCC PLL3 Dividers Configuration Register
|
|
fields:
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 0
|
|
bit_size: 9
|
|
description: Multiplication factor for PLL1 VCO
|
|
name: DIVN
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 9
|
|
bit_size: 7
|
|
description: PLL DIVP division factor
|
|
name: DIVP
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
description: PLL DIVQ division factor
|
|
name: DIVQ
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
description: PLL DIVR division factor
|
|
name: DIVR
|
|
fieldset/PLL3FRACR:
|
|
description: RCC PLL3 Fractional Divider Register
|
|
fields:
|
|
- array:
|
|
len: 1
|
|
stride: 0
|
|
bit_offset: 3
|
|
bit_size: 13
|
|
description: Fractional part of the multiplication factor for PLL3 VCO
|
|
name: FRACN
|
|
fieldset/PLLCFGR:
|
|
description: RCC PLLs Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: PLL1 fractional latch enable
|
|
name: PLL1FRACEN
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: PLL1 VCO selection
|
|
enum: PLLVCOSEL
|
|
name: PLL1VCOSEL
|
|
- bit_offset: 2
|
|
bit_size: 2
|
|
description: PLL1 input frequency range
|
|
enum: PLLRGE
|
|
name: PLL1RGE
|
|
- bit_offset: 4
|
|
bit_size: 1
|
|
description: PLL2 fractional latch enable
|
|
name: PLL2FRACEN
|
|
- bit_offset: 5
|
|
bit_size: 1
|
|
description: PLL2 VCO selection
|
|
enum: PLLVCOSEL
|
|
name: PLL2VCOSEL
|
|
- bit_offset: 6
|
|
bit_size: 2
|
|
description: PLL2 input frequency range
|
|
enum: PLLRGE
|
|
name: PLL2RGE
|
|
- bit_offset: 8
|
|
bit_size: 1
|
|
description: PLL3 fractional latch enable
|
|
name: PLL3FRACEN
|
|
- bit_offset: 9
|
|
bit_size: 1
|
|
description: PLL3 VCO selection
|
|
enum: PLLVCOSEL
|
|
name: PLL3VCOSEL
|
|
- bit_offset: 10
|
|
bit_size: 2
|
|
description: PLL3 input frequency range
|
|
enum: PLLRGE
|
|
name: PLL3RGE
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: PLL1 DIVP divider output enable
|
|
name: DIVP1EN
|
|
- bit_offset: 17
|
|
bit_size: 1
|
|
description: PLL1 DIVQ divider output enable
|
|
name: DIVQ1EN
|
|
- bit_offset: 18
|
|
bit_size: 1
|
|
description: PLL1 DIVR divider output enable
|
|
name: DIVR1EN
|
|
- bit_offset: 19
|
|
bit_size: 1
|
|
description: PLL2 DIVP divider output enable
|
|
name: DIVP2EN
|
|
- bit_offset: 20
|
|
bit_size: 1
|
|
description: PLL2 DIVQ divider output enable
|
|
name: DIVQ2EN
|
|
- bit_offset: 21
|
|
bit_size: 1
|
|
description: PLL2 DIVR divider output enable
|
|
name: DIVR2EN
|
|
- bit_offset: 22
|
|
bit_size: 1
|
|
description: PLL3 DIVP divider output enable
|
|
name: DIVP3EN
|
|
- bit_offset: 23
|
|
bit_size: 1
|
|
description: PLL3 DIVQ divider output enable
|
|
name: DIVQ3EN
|
|
- bit_offset: 24
|
|
bit_size: 1
|
|
description: PLL3 DIVR divider output enable
|
|
name: DIVR3EN
|
|
fieldset/PLLCKSELR:
|
|
description: RCC PLLs Clock Source Selection Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 2
|
|
description: DIVMx and PLLs clock source selection
|
|
enum: PLLSRC
|
|
name: PLLSRC
|
|
- array:
|
|
len: 3
|
|
stride: 8
|
|
bit_offset: 4
|
|
bit_size: 6
|
|
description: Prescaler for PLL1
|
|
name: DIVM
|