264 lines
6.8 KiB
YAML
264 lines
6.8 KiB
YAML
block/ADC_COMMON:
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description: Analog-to-Digital Converter
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items:
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- name: CSR
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description: ADC Common status register
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byte_offset: 0
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access: Read
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fieldset: CSR
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- name: CCR
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description: ADC common control register
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byte_offset: 8
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fieldset: CCR
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- name: CDR
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description: ADC common regular data register for dual and triple modes
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byte_offset: 12
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access: Read
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fieldset: CDR
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- name: CDR2
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description: ADC x common regular data register for 32-bit dual mode
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byte_offset: 16
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access: Read
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fieldset: CDR2
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fieldset/CCR:
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description: ADC common control register
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fields:
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- name: DUAL
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description: Dual ADC mode selection
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bit_offset: 0
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bit_size: 5
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enum: DUAL
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- name: DELAY
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description: Delay between 2 sampling phases
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bit_offset: 8
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bit_size: 4
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- name: DAMDF
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description: Dual ADC Mode Data Format
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bit_offset: 14
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bit_size: 2
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enum: DAMDF
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- name: CKMODE
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description: ADC clock mode
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bit_offset: 16
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bit_size: 2
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enum: CKMODE
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- name: PRESC
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description: ADC prescaler
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bit_offset: 18
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bit_size: 4
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enum: PRESC
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- name: VREFEN
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description: VREFINT enable
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bit_offset: 22
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bit_size: 1
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- name: VSENSEEN
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description: Temperature sensor enable
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bit_offset: 23
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bit_size: 1
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- name: VBATEN
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description: VBAT enable
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bit_offset: 24
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bit_size: 1
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fieldset/CDR:
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description: ADC common regular data register for dual and triple modes
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fields:
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- name: RDATA_MST
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description: Regular data of the master ADC
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bit_offset: 0
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bit_size: 16
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- name: RDATA_SLV
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description: Regular data of the slave ADC
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bit_offset: 16
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bit_size: 16
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fieldset/CDR2:
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description: ADC x common regular data register for 32-bit dual mode
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fields:
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- name: RDATA_ALT
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description: Regular data of the master/slave alternated ADCs
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bit_offset: 0
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bit_size: 32
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fieldset/CSR:
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description: ADC Common status register
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fields:
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- name: ADRDY_MST
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description: Master ADC ready
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bit_offset: 0
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bit_size: 1
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- name: EOSMP_MST
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description: End of Sampling phase flag of the master ADC
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bit_offset: 1
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bit_size: 1
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- name: EOC_MST
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description: End of regular conversion of the master ADC
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bit_offset: 2
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bit_size: 1
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- name: EOS_MST
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description: End of regular sequence flag of the master ADC
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bit_offset: 3
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bit_size: 1
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- name: OVR_MST
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description: Overrun flag of the master ADC
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bit_offset: 4
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bit_size: 1
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- name: JEOC_MST
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description: End of injected conversion flag of the master ADC
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bit_offset: 5
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bit_size: 1
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- name: JEOS_MST
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description: End of injected sequence flag of the master ADC
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bit_offset: 6
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bit_size: 1
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- name: AWD1_MST
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description: Analog watchdog 1 flag of the master ADC
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bit_offset: 7
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bit_size: 1
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- name: AWD2_MST
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description: Analog watchdog 2 flag of the master ADC
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bit_offset: 8
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bit_size: 1
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- name: AWD3_MST
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description: Analog watchdog 3 flag of the master ADC
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bit_offset: 9
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bit_size: 1
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- name: JQOVF_MST
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description: Injected Context Queue Overflow flag of the master ADC
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bit_offset: 10
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bit_size: 1
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- name: ADRDY_SLV
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description: Slave ADC ready
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bit_offset: 16
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bit_size: 1
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- name: EOSMP_SLV
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description: End of Sampling phase flag of the slave ADC
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bit_offset: 17
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bit_size: 1
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- name: EOC_SLV
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description: End of regular conversion of the slave ADC
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bit_offset: 18
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bit_size: 1
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- name: EOS_SLV
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description: End of regular sequence flag of the slave ADC
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bit_offset: 19
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bit_size: 1
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- name: OVR_SLV
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description: Overrun flag of the slave ADC
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bit_offset: 20
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bit_size: 1
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- name: JEOC_SLV
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description: End of injected conversion flag of the slave ADC
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bit_offset: 21
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bit_size: 1
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- name: JEOS_SLV
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description: End of injected sequence flag of the slave ADC
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bit_offset: 22
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bit_size: 1
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- name: AWD1_SLV
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description: Analog watchdog 1 flag of the slave ADC
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bit_offset: 23
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bit_size: 1
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- name: AWD2_SLV
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description: Analog watchdog 2 flag of the slave ADC
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bit_offset: 24
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bit_size: 1
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- name: AWD3_SLV
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description: Analog watchdog 3 flag of the slave ADC
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bit_offset: 25
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bit_size: 1
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- name: JQOVF_SLV
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description: Injected Context Queue Overflow flag of the slave ADC
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bit_offset: 26
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bit_size: 1
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enum/CKMODE:
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bit_size: 2
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variants:
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- name: Asynchronous
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description: Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock
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value: 0
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- name: SyncDiv1
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description: Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck
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value: 1
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- name: SyncDiv2
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description: Use AHB clock rcc_hclk3 divided by 2
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value: 2
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- name: SyncDiv4
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description: Use AHB clock rcc_hclk3 divided by 4
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value: 3
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enum/DAMDF:
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bit_size: 2
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variants:
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- name: NoPack
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description: Without data packing, CDR/CDR2 not used
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value: 0
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- name: Format32to10
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description: CDR formatted for 32-bit down to 10-bit resolution
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value: 2
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- name: Format8
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description: CDR formatted for 8-bit resolution
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value: 3
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enum/DUAL:
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bit_size: 5
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variants:
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- name: Independent
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description: Independent mode
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value: 0
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- name: DualRJ
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description: Dual, combined regular simultaneous + injected simultaneous mode
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value: 1
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- name: DualRA
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description: Dual, combined regular simultaneous + alternate trigger mode
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value: 2
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- name: DualIJ
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description: Dual, combined interleaved mode + injected simultaneous mode
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value: 3
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- name: DualJ
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description: Dual, injected simultaneous mode only
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value: 5
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- name: DualR
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description: Dual, regular simultaneous mode only
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value: 6
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- name: DualI
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description: Dual, interleaved mode only
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value: 7
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- name: DualA
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description: Dual, alternate trigger mode only
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value: 9
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enum/PRESC:
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bit_size: 4
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variants:
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- name: Div1
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description: adc_ker_ck_input not divided
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value: 0
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- name: Div2
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description: adc_ker_ck_input divided by 2
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value: 1
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- name: Div4
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description: adc_ker_ck_input divided by 4
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value: 2
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- name: Div6
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description: adc_ker_ck_input divided by 6
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value: 3
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- name: Div8
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description: adc_ker_ck_input divided by 8
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value: 4
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- name: Div10
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description: adc_ker_ck_input divided by 10
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value: 5
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- name: Div12
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description: adc_ker_ck_input divided by 12
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value: 6
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- name: Div16
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description: adc_ker_ck_input divided by 16
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value: 7
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- name: Div32
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description: adc_ker_ck_input divided by 32
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value: 8
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- name: Div64
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description: adc_ker_ck_input divided by 64
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value: 9
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- name: Div128
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description: adc_ker_ck_input divided by 128
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value: 10
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- name: Div256
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description: adc_ker_ck_input divided by 256
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value: 11
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