775 lines
18 KiB
YAML
775 lines
18 KiB
YAML
---
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block/LAYER:
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description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR,
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L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR
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items:
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- byte_offset: 0
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description: Layerx Control Register
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fieldset: CR
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name: CR
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- byte_offset: 4
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description: Layerx Window Horizontal Position Configuration Register
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fieldset: WHPCR
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name: WHPCR
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- byte_offset: 8
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description: Layerx Window Vertical Position Configuration Register
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fieldset: WVPCR
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name: WVPCR
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- byte_offset: 12
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description: Layerx Color Keying Configuration Register
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fieldset: CKCR
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name: CKCR
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- byte_offset: 16
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description: Layerx Pixel Format Configuration Register
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fieldset: PFCR
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name: PFCR
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- byte_offset: 20
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description: Layerx Constant Alpha Configuration Register
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fieldset: CACR
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name: CACR
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- byte_offset: 24
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description: Layerx Default Color Configuration Register
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fieldset: DCCR
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name: DCCR
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- byte_offset: 28
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description: Layerx Blending Factors Configuration Register
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fieldset: BFCR
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name: BFCR
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- byte_offset: 40
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description: Layerx Color Frame Buffer Address Register
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fieldset: CFBAR
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name: CFBAR
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- byte_offset: 44
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description: Layerx Color Frame Buffer Length Register
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fieldset: CFBLR
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name: CFBLR
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- byte_offset: 48
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description: Layerx ColorFrame Buffer Line Number Register
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fieldset: CFBLNR
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name: CFBLNR
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- access: Write
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byte_offset: 64
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description: Layerx CLUT Write Register
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fieldset: CLUTWR
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name: CLUTWR
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block/LTDC:
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description: LCD-TFT Controller
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items:
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- byte_offset: 8
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description: Synchronization Size Configuration Register
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fieldset: SSCR
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name: SSCR
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- byte_offset: 12
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description: Back Porch Configuration Register
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fieldset: BPCR
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name: BPCR
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- byte_offset: 16
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description: Active Width Configuration Register
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fieldset: AWCR
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name: AWCR
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- byte_offset: 20
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description: Total Width Configuration Register
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fieldset: TWCR
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name: TWCR
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- byte_offset: 24
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description: Global Control Register
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fieldset: GCR
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name: GCR
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- byte_offset: 36
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description: Shadow Reload Configuration Register
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fieldset: SRCR
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name: SRCR
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- byte_offset: 44
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description: Background Color Configuration Register
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fieldset: BCCR
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name: BCCR
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- byte_offset: 52
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description: Interrupt Enable Register
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fieldset: IER
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name: IER
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- access: Read
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byte_offset: 56
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description: Interrupt Status Register
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fieldset: ISR
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name: ISR
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- access: Write
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byte_offset: 60
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description: Interrupt Clear Register
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fieldset: ICR
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name: ICR
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- byte_offset: 64
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description: Line Interrupt Position Configuration Register
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fieldset: LIPCR
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name: LIPCR
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- access: Read
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byte_offset: 68
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description: Current Position Status Register
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fieldset: CPSR
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name: CPSR
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- access: Read
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byte_offset: 72
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description: Current Display Status Register
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fieldset: CDSR
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name: CDSR
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- array:
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len: 2
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stride: 128
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block: LAYER
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byte_offset: 132
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description: Cluster LAYER%s, containing L?CR, L?WHPCR, L?WVPCR, L?CKCR, L?PFCR,
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L?CACR, L?DCCR, L?BFCR, L?CFBAR, L?CFBLR, L?CFBLNR, L?CLUTWR
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name: LAYER
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enum/BF1:
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bit_size: 3
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variants:
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- description: BF1 = constant alpha
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name: Constant
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value: 4
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- description: BF1 = pixel alpha * constant alpha
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name: Pixel
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value: 6
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enum/BF2:
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bit_size: 3
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variants:
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- description: BF2 = 1 - constant alpha
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name: Constant
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value: 5
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- description: BF2 = 1 - pixel alpha * constant alpha
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name: Pixel
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value: 7
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enum/CFUIF:
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bit_size: 1
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variants:
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- description: Clears the FUIF flag in the ISR register
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name: Clear
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value: 1
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enum/CLIF:
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bit_size: 1
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variants:
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- description: Clears the LIF flag in the ISR register
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name: Clear
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value: 1
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enum/CLUTEN:
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bit_size: 1
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variants:
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- description: Color look-up table disabled
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name: Disabled
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value: 0
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- description: Color look-up table enabled
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name: Enabled
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value: 1
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enum/COLKEN:
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bit_size: 1
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variants:
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- description: Color keying disabled
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name: Disabled
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value: 0
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- description: Color keying enabled
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name: Enabled
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value: 1
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enum/CRRIF:
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bit_size: 1
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variants:
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- description: Clears the RRIF flag in the ISR register
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name: Clear
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value: 1
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enum/CTERRIF:
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bit_size: 1
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variants:
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- description: Clears the TERRIF flag in the ISR register
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name: Clear
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value: 1
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enum/DEN:
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bit_size: 1
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variants:
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- description: Dither disabled
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name: Disabled
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value: 0
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- description: Dither enabled
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name: Enabled
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value: 1
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enum/DEPOL:
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bit_size: 1
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variants:
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- description: Data enable polarity is active low
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name: ActiveLow
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value: 0
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- description: Data enable polarity is active high
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name: ActiveHigh
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value: 1
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enum/FUIE:
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bit_size: 1
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variants:
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- description: FIFO underrun interrupt disabled
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name: Disabled
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value: 0
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- description: FIFO underrun interrupt enabled
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name: Enabled
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value: 1
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enum/FUIF:
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bit_size: 1
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variants:
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- description: No FIFO underrun
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name: NoUnderrun
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value: 0
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- description: FIFO underrun interrupt generated, if one of the layer FIFOs is empty
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and pixel data is read from the FIFO
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name: Underrun
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value: 1
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enum/HDES:
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bit_size: 1
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variants:
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- description: Currently not in horizontal Data Enable phase
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name: NotActive
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value: 0
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- description: Currently in horizontal Data Enable phase
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name: Active
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value: 1
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enum/HSPOL:
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bit_size: 1
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variants:
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- description: Horizontal synchronization polarity is active low
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name: ActiveLow
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value: 0
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- description: Horizontal synchronization polarity is active high
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name: ActiveHigh
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value: 1
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enum/HSYNCS:
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bit_size: 1
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variants:
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- description: Currently not in HSYNC phase
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name: NotActive
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value: 0
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- description: Currently in HSYNC phase
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name: Active
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value: 1
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enum/IMR:
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bit_size: 1
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variants:
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- description: This bit is set by software and cleared only by hardware after reload
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(it cannot be cleared through register write once it is set)
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name: NoEffect
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value: 0
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- description: The shadow registers are reloaded immediately. This bit is set by
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software and cleared only by hardware after reload
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name: Reload
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value: 1
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enum/LEN:
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bit_size: 1
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variants:
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- description: Layer disabled
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name: Disabled
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value: 0
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- description: Layer enabled
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name: Enabled
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value: 1
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enum/LIE:
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bit_size: 1
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variants:
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- description: Line interrupt disabled
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name: Disabled
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value: 0
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- description: Line interrupt enabled
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name: Enabled
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value: 1
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enum/LIF:
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bit_size: 1
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variants:
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- description: Programmed line not reached
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name: NotReached
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value: 0
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- description: Line interrupt generated when a programmed line is reached
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name: Reached
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value: 1
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enum/LTDCEN:
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bit_size: 1
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variants:
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- description: LCD-TFT controller disabled
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name: Disabled
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value: 0
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- description: LCD-TFT controller enabled
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name: Enabled
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value: 1
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enum/PCPOL:
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bit_size: 1
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variants:
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- description: Pixel clock on rising edge
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name: RisingEdge
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value: 0
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- description: Pixel clock on falling edge
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name: FallingEdge
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value: 1
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enum/PF:
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bit_size: 3
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variants:
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- description: ARGB8888
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name: ARGB8888
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value: 0
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- description: RGB888
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name: RGB888
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value: 1
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- description: RGB565
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name: RGB565
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value: 2
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- description: ARGB1555
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name: ARGB1555
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value: 3
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- description: ARGB4444
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name: ARGB4444
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value: 4
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- description: L8 (8-bit luminance)
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name: L8
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value: 5
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- description: AL44 (4-bit alpha, 4-bit luminance)
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name: AL44
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value: 6
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- description: AL88 (8-bit alpha, 8-bit luminance)
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name: AL88
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value: 7
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enum/RRIE:
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bit_size: 1
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variants:
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- description: Register reload interrupt disabled
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name: Disabled
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value: 0
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- description: Register reload interrupt enabled
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name: Enabled
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value: 1
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enum/RRIF:
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bit_size: 1
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variants:
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- description: No register reload
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name: NoReload
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value: 0
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- description: Register reload interrupt generated when a vertical blanking reload
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occurs (and the first line after the active area is reached)
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name: Reload
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value: 1
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enum/TERRIE:
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bit_size: 1
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variants:
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- description: Transfer error interrupt disabled
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name: Disabled
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value: 0
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- description: Transfer error interrupt enabled
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name: Enabled
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value: 1
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enum/TERRIF:
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bit_size: 1
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variants:
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- description: No transfer error
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name: NoError
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value: 0
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- description: Transfer error interrupt generated when a bus error occurs
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name: Error
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value: 1
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enum/VBR:
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bit_size: 1
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variants:
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- description: This bit is set by software and cleared only by hardware after reload
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(it cannot be cleared through register write once it is set)
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name: NoEffect
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value: 0
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- description: The shadow registers are reloaded during the vertical blanking period
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(at the beginning of the first line after the active display area).
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name: Reload
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value: 1
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enum/VDES:
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bit_size: 1
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variants:
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- description: Currently not in vertical Data Enable phase
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name: NotActive
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value: 0
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- description: Currently in vertical Data Enable phase
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name: Active
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value: 1
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enum/VSPOL:
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bit_size: 1
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variants:
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- description: Vertical synchronization polarity is active low
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name: ActiveLow
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value: 0
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- description: Vertical synchronization polarity is active high
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name: ActiveHigh
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value: 1
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enum/VSYNCS:
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bit_size: 1
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variants:
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- description: Currently not in VSYNC phase
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name: NotActive
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value: 0
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- description: Currently in VSYNC phase
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name: Active
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value: 1
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fieldset/AWCR:
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description: Active Width Configuration Register
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fields:
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- bit_offset: 0
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bit_size: 11
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description: Accumulated Active Height (in units of horizontal scan line)
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name: AAH
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- bit_offset: 16
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bit_size: 12
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description: Accumulated Active Width (in units of pixel clock period)
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name: AAW
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fieldset/BCCR:
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description: Background Color Configuration Register
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fields:
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- bit_offset: 0
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bit_size: 8
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description: Background color blue value
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name: BCBLUE
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- bit_offset: 8
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bit_size: 8
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description: Background color green value
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name: BCGREEN
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- bit_offset: 16
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bit_size: 8
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description: Background color red value
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name: BCRED
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fieldset/BFCR:
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description: Layerx Blending Factors Configuration Register
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fields:
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- array:
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len: 2
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stride: 8
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bit_offset: 0
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bit_size: 3
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description: Blending Factor 2
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enum: BF2
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name: BF
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fieldset/BPCR:
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description: Back Porch Configuration Register
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fields:
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- bit_offset: 0
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bit_size: 11
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description: Accumulated Vertical back porch (in units of horizontal scan line)
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name: AVBP
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- bit_offset: 16
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bit_size: 12
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description: Accumulated Horizontal back porch (in units of pixel clock period)
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name: AHBP
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fieldset/CACR:
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description: Layerx Constant Alpha Configuration Register
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fields:
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- bit_offset: 0
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bit_size: 8
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description: Constant Alpha
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name: CONSTA
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fieldset/CDSR:
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description: Current Display Status Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: Vertical Data Enable display Status
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enum: VDES
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name: VDES
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- bit_offset: 1
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bit_size: 1
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description: Horizontal Data Enable display Status
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enum: HDES
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name: HDES
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- bit_offset: 2
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bit_size: 1
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description: Vertical Synchronization display Status
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enum: VSYNCS
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name: VSYNCS
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- bit_offset: 3
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bit_size: 1
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description: Horizontal Synchronization display Status
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enum: HSYNCS
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name: HSYNCS
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fieldset/CFBAR:
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description: Layerx Color Frame Buffer Address Register
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fields:
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- bit_offset: 0
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bit_size: 32
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description: Color Frame Buffer Start Address
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name: CFBADD
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fieldset/CFBLNR:
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description: Layerx ColorFrame Buffer Line Number Register
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fields:
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- bit_offset: 0
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bit_size: 11
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description: Frame Buffer Line Number
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name: CFBLNBR
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fieldset/CFBLR:
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description: Layerx Color Frame Buffer Length Register
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fields:
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- bit_offset: 0
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bit_size: 13
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description: Color Frame Buffer Line Length
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name: CFBLL
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- bit_offset: 16
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bit_size: 13
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description: Color Frame Buffer Pitch in bytes
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name: CFBP
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fieldset/CKCR:
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description: Layerx Color Keying Configuration Register
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fields:
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- bit_offset: 0
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bit_size: 8
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description: Color Key Blue value
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name: CKBLUE
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- bit_offset: 8
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bit_size: 8
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description: Color Key Green value
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name: CKGREEN
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- bit_offset: 16
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bit_size: 8
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description: Color Key Red value
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name: CKRED
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fieldset/CLUTWR:
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description: Layerx CLUT Write Register
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fields:
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- bit_offset: 0
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bit_size: 8
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description: Blue value
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name: BLUE
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- bit_offset: 8
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bit_size: 8
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description: Green value
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name: GREEN
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- bit_offset: 16
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bit_size: 8
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description: Red value
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name: RED
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- bit_offset: 24
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bit_size: 8
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description: CLUT Address
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name: CLUTADD
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fieldset/CPSR:
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description: Current Position Status Register
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fields:
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- bit_offset: 0
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bit_size: 16
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description: Current Y Position
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name: CYPOS
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- bit_offset: 16
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bit_size: 16
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description: Current X Position
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name: CXPOS
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fieldset/CR:
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description: Layerx Control Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: Layer Enable
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enum: LEN
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name: LEN
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- bit_offset: 1
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bit_size: 1
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description: Color Keying Enable
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enum: COLKEN
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name: COLKEN
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- bit_offset: 4
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bit_size: 1
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description: Color Look-Up Table Enable
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enum: CLUTEN
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name: CLUTEN
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fieldset/DCCR:
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description: Layerx Default Color Configuration Register
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fields:
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- bit_offset: 0
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bit_size: 8
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description: Default Color Blue
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name: DCBLUE
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- bit_offset: 8
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bit_size: 8
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description: Default Color Green
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name: DCGREEN
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- bit_offset: 16
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bit_size: 8
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description: Default Color Red
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name: DCRED
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- bit_offset: 24
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bit_size: 8
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description: Default Color Alpha
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name: DCALPHA
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fieldset/GCR:
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description: Global Control Register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: LCD-TFT controller enable bit
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enum: LTDCEN
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name: LTDCEN
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- bit_offset: 4
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bit_size: 3
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description: Dither Blue Width
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name: DBW
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- bit_offset: 8
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bit_size: 3
|
|
description: Dither Green Width
|
|
name: DGW
|
|
- bit_offset: 12
|
|
bit_size: 3
|
|
description: Dither Red Width
|
|
name: DRW
|
|
- bit_offset: 16
|
|
bit_size: 1
|
|
description: Dither Enable
|
|
enum: DEN
|
|
name: DEN
|
|
- bit_offset: 28
|
|
bit_size: 1
|
|
description: Pixel Clock Polarity
|
|
enum: PCPOL
|
|
name: PCPOL
|
|
- bit_offset: 29
|
|
bit_size: 1
|
|
description: Data Enable Polarity
|
|
enum: DEPOL
|
|
name: DEPOL
|
|
- bit_offset: 30
|
|
bit_size: 1
|
|
description: Vertical Synchronization Polarity
|
|
enum: VSPOL
|
|
name: VSPOL
|
|
- bit_offset: 31
|
|
bit_size: 1
|
|
description: Horizontal Synchronization Polarity
|
|
enum: HSPOL
|
|
name: HSPOL
|
|
fieldset/ICR:
|
|
description: Interrupt Clear Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Clears the Line Interrupt Flag
|
|
enum: CLIF
|
|
name: CLIF
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Clears the FIFO Underrun Interrupt flag
|
|
enum: CFUIF
|
|
name: CFUIF
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: Clears the Transfer Error Interrupt Flag
|
|
enum: CTERRIF
|
|
name: CTERRIF
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: Clears Register Reload Interrupt Flag
|
|
enum: CRRIF
|
|
name: CRRIF
|
|
fieldset/IER:
|
|
description: Interrupt Enable Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Line Interrupt Enable
|
|
enum: LIE
|
|
name: LIE
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: FIFO Underrun Interrupt Enable
|
|
enum: FUIE
|
|
name: FUIE
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: Transfer Error Interrupt Enable
|
|
enum: TERRIE
|
|
name: TERRIE
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: Register Reload interrupt enable
|
|
enum: RRIE
|
|
name: RRIE
|
|
fieldset/ISR:
|
|
description: Interrupt Status Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Line Interrupt flag
|
|
enum: LIF
|
|
name: LIF
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: FIFO Underrun Interrupt flag
|
|
enum: FUIF
|
|
name: FUIF
|
|
- bit_offset: 2
|
|
bit_size: 1
|
|
description: Transfer Error interrupt flag
|
|
enum: TERRIF
|
|
name: TERRIF
|
|
- bit_offset: 3
|
|
bit_size: 1
|
|
description: Register Reload Interrupt Flag
|
|
enum: RRIF
|
|
name: RRIF
|
|
fieldset/LIPCR:
|
|
description: Line Interrupt Position Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 11
|
|
description: Line Interrupt Position
|
|
name: LIPOS
|
|
fieldset/PFCR:
|
|
description: Layerx Pixel Format Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 3
|
|
description: Pixel Format
|
|
enum: PF
|
|
name: PF
|
|
fieldset/SRCR:
|
|
description: Shadow Reload Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 1
|
|
description: Immediate Reload
|
|
enum: IMR
|
|
name: IMR
|
|
- bit_offset: 1
|
|
bit_size: 1
|
|
description: Vertical Blanking Reload
|
|
enum: VBR
|
|
name: VBR
|
|
fieldset/SSCR:
|
|
description: Synchronization Size Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 11
|
|
description: Vertical Synchronization Height (in units of horizontal scan line)
|
|
name: VSH
|
|
- bit_offset: 16
|
|
bit_size: 12
|
|
description: Horizontal Synchronization Width (in units of pixel clock period)
|
|
name: HSW
|
|
fieldset/TWCR:
|
|
description: Total Width Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 11
|
|
description: Total Height (in units of horizontal scan line)
|
|
name: TOTALH
|
|
- bit_offset: 16
|
|
bit_size: 12
|
|
description: Total Width (in units of pixel clock period)
|
|
name: TOTALW
|
|
fieldset/WHPCR:
|
|
description: Layerx Window Horizontal Position Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 12
|
|
description: Window Horizontal Start Position
|
|
name: WHSTPOS
|
|
- bit_offset: 16
|
|
bit_size: 12
|
|
description: Window Horizontal Stop Position
|
|
name: WHSPPOS
|
|
fieldset/WVPCR:
|
|
description: Layerx Window Vertical Position Configuration Register
|
|
fields:
|
|
- bit_offset: 0
|
|
bit_size: 11
|
|
description: Window Vertical Start Position
|
|
name: WVSTPOS
|
|
- bit_offset: 16
|
|
bit_size: 11
|
|
description: Window Vertical Stop Position
|
|
name: WVSPPOS
|