949 lines
22 KiB
YAML
949 lines
22 KiB
YAML
block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: CFGR
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description: Clock configuration register (RCC_CFGR)
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byte_offset: 4
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fieldset: CFGR
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- name: CIR
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description: Clock interrupt register (RCC_CIR)
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byte_offset: 8
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fieldset: CIR
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- name: APB2RSTR
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description: APB2 peripheral reset register (RCC_APB2RSTR)
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byte_offset: 12
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fieldset: APB2RSTR
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- name: APB1RSTR
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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byte_offset: 16
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fieldset: APB1RSTR
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- name: AHBENR
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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byte_offset: 20
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fieldset: AHBENR
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- name: APB2ENR
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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byte_offset: 24
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fieldset: APB2ENR
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- name: APB1ENR
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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byte_offset: 28
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fieldset: APB1ENR
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- name: BDCR
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description: Backup domain control register (RCC_BDCR)
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byte_offset: 32
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fieldset: BDCR
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- name: CSR
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description: Control/status register (RCC_CSR)
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byte_offset: 36
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fieldset: CSR
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- name: AHBRSTR
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description: AHB peripheral clock reset register (RCC_AHBRSTR)
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byte_offset: 40
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fieldset: AHBRSTR
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- name: CFGR2
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description: Clock configuration register 2
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byte_offset: 44
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fieldset: CFGR2
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fieldset/AHBENR:
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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fields:
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: SRAMEN
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description: SRAM interface clock enable
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bit_offset: 2
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bit_size: 1
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- name: FLASHEN
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description: FLASH clock enable
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bit_offset: 4
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 6
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bit_size: 1
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- name: USB_OTG_FSEN
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description: USB OTG FS clock enable
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bit_offset: 12
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bit_size: 1
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- name: ETHEN
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description: Ethernet MAC clock enable
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bit_offset: 14
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bit_size: 1
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- name: ETHTXEN
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description: Ethernet MAC TX clock enable
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bit_offset: 15
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bit_size: 1
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- name: ETHRXEN
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description: Ethernet MAC RX clock enable
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bit_offset: 16
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bit_size: 1
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fieldset/AHBRSTR:
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description: AHB peripheral clock reset register (RCC_AHBRSTR)
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fields:
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- name: USB_OTG_FSRST
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description: USB OTG FS reset
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bit_offset: 12
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bit_size: 1
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- name: ETHRST
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description: Ethernet MAC reset
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bit_offset: 14
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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fields:
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- name: TIM2EN
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description: Timer 2 clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: Timer 3 clock enable
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bit_offset: 1
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bit_size: 1
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- name: TIM4EN
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description: Timer 4 clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM5EN
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description: Timer 5 clock enable
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bit_offset: 3
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bit_size: 1
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- name: TIM6EN
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description: Timer 6 clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: Timer 7 clock enable
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bit_offset: 5
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI 2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: SPI3EN
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description: SPI 3 clock enable
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bit_offset: 15
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bit_size: 1
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- name: USART2EN
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description: USART 2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: USART3EN
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description: USART 3 clock enable
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bit_offset: 18
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bit_size: 1
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- name: UART4EN
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description: UART 4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: UART5EN
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description: UART 5 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C 1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C 2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: CAN1EN
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description: CAN1 clock enable
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bit_offset: 25
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bit_size: 1
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- name: CAN2EN
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description: CAN2 clock enable
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bit_offset: 26
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bit_size: 1
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- name: BKPEN
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description: Backup interface clock enable
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bit_offset: 27
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: DACEN
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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fieldset/APB1RSTR:
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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fields:
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- name: TIM2RST
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description: Timer 2 reset
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bit_offset: 0
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bit_size: 1
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- name: TIM3RST
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description: Timer 3 reset
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bit_offset: 1
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bit_size: 1
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- name: TIM4RST
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description: Timer 4 reset
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bit_offset: 2
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bit_size: 1
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- name: TIM5RST
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description: Timer 5 reset
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bit_offset: 3
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bit_size: 1
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- name: TIM6RST
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description: Timer 6 reset
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bit_offset: 4
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bit_size: 1
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- name: TIM7RST
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description: Timer 7 reset
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bit_offset: 5
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bit_size: 1
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- name: WWDGRST
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description: Window watchdog reset
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bit_offset: 11
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bit_size: 1
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- name: SPI2RST
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description: SPI2 reset
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bit_offset: 14
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bit_size: 1
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- name: SPI3RST
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description: SPI3 reset
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bit_offset: 15
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bit_size: 1
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- name: USART2RST
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description: USART 2 reset
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bit_offset: 17
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bit_size: 1
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- name: USART3RST
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description: USART 3 reset
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bit_offset: 18
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bit_size: 1
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- name: UART4RST
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description: USART 4 reset
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bit_offset: 19
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bit_size: 1
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- name: UART5RST
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description: USART 5 reset
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bit_offset: 20
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bit_size: 1
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- name: I2C1RST
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description: I2C1 reset
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bit_offset: 21
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bit_size: 1
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- name: I2C2RST
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description: I2C2 reset
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bit_offset: 22
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bit_size: 1
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- name: CAN1RST
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description: CAN1 reset
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bit_offset: 25
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bit_size: 1
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- name: CAN2RST
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description: CAN2 reset
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bit_offset: 26
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bit_size: 1
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- name: BKPRST
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description: Backup interface reset
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bit_offset: 27
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bit_size: 1
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- name: PWRRST
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description: Power interface reset
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bit_offset: 28
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bit_size: 1
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- name: DACRST
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description: DAC interface reset
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bit_offset: 29
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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fields:
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- name: AFIOEN
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description: Alternate function I/O clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOAEN
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description: I/O port A clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIOBEN
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description: I/O port B clock enable
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bit_offset: 3
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bit_size: 1
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- name: GPIOCEN
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description: I/O port C clock enable
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bit_offset: 4
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bit_size: 1
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- name: GPIODEN
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description: I/O port D clock enable
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bit_offset: 5
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bit_size: 1
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- name: GPIOEEN
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description: I/O port E clock enable
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bit_offset: 6
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bit_size: 1
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- name: ADC1EN
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description: ADC 1 interface clock enable
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bit_offset: 9
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bit_size: 1
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- name: ADC2EN
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description: ADC 2 interface clock enable
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bit_offset: 10
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bit_size: 1
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- name: TIM1EN
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description: TIM1 Timer clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI1EN
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description: SPI 1 clock enable
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bit_offset: 12
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bit_size: 1
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- name: USART1EN
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description: USART1 clock enable
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bit_offset: 14
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bit_size: 1
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fieldset/APB2RSTR:
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description: APB2 peripheral reset register (RCC_APB2RSTR)
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fields:
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- name: AFIORST
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description: Alternate function I/O reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 2
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 3
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 4
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bit_size: 1
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- name: GPIODRST
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description: IO port D reset
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bit_offset: 5
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bit_size: 1
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- name: GPIOERST
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description: IO port E reset
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bit_offset: 6
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bit_size: 1
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- name: ADC1RST
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description: ADC 1 interface reset
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bit_offset: 9
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bit_size: 1
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- name: ADC2RST
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description: ADC 2 interface reset
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bit_offset: 10
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bit_size: 1
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- name: TIM1RST
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description: TIM1 timer reset
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bit_offset: 11
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bit_size: 1
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- name: SPI1RST
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description: SPI 1 reset
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bit_offset: 12
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bit_size: 1
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- name: USART1RST
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description: USART1 reset
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bit_offset: 14
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bit_size: 1
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fieldset/BDCR:
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description: Backup domain control register (RCC_BDCR)
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fields:
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- name: LSEON
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description: External Low Speed oscillator enable
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bit_offset: 0
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bit_size: 1
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- name: LSERDY
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description: External Low Speed oscillator ready
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bit_offset: 1
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bit_size: 1
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- name: LSEBYP
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description: External Low Speed oscillator bypass
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bit_offset: 2
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bit_size: 1
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- name: RTCSEL
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description: RTC clock source selection
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bit_offset: 8
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bit_size: 2
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enum: RTCSEL
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- name: RTCEN
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description: RTC clock enable
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bit_offset: 15
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bit_size: 1
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- name: BDRST
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description: Backup domain software reset
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bit_offset: 16
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bit_size: 1
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fieldset/CFGR:
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description: Clock configuration register (RCC_CFGR)
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fields:
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- name: SW
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description: System clock Switch
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bit_offset: 0
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bit_size: 2
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enum: SW
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- name: SWS
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description: System Clock Switch Status
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bit_offset: 2
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bit_size: 2
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enum: SW
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- name: HPRE
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description: AHB prescaler
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bit_offset: 4
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bit_size: 4
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enum: HPRE
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- name: PPRE1
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description: APB Low speed prescaler (APB1)
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bit_offset: 8
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bit_size: 3
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enum: PPRE
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- name: PPRE2
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description: APB High speed prescaler (APB2)
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bit_offset: 11
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bit_size: 3
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enum: PPRE
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- name: ADCPRE
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description: ADC prescaler
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bit_offset: 14
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bit_size: 2
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enum: ADCPRE
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- name: PLLSRC
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description: PLL entry clock source
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bit_offset: 16
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bit_size: 1
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enum: PLLSRC
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- name: PLLXTPRE
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description: HSE divider for PLL entry
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bit_offset: 17
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bit_size: 1
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enum: PLLXTPRE
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- name: PLLMUL
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description: PLL Multiplication Factor
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bit_offset: 18
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bit_size: 4
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enum: PLLMUL
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- name: USBPRE
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description: USB prescaler
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bit_offset: 22
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bit_size: 1
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enum: USBPRE
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- name: MCO
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description: Microcontroller clock output
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bit_offset: 24
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bit_size: 4
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enum: MCO
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fieldset/CFGR2:
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description: Clock configuration register2 (RCC_CFGR2)
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fields:
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- name: PREDIV1
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description: PREDIV1 division factor
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bit_offset: 0
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bit_size: 4
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enum: PREDIV1
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- name: PREDIV2
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description: PREDIV2 division factor
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bit_offset: 4
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bit_size: 4
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enum: PREDIV1
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- name: PLL2MUL
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description: PLL2 Multiplication Factor
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bit_offset: 8
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bit_size: 4
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enum: PLL2MUL
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- name: PLL3MUL
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description: PLL3 Multiplication Factor
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bit_offset: 12
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bit_size: 4
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enum: PLL2MUL
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- name: PREDIV1SRC
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description: PREDIV1 entry clock source
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bit_offset: 16
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bit_size: 1
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enum: PREDIV1SRC
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- name: I2S2SRC
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description: I2S2 clock source
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bit_offset: 17
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bit_size: 1
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enum: I2S2SRC
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- name: I2S3SRC
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description: I2S3 clock source
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bit_offset: 18
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bit_size: 1
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enum: I2S2SRC
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fieldset/CIR:
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description: Clock interrupt register (RCC_CIR)
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fields:
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- name: LSIRDYF
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description: LSI Ready Interrupt flag
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bit_offset: 0
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bit_size: 1
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- name: LSERDYF
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description: LSE Ready Interrupt flag
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bit_offset: 1
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bit_size: 1
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- name: HSIRDYF
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description: HSI Ready Interrupt flag
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bit_offset: 2
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bit_size: 1
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- name: HSERDYF
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description: HSE Ready Interrupt flag
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bit_offset: 3
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bit_size: 1
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- name: PLLRDYF
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description: PLL Ready Interrupt flag
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bit_offset: 4
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bit_size: 1
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- name: PLL2RDYF
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description: PLL2 Ready Interrupt flag
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bit_offset: 5
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bit_size: 1
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- name: PLL3RDYF
|
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description: PLL3 Ready Interrupt flag
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bit_offset: 6
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bit_size: 1
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|
- name: CSSF
|
|
description: Clock Security System Interrupt flag
|
|
bit_offset: 7
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bit_size: 1
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|
- name: LSIRDYIE
|
|
description: LSI Ready Interrupt Enable
|
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bit_offset: 8
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|
bit_size: 1
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- name: LSERDYIE
|
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description: LSE Ready Interrupt Enable
|
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bit_offset: 9
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bit_size: 1
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|
- name: HSIRDYIE
|
|
description: HSI Ready Interrupt Enable
|
|
bit_offset: 10
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|
bit_size: 1
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|
- name: HSERDYIE
|
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description: HSE Ready Interrupt Enable
|
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bit_offset: 11
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bit_size: 1
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- name: PLLRDYIE
|
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description: PLL Ready Interrupt Enable
|
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bit_offset: 12
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bit_size: 1
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- name: PLL2RDYIE
|
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description: PLL2 Ready Interrupt Enable
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bit_offset: 13
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bit_size: 1
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- name: PLL3RDYIE
|
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description: PLL3 Ready Interrupt Enable
|
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bit_offset: 14
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bit_size: 1
|
|
- name: LSIRDYC
|
|
description: LSI Ready Interrupt Clear
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE Ready Interrupt Clear
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI Ready Interrupt Clear
|
|
bit_offset: 18
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bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE Ready Interrupt Clear
|
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bit_offset: 19
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bit_size: 1
|
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- name: PLLRDYC
|
|
description: PLL Ready Interrupt Clear
|
|
bit_offset: 20
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bit_size: 1
|
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- name: PLL2RDYC
|
|
description: PLL2 Ready Interrupt Clear
|
|
bit_offset: 21
|
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bit_size: 1
|
|
- name: PLL3RDYC
|
|
description: PLL3 Ready Interrupt Clear
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: Clock security system interrupt clear
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: Internal High Speed clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: Internal High Speed clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSITRIM
|
|
description: Internal High Speed clock trimming
|
|
bit_offset: 3
|
|
bit_size: 5
|
|
- name: HSICAL
|
|
description: Internal High Speed clock Calibration
|
|
bit_offset: 8
|
|
bit_size: 8
|
|
- name: HSEON
|
|
description: External High Speed clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: External High Speed clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: External High Speed clock Bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: Clock Security System enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PLL2ON
|
|
description: PLL2 enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PLL2RDY
|
|
description: PLL2 clock ready flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: PLL3ON
|
|
description: PLL3 enable
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: PLL3RDY
|
|
description: PLL3 clock ready flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
fieldset/CSR:
|
|
description: Control/status register (RCC_CSR)
|
|
fields:
|
|
- name: LSION
|
|
description: Internal low speed oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: Internal low speed oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: PIN reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: PORRSTF
|
|
description: POR/PDR reset flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
enum/ADCPRE:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Div2
|
|
description: PCLK2 divided by 2
|
|
value: 0
|
|
- name: Div4
|
|
description: PCLK2 divided by 4
|
|
value: 1
|
|
- name: Div6
|
|
description: PCLK2 divided by 6
|
|
value: 2
|
|
- name: Div8
|
|
description: PCLK2 divided by 8
|
|
value: 3
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: SYSCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: SYSCLK divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: SYSCLK divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: SYSCLK divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: SYSCLK divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: SYSCLK divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: SYSCLK divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: SYSCLK divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: SYSCLK divided by 512
|
|
value: 15
|
|
enum/I2S2SRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: SYSCLK
|
|
description: System clock (SYSCLK) selected as I2S clock entry
|
|
value: 0
|
|
- name: PLL3
|
|
description: PLL3 VCO clock selected as I2S clock entry
|
|
value: 1
|
|
enum/MCO:
|
|
bit_size: 4
|
|
variants:
|
|
- name: NoMCO
|
|
description: MCO output disabled, no clock on MCO
|
|
value: 0
|
|
- name: SYSCLK
|
|
description: System clock selected
|
|
value: 4
|
|
- name: HSI
|
|
description: HSI oscillator clock selected
|
|
value: 5
|
|
- name: HSE
|
|
description: HSE oscillator clock selected
|
|
value: 6
|
|
- name: PLL
|
|
description: PLL clock divided by 2 selected
|
|
value: 7
|
|
- name: PLL2
|
|
description: PLL2 clock selected
|
|
value: 8
|
|
- name: PLL3DIV2
|
|
description: PLL3 clock divided by 2 selected
|
|
value: 9
|
|
- name: XT1
|
|
description: XT1 external oscillator selected
|
|
value: 10
|
|
- name: PLL3
|
|
description: PLL3 clock selected
|
|
value: 11
|
|
enum/PLL2MUL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Mul8
|
|
description: PLL clock entry x8
|
|
value: 6
|
|
- name: Mul9
|
|
description: PLL clock entry x9
|
|
value: 7
|
|
- name: Mul10
|
|
description: PLL clock entry x10
|
|
value: 8
|
|
- name: Mul11
|
|
description: PLL clock entry x11
|
|
value: 9
|
|
- name: Mul12
|
|
description: PLL clock entry x12
|
|
value: 10
|
|
- name: Mul13
|
|
description: PLL clock entry x13
|
|
value: 11
|
|
- name: Mul14
|
|
description: PLL clock entry x14
|
|
value: 12
|
|
- name: Mul16
|
|
description: PLL clock entry x16
|
|
value: 14
|
|
- name: Mul20
|
|
description: PLL clock entry x20
|
|
value: 15
|
|
enum/PLLMUL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Mul4
|
|
description: PLL input clock x4
|
|
value: 2
|
|
- name: Mul5
|
|
description: PLL input clock x5
|
|
value: 3
|
|
- name: Mul6
|
|
description: PLL input clock x6
|
|
value: 4
|
|
- name: Mul7
|
|
description: PLL input clock x7
|
|
value: 5
|
|
- name: Mul8
|
|
description: PLL input clock x8
|
|
value: 6
|
|
- name: Mul9
|
|
description: PLL input clock x9
|
|
value: 7
|
|
- name: Mul6_5
|
|
description: PLL input clock x6.5
|
|
value: 13
|
|
enum/PLLSRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSI_Div2
|
|
description: HSI divided by 2 selected as PLL input clock
|
|
value: 0
|
|
- name: HSE_Div_PREDIV
|
|
description: HSE divided by PREDIV selected as PLL input clock
|
|
value: 1
|
|
enum/PLLXTPRE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Div1
|
|
description: HSE clock not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HSE clock divided by 2
|
|
value: 1
|
|
enum/PPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK divided by 16
|
|
value: 7
|
|
enum/PREDIV1:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: PREDIV input clock not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: PREDIV input clock divided by 2
|
|
value: 1
|
|
- name: Div3
|
|
description: PREDIV input clock divided by 3
|
|
value: 2
|
|
- name: Div4
|
|
description: PREDIV input clock divided by 4
|
|
value: 3
|
|
- name: Div5
|
|
description: PREDIV input clock divided by 5
|
|
value: 4
|
|
- name: Div6
|
|
description: PREDIV input clock divided by 6
|
|
value: 5
|
|
- name: Div7
|
|
description: PREDIV input clock divided by 7
|
|
value: 6
|
|
- name: Div8
|
|
description: PREDIV input clock divided by 8
|
|
value: 7
|
|
- name: Div9
|
|
description: PREDIV input clock divided by 9
|
|
value: 8
|
|
- name: Div10
|
|
description: PREDIV input clock divided by 10
|
|
value: 9
|
|
- name: Div11
|
|
description: PREDIV input clock divided by 11
|
|
value: 10
|
|
- name: Div12
|
|
description: PREDIV input clock divided by 12
|
|
value: 11
|
|
- name: Div13
|
|
description: PREDIV input clock divided by 13
|
|
value: 12
|
|
- name: Div14
|
|
description: PREDIV input clock divided by 14
|
|
value: 13
|
|
- name: Div15
|
|
description: PREDIV input clock divided by 15
|
|
value: 14
|
|
- name: Div16
|
|
description: PREDIV input clock divided by 16
|
|
value: 15
|
|
enum/PREDIV1SRC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: HSE
|
|
description: HSE oscillator clock selected as PREDIV1 clock entry
|
|
value: 0
|
|
- name: PLL2
|
|
description: PLL2 selected as PREDIV1 clock entry
|
|
value: 1
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE oscillator clock used as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI oscillator clock used as RTC clock
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE oscillator clock divided by a prescaler used as RTC clock
|
|
value: 3
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI
|
|
description: HSI oscillator used as system clock
|
|
value: 0
|
|
- name: HSE
|
|
description: HSE oscillator used as system clock
|
|
value: 1
|
|
- name: PLL
|
|
description: PLL used as system clock
|
|
value: 2
|
|
enum/USBPRE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Div1_5
|
|
description: PLL clock is divided by 1.5
|
|
value: 0
|
|
- name: Div1
|
|
description: PLL clock is not divided
|
|
value: 1
|