893 lines
23 KiB
YAML
893 lines
23 KiB
YAML
---
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block/PWR:
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description: Power control
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items:
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- name: CR1
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description: Power control register 1
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byte_offset: 0
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fieldset: CR1
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- name: CR2
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description: Power control register 2
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byte_offset: 4
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fieldset: CR2
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- name: CR3
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description: Power control register 3
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byte_offset: 8
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fieldset: CR3
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- name: CR4
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description: Power control register 4
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byte_offset: 12
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fieldset: CR4
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- name: SR1
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description: Power status register 1
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byte_offset: 16
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access: Read
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fieldset: SR1
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- name: SR2
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description: Power status register 2
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byte_offset: 20
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access: Read
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fieldset: SR2
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- name: SCR
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description: Power status clear register
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byte_offset: 24
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access: Write
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fieldset: SCR
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- name: CR5
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description: Power control register 5
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byte_offset: 28
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fieldset: CR5
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- name: PUCR
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description: Power Port pull-up control register
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array:
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len: 8
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stride: 8
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byte_offset: 32
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fieldset: PCR
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- name: PDCR
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description: Power Port pull-down control register
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array:
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len: 8
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stride: 8
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byte_offset: 36
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fieldset: PCR
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- name: C2CR1
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description: "Power CPU2 control register 1 [dual core device only]"
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byte_offset: 128
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fieldset: C2CR1
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- name: C2CR3
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description: "Power CPU2 control register 3 [dual core device only]"
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byte_offset: 132
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fieldset: C2CR3
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- name: EXTSCR
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description: Power extended status and status clear register
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byte_offset: 136
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fieldset: EXTSCR
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- name: SECCFGR
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description: "Power security configuration register [dual core device only]"
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byte_offset: 140
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fieldset: SECCFGR
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- name: SUBGHZSPICR
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description: Power SPI3 control register
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byte_offset: 144
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fieldset: SUBGHZSPICR
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- name: RSSCMDR
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description: "RSS Command register [dual core device only]"
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byte_offset: 152
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fieldset: RSSCMDR
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fieldset/C2CR1:
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description: "Power CPU2 control register 1 [dual core device only]"
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fields:
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- name: LPMS
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description: Low-power mode selection for CPU2
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bit_offset: 0
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bit_size: 3
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- name: FPDR
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description: Flash memory power down mode during LPRun for CPU2
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bit_offset: 4
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bit_size: 1
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- name: FPDS
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description: Flash memory power down mode during LPSleep for CPU2
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bit_offset: 5
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bit_size: 1
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fieldset/C2CR3:
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description: "Power CPU2 control register 3 [dual core device only]"
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fields:
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- name: EWUP
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description: Enable Wakeup pin WKUP1 for CPU2
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bit_offset: 0
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bit_size: 1
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array:
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len: 3
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stride: 1
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- name: EWPVD
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description: Enable wakeup PVD for CPU2
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bit_offset: 8
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bit_size: 1
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- name: APC
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description: Apply pull-up and pull-down configuration for CPU2
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bit_offset: 10
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bit_size: 1
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- name: EWRFBUSY
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description: EWRFBUSY
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bit_offset: 11
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bit_size: 1
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- name: EWRFIRQ
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description: akeup for CPU2
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bit_offset: 13
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bit_size: 1
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- name: EIWUL
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description: Enable internal wakeup line for CPU2
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bit_offset: 15
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bit_size: 1
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fieldset/CR1:
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description: Power control register 1
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fields:
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- name: LPMS
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description: Low-power mode selection for CPU1
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bit_offset: 0
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bit_size: 3
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enum: LPMS
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- name: SUBGHZSPINSSSEL
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description: sub-GHz SPI NSS source select
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bit_offset: 3
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bit_size: 1
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enum: SUBGHZSPINSSSEL
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- name: FPDR
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description: Flash memory power down mode during LPRun for CPU1
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bit_offset: 4
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bit_size: 1
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enum: FPDR
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- name: FPDS
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description: Flash memory power down mode during LPSleep for CPU1
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bit_offset: 5
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bit_size: 1
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enum: FPDS
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- name: DBP
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description: Disable backup domain write protection
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bit_offset: 8
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bit_size: 1
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enum: DBP
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- name: VOS
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description: Voltage scaling range selection
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bit_offset: 9
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bit_size: 2
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enum: VOS
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- name: LPR
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description: Low-power run
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bit_offset: 14
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bit_size: 1
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enum: LPR
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fieldset/CR2:
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description: Power control register 2
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fields:
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- name: PVDE
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description: Power voltage detector enable
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bit_offset: 0
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bit_size: 1
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enum: PVDE
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- name: PLS
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description: Power voltage detector level selection.
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bit_offset: 1
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bit_size: 3
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enum: PLS
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- name: PVME
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description: "Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V"
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bit_offset: 6
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bit_size: 1
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enum: PVME
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fieldset/CR3:
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description: Power control register 3
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fields:
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- name: EWUP
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description: Enable Wakeup pin WKUP1 for CPU1
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bit_offset: 0
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bit_size: 1
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array:
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len: 3
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stride: 1
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enum: EWUP
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- name: EULPEN
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description: Ultra-low-power enable
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bit_offset: 7
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bit_size: 1
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enum: EULPEN
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- name: EWPVD
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description: Enable wakeup PVD for CPU1
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bit_offset: 8
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bit_size: 1
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enum: EWPVD
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- name: RRS
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description: SRAM2 retention in Standby mode
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bit_offset: 9
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bit_size: 1
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enum: RRS
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- name: APC
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description: Apply pull-up and pull-down configuration from CPU1
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bit_offset: 10
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bit_size: 1
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enum: APC
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- name: EWRFBUSY
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description: Enable Radio BUSY Wakeup from Standby for CPU1
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bit_offset: 11
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bit_size: 1
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enum: EWRFBUSY
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- name: EWRFIRQ
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description: akeup for CPU1
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bit_offset: 13
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bit_size: 1
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enum: EWRFIRQ
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- name: EC2H
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description: nable CPU2 Hold interrupt for CPU1
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bit_offset: 14
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bit_size: 1
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- name: EIWUL
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description: Enable internal wakeup line for CPU1
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bit_offset: 15
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bit_size: 1
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enum: EIWUL
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fieldset/CR4:
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description: Power control register 4
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fields:
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- name: WP
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description: Wakeup pin WKUP1 polarity
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bit_offset: 0
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bit_size: 1
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array:
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len: 3
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stride: 1
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enum: WP
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- name: VBE
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description: VBAT battery charging enable
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bit_offset: 8
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bit_size: 1
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enum: VBE
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- name: VBRS
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description: VBAT battery charging resistor selection
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bit_offset: 9
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bit_size: 1
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enum: VBRS
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- name: WRFBUSYP
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description: Wakeup Radio BUSY polarity
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bit_offset: 11
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bit_size: 1
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enum: WRFBUSYP
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- name: C2BOOT
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description: oot CPU2 after reset or wakeup from Stop or Standby modes.
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bit_offset: 15
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bit_size: 1
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fieldset/CR5:
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description: Power control register 5
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fields:
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- name: RFEOLEN
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description: Enable Radio End Of Life detector enabled
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bit_offset: 14
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bit_size: 1
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enum: RFEOLEN
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- name: SMPSEN
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description: Enable SMPS Step Down converter SMPS mode enabled.
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bit_offset: 15
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bit_size: 1
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enum: SMPSEN
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fieldset/EXTSCR:
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description: Power extended status and status clear register
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fields:
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- name: C1CSSF
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description: Clear CPU1 Stop Standby flags
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bit_offset: 0
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bit_size: 1
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- name: C2CSSF
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description: lear CPU2 Stop Standby flags
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bit_offset: 1
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bit_size: 1
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- name: C1SBF
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description: System Standby flag for CPU1. (no core states retained)
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bit_offset: 8
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bit_size: 1
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enum: CSBF
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- name: C1STOP2F
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description: System Stop2 flag for CPU1. (partial core states retained)
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bit_offset: 9
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bit_size: 1
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enum: CSTOPF
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- name: C1STOPF
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description: "System Stop0, 1 flag for CPU1. (All core states retained)"
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bit_offset: 10
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bit_size: 1
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enum: CSTOPF
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- name: C2SBF
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description: ystem Standby flag for CPU2. (no core states retained)
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bit_offset: 11
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bit_size: 1
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- name: C2STOP2F
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description: ystem Stop2 flag for CPU2. (partial core states retained)
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bit_offset: 12
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bit_size: 1
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- name: C2STOPF
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description: "ystem Stop0, 1 flag for CPU2. (All core states retained)"
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bit_offset: 13
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bit_size: 1
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- name: C1DS
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description: CPU1 deepsleep mode
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bit_offset: 14
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bit_size: 1
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enum: CDS
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- name: C2DS
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description: PU2 deepsleep mode
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bit_offset: 15
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bit_size: 1
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fieldset/PCR:
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description: Power Port pull control register
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fields:
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- name: P
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description: Port pull bit y (y=0..15)
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bit_offset: 0
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bit_size: 1
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array:
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len: 16
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stride: 1
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fieldset/RSSCMDR:
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description: "RSS Command register [dual core device only]"
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fields:
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- name: RSSCMD
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description: RSS command
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bit_offset: 0
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bit_size: 8
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fieldset/SCR:
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description: Power status clear register
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fields:
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- name: CWUF
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description: Clear wakeup flag 1
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bit_offset: 0
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bit_size: 1
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array:
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len: 3
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stride: 1
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- name: CWPVDF
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description: Clear wakeup PVD interrupt flag
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bit_offset: 8
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bit_size: 1
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- name: CWRFBUSYF
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description: Clear wakeup Radio BUSY flag
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bit_offset: 11
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bit_size: 1
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- name: CC2HF
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description: lear CPU2 Hold interrupt flag
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bit_offset: 14
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bit_size: 1
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fieldset/SECCFGR:
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description: "Power security configuration register [dual core device only]"
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fields:
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- name: C2EWILA
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description: wakeup on CPU2 illegal access interrupt enable
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bit_offset: 15
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bit_size: 1
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fieldset/SR1:
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description: Power status register 1
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fields:
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- name: WUF
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description: Wakeup flag 1
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bit_offset: 0
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bit_size: 1
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array:
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len: 3
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stride: 1
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enum: WUF
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- name: WPVDF
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description: Wakeup PVD flag
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bit_offset: 8
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bit_size: 1
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enum: WPVDF
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- name: WRFBUSYF
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description: Radio BUSY wakeup flag
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bit_offset: 11
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bit_size: 1
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enum: WRFBUSYF
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- name: C2HF
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description: PU2 Hold interrupt flag
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bit_offset: 14
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bit_size: 1
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- name: WUFI
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description: Internal wakeup interrupt flag
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bit_offset: 15
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bit_size: 1
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enum: WUFI
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fieldset/SR2:
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description: Power status register 2
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fields:
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- name: C2BOOTS
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description: PU2 boot/wakeup request source information
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bit_offset: 0
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bit_size: 1
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- name: RFBUSYS
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description: Radio BUSY signal status
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bit_offset: 1
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bit_size: 1
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enum: RFBUSYS
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- name: RFBUSYMS
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description: Radio BUSY masked signal status
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bit_offset: 2
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bit_size: 1
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enum: RFBUSYMS
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- name: SMPSRDY
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description: SMPS ready flag
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bit_offset: 3
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bit_size: 1
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enum: SMPSRDY
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- name: LDORDY
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description: LDO ready flag
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bit_offset: 4
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bit_size: 1
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enum: LDORDY
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- name: RFEOLF
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description: Radio end of life flag
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bit_offset: 5
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bit_size: 1
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enum: RFEOLF
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- name: REGMRS
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description: regulator2 low power flag
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bit_offset: 6
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bit_size: 1
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enum: REGMRS
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- name: FLASHRDY
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description: Flash ready
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bit_offset: 7
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bit_size: 1
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enum: FLASHRDY
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- name: REGLPS
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description: regulator1 started
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bit_offset: 8
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bit_size: 1
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enum: REGLPS
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- name: REGLPF
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description: regulator1 low power flag
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bit_offset: 9
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bit_size: 1
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enum: REGLPF
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- name: VOSF
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description: Voltage scaling flag
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bit_offset: 10
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bit_size: 1
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enum: VOSF
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- name: PVDO
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description: Power voltage detector output
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bit_offset: 11
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bit_size: 1
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enum: PVDO
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- name: PVMO
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description: "Peripheral voltage monitoring output: VDDA vs. 1.62 V"
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bit_offset: 14
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bit_size: 1
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enum: PVMO
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fieldset/SUBGHZSPICR:
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description: Power SPI3 control register
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fields:
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- name: NSS
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description: sub-GHz SPI NSS control
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bit_offset: 15
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bit_size: 1
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enum: NSS
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enum/APC:
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bit_size: 1
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variants:
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- name: Disabled
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description: I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied
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value: 0
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- name: Enabled
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description: PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os
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value: 1
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enum/CDS:
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bit_size: 1
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variants:
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- name: RunningOrSleep
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description: CPU is running or in sleep
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value: 0
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- name: DeepSleep
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description: CPU is in Deep-Sleep
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value: 1
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enum/CSBF:
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bit_size: 1
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variants:
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- name: NoStandby
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description: System has not been in Standby mode
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value: 0
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- name: Standby
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description: System has been in Standby mode
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value: 1
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enum/CSTOPF:
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bit_size: 1
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variants:
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- name: NoStop
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description: System has not been in Stop 2 mode
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value: 0
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- name: Stop
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description: System has been in Stop 2 mode
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value: 1
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enum/DBP:
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bit_size: 1
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variants:
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- name: Disabled
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description: Access to RTC and backup registers disabled
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value: 0
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- name: Enabled
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description: Access to RTC and backup registers enabled
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value: 1
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enum/EIWUL:
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bit_size: 1
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variants:
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- name: Disabled
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description: Internal wakeup line interrupt to CPU disabled
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value: 0
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- name: Enabled
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description: Internal wakeup line interrupt to CPU enabled
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value: 1
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enum/EULPEN:
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bit_size: 1
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variants:
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- name: Disabled
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description: Disable (the supply voltage is monitored continuously)
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value: 0
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- name: Enabled
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description: "Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only periodically"
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value: 1
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enum/EWPVD:
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bit_size: 1
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variants:
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- name: Disabled
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description: PVD not enabled by the sub-GHz radio active state
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value: 0
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- name: Enabled
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description: PVD enabled while the sub-GHz radio is active
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value: 1
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enum/EWRFBUSY:
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bit_size: 1
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variants:
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- name: Disabled
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description: Radio Busy is disabled and does not trigger a wakeup from Standby event to CPUwhen a rising or a falling edge occurs
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value: 0
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- name: Enabled
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description: Radio Busy is enabled and triggers a wakeup from Standby event to CPUwhen a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4
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value: 1
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enum/EWRFIRQ:
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bit_size: 1
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variants:
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- name: Disabled
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description: "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU."
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value: 0
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- name: Enabled
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description: "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU."
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value: 1
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enum/EWUP:
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bit_size: 1
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variants:
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- name: Disabled
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description: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode
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value: 0
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- name: Enabled
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description: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode)
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value: 1
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enum/FLASHRDY:
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bit_size: 1
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variants:
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- name: NotReady
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|
description: Flash memory not ready to be accessed
|
|
value: 0
|
|
- name: Ready
|
|
description: Flash memory ready to be accessed
|
|
value: 1
|
|
enum/FPDR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Idle
|
|
description: Flash memory in Idle mode when system is in LPRun mode
|
|
value: 0
|
|
- name: PowerDown
|
|
description: Flash memory in Power-down mode when system is in LPRun mode
|
|
value: 1
|
|
enum/FPDS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Idle
|
|
description: Flash memory in Idle mode when system is in LPSleep mode
|
|
value: 0
|
|
- name: PowerDown
|
|
description: Flash memory in Power-down mode when system is in LPSleep mode
|
|
value: 1
|
|
enum/LDORDY:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotReady
|
|
description: LDO not ready or off
|
|
value: 0
|
|
- name: Ready
|
|
description: LDO ready
|
|
value: 1
|
|
enum/LPMS:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Stop0
|
|
description: Stop 0 mode
|
|
value: 0
|
|
- name: Stop1
|
|
description: Stop 1 mode
|
|
value: 1
|
|
- name: Stop2
|
|
description: Stop 2 mode
|
|
value: 2
|
|
- name: Standby
|
|
description: Standby mode
|
|
value: 3
|
|
- name: Shutdown
|
|
description: Shutdown mode
|
|
value: 4
|
|
enum/LPR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: MainMode
|
|
description: Voltage regulator in Main mode in Low-power run mode
|
|
value: 0
|
|
- name: LowPowerMode
|
|
description: Voltage regulator in low-power mode in Low-power run mode
|
|
value: 1
|
|
enum/NSS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Low
|
|
description: Sub-GHz SPI NSS signal at level low
|
|
value: 0
|
|
- name: High
|
|
description: Sub-GHz SPI NSS signal is at level high
|
|
value: 1
|
|
enum/PLS:
|
|
bit_size: 3
|
|
variants:
|
|
- name: V2_0
|
|
description: 2.0V
|
|
value: 0
|
|
- name: V2_2
|
|
description: 2.2V
|
|
value: 1
|
|
- name: V2_4
|
|
description: 2.4V
|
|
value: 2
|
|
- name: V2_5
|
|
description: 2.5V
|
|
value: 3
|
|
- name: V2_6
|
|
description: 2.6V
|
|
value: 4
|
|
- name: V2_8
|
|
description: 2.8V
|
|
value: 5
|
|
- name: V2_9
|
|
description: 2.9V
|
|
value: 6
|
|
- name: External
|
|
description: External input analog voltage PVD_IN (compared internally to VREFINT)
|
|
value: 7
|
|
enum/PVDE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: PVD Disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: PVD Enabled
|
|
value: 1
|
|
enum/PVDO:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Above
|
|
description: VDD or voltage level on PVD_IN above the selected PVD threshold
|
|
value: 0
|
|
- name: Below
|
|
description: VDD or voltage level on PVD_IN below the selected PVD threshold
|
|
value: 1
|
|
enum/PVME:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: PVM3 (VDDA monitoring versus 1.62 V threshold) disable
|
|
value: 0
|
|
- name: Enabled
|
|
description: PVM3 (VDDA monitoring versus 1.62 V threshold) enable
|
|
value: 1
|
|
enum/PVMO:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Above
|
|
description: VDDA voltage above PVM3 threshold (around 1.62 V)
|
|
value: 0
|
|
- name: Below
|
|
description: VDDA voltage below PVM3 threshold (around 1.62 V)
|
|
value: 1
|
|
enum/REGLPF:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Main
|
|
description: Main regulator (MR) ready and used
|
|
value: 0
|
|
- name: LowPower
|
|
description: Low-power regulator (LPR) used
|
|
value: 1
|
|
enum/REGLPS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotReady
|
|
description: LPR not ready
|
|
value: 0
|
|
- name: Ready
|
|
description: LPR ready
|
|
value: 1
|
|
enum/REGMRS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: V_DD
|
|
description: Main regulator supplied directly from VDD
|
|
value: 0
|
|
- name: LDO_SMPS
|
|
description: Main regulator supplied through LDO or SMPS
|
|
value: 1
|
|
enum/RFBUSYMS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotBusy
|
|
description: radio busy masked signal low (not busy)
|
|
value: 0
|
|
- name: Busy
|
|
description: radio busy masked signal high (busy)
|
|
value: 1
|
|
enum/RFBUSYS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotBusy
|
|
description: radio busy signal low (not busy)
|
|
value: 0
|
|
- name: Busy
|
|
description: radio busy signal high (busy)
|
|
value: 1
|
|
enum/RFEOLEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: Radio end-of-life detector disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: Radio end-of-life detector enabled
|
|
value: 1
|
|
enum/RFEOLF:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Above
|
|
description: Supply voltage above radio end-of-life operating low level
|
|
value: 0
|
|
- name: Below
|
|
description: Supply voltage below radio end-of-life operating low level
|
|
value: 1
|
|
enum/RRS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: PowerOff
|
|
description: SRAM2 powered off in Standby mode (SRAM2 content lost)
|
|
value: 0
|
|
- name: OnLPR
|
|
description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)
|
|
value: 1
|
|
enum/SMPSEN:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: SMPS step-down converter SMPS mode disabled (LDO mode enabled)
|
|
value: 0
|
|
- name: Enabled
|
|
description: SMPS step-down converter SMPS mode enabled
|
|
value: 1
|
|
enum/SMPSRDY:
|
|
bit_size: 1
|
|
variants:
|
|
- name: NotReady
|
|
description: SMPS step-down converter not ready or off
|
|
value: 0
|
|
- name: Ready
|
|
description: SMPS step-down converter ready
|
|
value: 1
|
|
enum/SUBGHZSPINSSSEL:
|
|
bit_size: 1
|
|
variants:
|
|
- name: SUBGHZSPICR
|
|
description: sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled)
|
|
value: 0
|
|
- name: LPTIM3
|
|
description: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)
|
|
value: 1
|
|
enum/VBE:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Disabled
|
|
description: VBAT battery charging disabled
|
|
value: 0
|
|
- name: Enabled
|
|
description: VBAT battery charging enabled
|
|
value: 1
|
|
enum/VBRS:
|
|
bit_size: 1
|
|
variants:
|
|
- name: R5k
|
|
description: VBAT charging through a 5 kΩ resistor
|
|
value: 0
|
|
- name: R1_5k
|
|
description: VBAT charging through a 1.5 kΩ resistor
|
|
value: 1
|
|
enum/VOS:
|
|
bit_size: 2
|
|
variants:
|
|
- name: V1_2
|
|
description: 1.2 V (range 1)
|
|
value: 1
|
|
- name: V1_0
|
|
description: 1.0 V (range 2)
|
|
value: 2
|
|
enum/VOSF:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Ready
|
|
description: Regulator ready in the selected voltage range
|
|
value: 0
|
|
- name: Change
|
|
description: Regulator output voltage changed to the required voltage level
|
|
value: 1
|
|
enum/WP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: RisingEdge
|
|
description: Detection on high level (rising edge)
|
|
value: 0
|
|
- name: FallingEdge
|
|
description: Detection on low level (falling edge)
|
|
value: 1
|
|
enum/WPVDF:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: No wakeup event detected on PVD
|
|
value: 0
|
|
- name: Wakeup
|
|
description: Wakeup event detected on PVD
|
|
value: 1
|
|
enum/WRFBUSYF:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: No wakeup event detected on radio busy
|
|
value: 0
|
|
- name: Wakeup
|
|
description: Wakeup event detected on radio busy
|
|
value: 1
|
|
enum/WRFBUSYP:
|
|
bit_size: 1
|
|
variants:
|
|
- name: RisingEdge
|
|
description: Detection on high level (rising edge)
|
|
value: 0
|
|
- name: FallingEdge
|
|
description: Detection on low level (falling edge)
|
|
value: 1
|
|
enum/WUF:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: No wakeup event detected on WKUP3
|
|
value: 0
|
|
- name: Wakeup
|
|
description: Wakeup event detected on WKUP3
|
|
value: 1
|
|
enum/WUFI:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Clear
|
|
description: All internal wakeup sources are cleared
|
|
value: 0
|
|
- name: Wakeup
|
|
description: wakeup is detected on the internal wakeup line
|
|
value: 1
|