526 lines
11 KiB
YAML
526 lines
11 KiB
YAML
---
|
|
block/ADC:
|
|
description: Analog-to-Digital Converter
|
|
items:
|
|
- name: ISR
|
|
description: interrupt and status register
|
|
byte_offset: 0
|
|
fieldset: ISR
|
|
- name: IER
|
|
description: interrupt enable register
|
|
byte_offset: 4
|
|
fieldset: IER
|
|
- name: CR
|
|
description: control register
|
|
byte_offset: 8
|
|
fieldset: CR
|
|
- name: CFGR
|
|
description: configuration register
|
|
byte_offset: 12
|
|
fieldset: CFGR
|
|
- name: CFGR2
|
|
description: configuration register
|
|
byte_offset: 16
|
|
fieldset: CFGR2
|
|
- name: SMPR
|
|
description: sample time register 1
|
|
array:
|
|
len: 2
|
|
stride: 4
|
|
byte_offset: 20
|
|
fieldset: SMPR
|
|
- name: TR
|
|
description: watchdog threshold register 1
|
|
array:
|
|
len: 3
|
|
stride: 4
|
|
byte_offset: 32
|
|
fieldset: TR
|
|
- name: SQR1
|
|
description: regular sequence register 1
|
|
byte_offset: 48
|
|
fieldset: SQR1
|
|
- name: SQR2
|
|
description: regular sequence register 2
|
|
byte_offset: 52
|
|
fieldset: SQR2
|
|
- name: SQR3
|
|
description: regular sequence register 3
|
|
byte_offset: 56
|
|
fieldset: SQR3
|
|
- name: SQR4
|
|
description: regular sequence register 4
|
|
byte_offset: 60
|
|
fieldset: SQR4
|
|
- name: DR
|
|
description: regular Data Register
|
|
byte_offset: 64
|
|
access: Read
|
|
fieldset: DR
|
|
- name: JSQR
|
|
description: injected sequence register
|
|
byte_offset: 76
|
|
fieldset: JSQR
|
|
- name: OFR
|
|
description: offset register 1
|
|
array:
|
|
len: 4
|
|
stride: 4
|
|
byte_offset: 96
|
|
fieldset: OFR
|
|
- name: JDR
|
|
description: injected data registers
|
|
array:
|
|
len: 4
|
|
stride: 4
|
|
byte_offset: 128
|
|
access: Read
|
|
fieldset: JDR
|
|
- name: AWD2CR
|
|
description: Analog Watchdog 2 Configuration Register
|
|
byte_offset: 160
|
|
fieldset: AWD2CR
|
|
- name: AWD3CR
|
|
description: Analog Watchdog 3 Configuration Register
|
|
byte_offset: 164
|
|
fieldset: AWD3CR
|
|
- name: DIFSEL
|
|
description: Differential Mode Selection Register 2
|
|
byte_offset: 176
|
|
fieldset: DIFSEL
|
|
- name: CALFACT
|
|
description: Calibration Factors
|
|
byte_offset: 180
|
|
fieldset: CALFACT
|
|
fieldset/AWD2CR:
|
|
description: Analog Watchdog 2 Configuration Register
|
|
fields:
|
|
- name: AWD2CH
|
|
description: AWD2CH
|
|
bit_offset: 1
|
|
bit_size: 18
|
|
fieldset/AWD3CR:
|
|
description: Analog Watchdog 3 Configuration Register
|
|
fields:
|
|
- name: AWD3CH
|
|
description: AWD3CH
|
|
bit_offset: 1
|
|
bit_size: 18
|
|
fieldset/CALFACT:
|
|
description: Calibration Factors
|
|
fields:
|
|
- name: CALFACT_S
|
|
description: CALFACT_S
|
|
bit_offset: 0
|
|
bit_size: 7
|
|
- name: CALFACT_D
|
|
description: CALFACT_D
|
|
bit_offset: 16
|
|
bit_size: 7
|
|
fieldset/CFGR:
|
|
description: configuration register
|
|
fields:
|
|
- name: DMAEN
|
|
description: DMAEN
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: DMACFG
|
|
description: DMACFG
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: RES
|
|
description: RES
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: RES
|
|
- name: ALIGN
|
|
description: ALIGN
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: EXTSEL
|
|
description: EXTSEL
|
|
bit_offset: 6
|
|
bit_size: 4
|
|
- name: EXTEN
|
|
description: EXTEN
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
- name: OVRMOD
|
|
description: OVRMOD
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: CONT
|
|
description: CONT
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: AUTDLY
|
|
description: AUTDLY
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: AUTOFF
|
|
description: AUTOFF
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: DISCEN
|
|
description: DISCEN
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: DISCNUM
|
|
description: DISCNUM
|
|
bit_offset: 17
|
|
bit_size: 3
|
|
- name: JDISCEN
|
|
description: JDISCEN
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: JQM
|
|
description: JQM
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: AWD1SGL
|
|
description: AWD1SGL
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: AWD1EN
|
|
description: AWD1EN
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: JAWD1EN
|
|
description: JAWD1EN
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: JAUTO
|
|
description: JAUTO
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: AWDCH1CH
|
|
description: AWDCH1CH
|
|
bit_offset: 26
|
|
bit_size: 5
|
|
fieldset/CFGR2:
|
|
description: configuration register
|
|
fields:
|
|
- name: ROVSE
|
|
description: DMAEN
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: JOVSE
|
|
description: DMACFG
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: OVSR
|
|
description: RES
|
|
bit_offset: 2
|
|
bit_size: 3
|
|
- name: OVSS
|
|
description: ALIGN
|
|
bit_offset: 5
|
|
bit_size: 4
|
|
- name: TOVS
|
|
description: EXTSEL
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: ROVSM
|
|
description: EXTEN
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: control register
|
|
fields:
|
|
- name: ADEN
|
|
description: ADEN
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: ADDIS
|
|
description: ADDIS
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: ADSTART
|
|
description: ADSTART
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: JADSTART
|
|
description: JADSTART
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: ADSTP
|
|
description: ADSTP
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: JADSTP
|
|
description: JADSTP
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: ADVREGEN
|
|
description: ADVREGEN
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: DEEPPWD
|
|
description: DEEPPWD
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: ADCALDIF
|
|
description: ADCALDIF
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: ADCAL
|
|
description: ADCAL
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/DIFSEL:
|
|
description: Differential Mode Selection Register 2
|
|
fields:
|
|
- name: DIFSEL_1_15
|
|
description: Differential mode for channels 15 to 1
|
|
bit_offset: 1
|
|
bit_size: 15
|
|
- name: DIFSEL_16_18
|
|
description: Differential mode for channels 18 to 16
|
|
bit_offset: 16
|
|
bit_size: 3
|
|
fieldset/DR:
|
|
description: regular Data Register
|
|
fields:
|
|
- name: regularDATA
|
|
description: regularDATA
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/IER:
|
|
description: interrupt enable register
|
|
fields:
|
|
- name: ADRDYIE
|
|
description: ADRDYIE
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EOSMPIE
|
|
description: EOSMPIE
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: EOCIE
|
|
description: EOCIE
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: EOSIE
|
|
description: EOSIE
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: OVRIE
|
|
description: OVRIE
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: JEOCIE
|
|
description: JEOCIE
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: JEOSIE
|
|
description: JEOSIE
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: AWD1IE
|
|
description: AWD1IE
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
- name: AWD2IE
|
|
description: AWD2IE
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: AWD3IE
|
|
description: AWD3IE
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: JQOVFIE
|
|
description: JQOVFIE
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/ISR:
|
|
description: interrupt and status register
|
|
fields:
|
|
- name: ADRDY
|
|
description: ADRDY
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: EOSMP
|
|
description: EOSMP
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: EOC
|
|
description: EOC
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: EOS
|
|
description: EOS
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: OVR
|
|
description: OVR
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: JEOC
|
|
description: JEOC
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: JEOS
|
|
description: JEOS
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: AWD
|
|
description: AWD1
|
|
bit_offset: 7
|
|
bit_size: 1
|
|
array:
|
|
len: 3
|
|
stride: 1
|
|
- name: JQOVF
|
|
description: JQOVF
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/JDR:
|
|
description: injected data register 1
|
|
fields:
|
|
- name: JDATA
|
|
description: JDATA1
|
|
bit_offset: 0
|
|
bit_size: 16
|
|
fieldset/JSQR:
|
|
description: injected sequence register
|
|
fields:
|
|
- name: JL
|
|
description: JL
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: JEXTSEL
|
|
description: JEXTSEL
|
|
bit_offset: 2
|
|
bit_size: 4
|
|
- name: JEXTEN
|
|
description: JEXTEN
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: JSQ
|
|
description: JSQ1
|
|
bit_offset: 8
|
|
bit_size: 5
|
|
array:
|
|
len: 4
|
|
stride: 6
|
|
fieldset/OFR:
|
|
description: offset register
|
|
fields:
|
|
- name: OFFSET
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: OFFSET_CH
|
|
bit_offset: 26
|
|
bit_size: 5
|
|
- name: OFFSET_EN
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/SMPR:
|
|
description: sample time register 1
|
|
fields:
|
|
- name: SMP
|
|
description: Channel 0 sampling time selection
|
|
bit_offset: 0
|
|
bit_size: 3
|
|
array:
|
|
len: 10
|
|
stride: 3
|
|
enum: SAMPLE_TIME
|
|
fieldset/SQR1:
|
|
description: regular sequence register 1
|
|
fields:
|
|
- name: L
|
|
description: Regular channel sequence length
|
|
bit_offset: 0
|
|
bit_size: 4
|
|
- name: SQ
|
|
description: SQ1
|
|
bit_offset: 6
|
|
bit_size: 5
|
|
array:
|
|
len: 4
|
|
stride: 6
|
|
fieldset/SQR2:
|
|
description: regular sequence register 2
|
|
fields:
|
|
- name: SQ
|
|
description: SQ5
|
|
bit_offset: 0
|
|
bit_size: 5
|
|
array:
|
|
len: 5
|
|
stride: 6
|
|
fieldset/SQR3:
|
|
description: regular sequence register 3
|
|
fields:
|
|
- name: SQ
|
|
description: SQ10
|
|
bit_offset: 0
|
|
bit_size: 5
|
|
array:
|
|
len: 5
|
|
stride: 6
|
|
fieldset/SQR4:
|
|
description: regular sequence register 4
|
|
fields:
|
|
- name: SQ
|
|
description: SQ15
|
|
bit_offset: 0
|
|
bit_size: 5
|
|
array:
|
|
len: 2
|
|
stride: 6
|
|
fieldset/TR:
|
|
description: watchdog threshold register
|
|
fields:
|
|
- name: LT
|
|
description: LT1
|
|
bit_offset: 0
|
|
bit_size: 12
|
|
- name: HT
|
|
description: HT1
|
|
bit_offset: 16
|
|
bit_size: 12
|
|
enum/RES:
|
|
bit_size: 2
|
|
variants:
|
|
- name: TwelveBit
|
|
description: 12-bit resolution
|
|
value: 0
|
|
- name: TenBit
|
|
description: 10-bit resolution
|
|
value: 1
|
|
- name: EightBit
|
|
description: 8-bit resolution
|
|
value: 2
|
|
- name: SixBit
|
|
description: 6-bit resolution
|
|
value: 3
|
|
enum/SAMPLE_TIME:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Cycles2_5
|
|
description: 2.5 ADC cycles
|
|
value: 0
|
|
- name: Cycles6_5
|
|
description: 6.5 ADC cycles
|
|
value: 1
|
|
- name: Cycles12_5
|
|
description: 12.5 ADC cycles
|
|
value: 2
|
|
- name: Cycles24_5
|
|
description: 24.5 ADC cycles
|
|
value: 3
|
|
- name: Cycles47_5
|
|
description: 47.5 ADC cycles
|
|
value: 4
|
|
- name: Cycles92_5
|
|
description: 92.5 ADC cycles
|
|
value: 5
|
|
- name: Cycles247_5
|
|
description: 247.5 ADC cycles
|
|
value: 6
|
|
- name: Cycles640_5
|
|
description: 640.5 ADC cycles
|
|
value: 7
|