183 lines
2.5 KiB
YAML
183 lines
2.5 KiB
YAML
PA0:
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CM4_EVENTOUT: 15
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COMP1_OUT: 12
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TIM2_CH1: 1
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TIM2_ETR: 14
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PA1:
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CM4_EVENTOUT: 15
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I2C1_SMBA: 4
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SPI1_SCK: 5
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TIM2_CH2: 1
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PA10:
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CM4_EVENTOUT: 15
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I2C1_SDA: 4
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TIM1_CH3: 1
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TSC_G7_IO2: 9
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USART1_RX: 7
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PA11:
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CM4_EVENTOUT: 15
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SPI1_MISO: 5
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TIM1_BKIN2: 2
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TIM1_CH4: 1
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USART1_CTS: 7
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USART1_NSS: 7
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PA12:
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CM4_EVENTOUT: 15
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LPUART1_RX: 8
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SPI1_MOSI: 5
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TIM1_ETR: 1
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USART1_DE: 7
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USART1_RTS: 7
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PA13:
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CM4_EVENTOUT: 15
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SPI1_MOSI: 5
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SYS_JTMS-SWDIO: 0
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TSC_G7_IO1: 9
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PA14:
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CM4_EVENTOUT: 15
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I2C1_SMBA: 4
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LPTIM1_OUT: 1
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SPI1_NSS: 5
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SYS_JTCK-SWCLK: 0
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PA15:
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CM4_EVENTOUT: 15
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RCC_MCO: 6
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SPI1_NSS: 5
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SYS_JTDI: 0
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TIM2_CH1: 1
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TIM2_ETR: 2
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TSC_G3_IO1: 9
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PA2:
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CM4_EVENTOUT: 15
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LPUART1_TX: 8
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RCC_LSCO: 0
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TIM2_CH3: 1
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PA3:
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CM4_EVENTOUT: 15
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LPUART1_RX: 8
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TIM2_CH4: 1
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PA4:
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CM4_EVENTOUT: 15
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LPTIM2_OUT: 14
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SPI1_NSS: 5
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PA5:
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CM4_EVENTOUT: 15
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LPTIM2_ETR: 14
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SPI1_MOSI: 4
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SPI1_SCK: 5
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TIM2_CH1: 1
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TIM2_ETR: 2
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PA6:
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CM4_EVENTOUT: 15
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LPUART1_CTS: 8
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SPI1_MISO: 5
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TIM1_BKIN: 1
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PA7:
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CM4_EVENTOUT: 15
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SPI1_MOSI: 5
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TIM1_CH1N: 1
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PA8:
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CM4_EVENTOUT: 15
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LPTIM2_OUT: 14
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RCC_MCO: 0
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TIM1_CH1: 1
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USART1_CK: 7
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PA9:
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CM4_EVENTOUT: 15
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I2C1_SCL: 4
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TIM1_CH2: 1
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USART1_TX: 7
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PB0:
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CM4_EVENTOUT: 15
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COMP1_OUT: 12
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RF_TX_MOD_EXT_PA: 6
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PB1:
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CM4_EVENTOUT: 15
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LPTIM2_IN1: 14
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LPUART1_DE: 8
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LPUART1_RTS: 8
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PB10:
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CM4_EVENTOUT: 15
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TSC_G3_IO2: 9
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PB12:
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CM4_EVENTOUT: 15
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TIM2_CH2: 1
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TSC_G1_IO1: 9
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PB13:
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CM4_EVENTOUT: 15
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TIM2_CH3: 1
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TSC_G1_IO2: 9
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PB14:
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CM4_EVENTOUT: 15
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TIM1_CH1: 1
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PB15:
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CM4_EVENTOUT: 15
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TIM2_CH1: 1
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PB2:
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CM4_EVENTOUT: 15
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LPTIM1_OUT: 1
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RTC_OUT: 0
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SPI1_NSS: 5
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PB3:
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CM4_EVENTOUT: 15
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SPI1_SCK: 5
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SYS_JTDO-SWO: 0
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TIM2_CH2: 1
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USART1_DE: 7
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USART1_RTS: 7
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PB4:
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CM4_EVENTOUT: 15
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SPI1_MISO: 5
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SYS_JTRST: 0
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TSC_G2_IO1: 9
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USART1_CTS: 7
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USART1_NSS: 7
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PB5:
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CM4_EVENTOUT: 15
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I2C1_SMBA: 4
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LPTIM1_IN1: 1
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LPUART1_TX: 8
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SPI1_MOSI: 5
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TSC_G2_IO2: 9
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USART1_CK: 7
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PB6:
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CM4_EVENTOUT: 15
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I2C1_SCL: 4
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LPTIM1_ETR: 1
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RCC_MCO: 0
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SPI1_NSS: 5
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TSC_G2_IO3: 9
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USART1_TX: 7
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PB7:
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CM4_EVENTOUT: 15
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I2C1_SDA: 4
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LPTIM1_IN2: 1
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TIM1_BKIN: 3
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TIM1_CH3: 12
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TSC_G2_IO4: 9
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USART1_RX: 7
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PB8:
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CM4_EVENTOUT: 15
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I2C1_SCL: 4
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TIM1_CH2N: 1
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TSC_G7_IO3: 9
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PB9:
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CM4_EVENTOUT: 15
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I2C1_SDA: 4
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TIM1_CH3N: 1
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TSC_G7_IO4: 9
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PC1:
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CM4_EVENTOUT: 15
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TSC_G3_IO3: 9
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PC13: {}
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PC14:
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CM4_EVENTOUT: 15
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PC15:
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CM4_EVENTOUT: 15
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PE4:
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CM4_EVENTOUT: 15
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PH3:
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CM4_EVENTOUT: 15
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RCC_LSCO: 0
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PI8: {}
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