619 lines
13 KiB
YAML
619 lines
13 KiB
YAML
block/SPI:
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description: Serial peripheral interface
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items:
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- name: CR1
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description: control register 1
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byte_offset: 0
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fieldset: CR1
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- name: CR2
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description: control register 2
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byte_offset: 4
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fieldset: CR2
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- name: SR
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description: status register
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byte_offset: 8
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fieldset: SR
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- name: DR
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description: data register
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byte_offset: 12
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fieldset: DR
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- name: CRCPR
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description: CRC polynomial register
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byte_offset: 16
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fieldset: CRCPR
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- name: RXCRCR
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description: RX CRC register
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byte_offset: 20
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access: Read
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fieldset: RXCRCR
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- name: TXCRCR
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description: TX CRC register
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byte_offset: 24
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access: Read
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fieldset: TXCRCR
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- name: I2SCFGR
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description: I2S configuration register
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byte_offset: 28
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fieldset: I2SCFGR
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- name: I2SPR
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description: I2S prescaler register
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byte_offset: 32
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fieldset: I2SPR
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fieldset/CR1:
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description: control register 1
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fields:
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- name: CPHA
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description: Clock phase
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bit_offset: 0
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bit_size: 1
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enum: CPHA
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- name: CPOL
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description: Clock polarity
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bit_offset: 1
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bit_size: 1
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enum: CPOL
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- name: MSTR
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description: Master selection
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bit_offset: 2
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bit_size: 1
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enum: MSTR
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- name: BR
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description: Baud rate control
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bit_offset: 3
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bit_size: 3
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enum: BR
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- name: SPE
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description: SPI enable
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bit_offset: 6
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bit_size: 1
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- name: LSBFIRST
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description: Frame format
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bit_offset: 7
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bit_size: 1
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enum: LSBFIRST
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- name: SSI
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description: Internal slave select
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bit_offset: 8
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bit_size: 1
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- name: SSM
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description: Software slave management
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bit_offset: 9
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bit_size: 1
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- name: RXONLY
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description: Receive only
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bit_offset: 10
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bit_size: 1
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enum: RXONLY
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- name: CRCL
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description: CRC length
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bit_offset: 11
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bit_size: 1
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enum: CRCL
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- name: CRCNEXT
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description: CRC transfer next
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bit_offset: 12
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bit_size: 1
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enum: CRCNEXT
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- name: CRCEN
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description: Hardware CRC calculation enable
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bit_offset: 13
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bit_size: 1
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- name: BIDIOE
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description: Output enable in bidirectional mode
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bit_offset: 14
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bit_size: 1
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enum: BIDIOE
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- name: BIDIMODE
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description: Bidirectional data mode enable
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bit_offset: 15
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bit_size: 1
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enum: BIDIMODE
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fieldset/CR2:
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description: control register 2
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fields:
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- name: RXDMAEN
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description: Rx buffer DMA enable
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bit_offset: 0
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bit_size: 1
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- name: TXDMAEN
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description: Tx buffer DMA enable
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bit_offset: 1
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bit_size: 1
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- name: SSOE
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description: SS output enable
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bit_offset: 2
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bit_size: 1
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- name: NSSP
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description: NSS pulse management
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bit_offset: 3
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bit_size: 1
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- name: FRF
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description: Frame format
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bit_offset: 4
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bit_size: 1
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enum: FRF
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- name: ERRIE
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description: Error interrupt enable
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bit_offset: 5
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bit_size: 1
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- name: RXNEIE
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description: RX buffer not empty interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: TXEIE
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description: Tx buffer empty interrupt enable
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bit_offset: 7
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bit_size: 1
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- name: DS
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description: Data size
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bit_offset: 8
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bit_size: 4
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enum: DS
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- name: FRXTH
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description: FIFO reception threshold
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bit_offset: 12
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bit_size: 1
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enum: FRXTH
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- name: LDMA_RX
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description: Last DMA transfer for reception
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bit_offset: 13
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bit_size: 1
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enum: LDMA_RX
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- name: LDMA_TX
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description: Last DMA transfer for transmission
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bit_offset: 14
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bit_size: 1
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enum: LDMA_TX
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fieldset/CRCPR:
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description: CRC polynomial register
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fields:
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- name: CRCPOLY
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description: CRC polynomial register
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bit_offset: 0
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bit_size: 16
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fieldset/DR:
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description: data register
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fields:
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- name: DR
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description: Data register
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bit_offset: 0
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bit_size: 16
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fieldset/I2SCFGR:
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description: I2S configuration register
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fields:
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- name: CHLEN
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description: Channel length (number of bits per audio channel)
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bit_offset: 0
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bit_size: 1
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enum: CHLEN
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- name: DATLEN
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description: Data length to be transferred
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bit_offset: 1
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bit_size: 2
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enum: DATLEN
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- name: CKPOL
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description: Steady state clock polarity
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bit_offset: 3
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bit_size: 1
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enum: CKPOL
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- name: I2SSTD
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description: I2S standard selection
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bit_offset: 4
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bit_size: 2
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enum: ISSTD
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- name: PCMSYNC
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description: PCM frame synchronization
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bit_offset: 7
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bit_size: 1
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enum: PCMSYNC
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- name: I2SCFG
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description: I2S configuration mode
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bit_offset: 8
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bit_size: 2
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enum: ISCFG
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- name: I2SE
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description: I2S Enabled
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bit_offset: 10
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bit_size: 1
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- name: I2SMOD
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description: I2S mode selection
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bit_offset: 11
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bit_size: 1
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enum: ISMOD
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- name: ASTRTEN
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description: Asynchronous start enable
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bit_offset: 12
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bit_size: 1
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fieldset/I2SPR:
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description: I2S prescaler register
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fields:
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- name: I2SDIV
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description: I2S Linear prescaler
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bit_offset: 0
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bit_size: 8
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- name: ODD
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description: Odd factor for the prescaler
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bit_offset: 8
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bit_size: 1
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enum: ODD
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- name: MCKOE
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description: Master clock output enable
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bit_offset: 9
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bit_size: 1
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fieldset/RXCRCR:
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description: RX CRC register
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fields:
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- name: RxCRC
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description: Rx CRC register
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bit_offset: 0
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bit_size: 16
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fieldset/SR:
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description: status register
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fields:
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- name: RXNE
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description: Receive buffer not empty
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bit_offset: 0
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bit_size: 1
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- name: TXE
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description: Transmit buffer empty
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bit_offset: 1
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bit_size: 1
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- name: CHSIDE
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description: Channel side
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bit_offset: 2
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bit_size: 1
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enum: CHSIDE
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- name: UDR
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description: Underrun flag
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bit_offset: 3
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bit_size: 1
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- name: CRCERR
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description: CRC error flag
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bit_offset: 4
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bit_size: 1
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- name: MODF
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description: Mode fault
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bit_offset: 5
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bit_size: 1
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- name: OVR
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description: Overrun flag
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bit_offset: 6
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bit_size: 1
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- name: BSY
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description: Busy flag
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bit_offset: 7
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bit_size: 1
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- name: FRE
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description: frame format error
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bit_offset: 8
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bit_size: 1
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- name: FRLVL
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description: FIFO reception level
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bit_offset: 9
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bit_size: 2
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enum: FRLVL
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- name: FTLVL
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description: FIFO Transmission Level
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bit_offset: 11
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bit_size: 2
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enum: FTLVL
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fieldset/TXCRCR:
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description: TX CRC register
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fields:
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- name: TxCRC
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description: Tx CRC register
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bit_offset: 0
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bit_size: 16
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enum/BIDIMODE:
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bit_size: 1
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variants:
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- name: Unidirectional
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description: 2-line unidirectional data mode selected
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value: 0
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- name: Bidirectional
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description: 1-line bidirectional data mode selected
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value: 1
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enum/BIDIOE:
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bit_size: 1
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variants:
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- name: OutputDisabled
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description: Output disabled (receive-only mode)
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value: 0
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- name: OutputEnabled
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description: Output enabled (transmit-only mode)
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value: 1
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enum/BR:
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bit_size: 3
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variants:
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- name: Div2
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description: f_PCLK / 2
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value: 0
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- name: Div4
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description: f_PCLK / 4
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value: 1
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- name: Div8
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description: f_PCLK / 8
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value: 2
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- name: Div16
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description: f_PCLK / 16
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value: 3
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- name: Div32
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description: f_PCLK / 32
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value: 4
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- name: Div64
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description: f_PCLK / 64
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value: 5
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- name: Div128
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description: f_PCLK / 128
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value: 6
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- name: Div256
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description: f_PCLK / 256
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value: 7
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enum/CHLEN:
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bit_size: 1
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variants:
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- name: SixteenBit
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description: 16-bit wide
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value: 0
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- name: ThirtyTwoBit
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description: 32-bit wide
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value: 1
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enum/CHSIDE:
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bit_size: 1
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variants:
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- name: Left
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description: Channel left has to be transmitted or has been received
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value: 0
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- name: Right
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description: Channel right has to be transmitted or has been received
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value: 1
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enum/CKPOL:
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bit_size: 1
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variants:
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- name: IdleLow
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description: I2S clock inactive state is low level
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value: 0
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- name: IdleHigh
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description: I2S clock inactive state is high level
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value: 1
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enum/CPHA:
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bit_size: 1
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variants:
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- name: FirstEdge
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description: The first clock transition is the first data capture edge
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value: 0
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- name: SecondEdge
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description: The second clock transition is the first data capture edge
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value: 1
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enum/CPOL:
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bit_size: 1
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variants:
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- name: IdleLow
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description: CK to 0 when idle
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value: 0
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- name: IdleHigh
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description: CK to 1 when idle
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value: 1
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enum/CRCL:
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bit_size: 1
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variants:
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- name: EightBit
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description: 8-bit CRC length
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value: 0
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- name: SixteenBit
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description: 16-bit CRC length
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value: 1
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enum/CRCNEXT:
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bit_size: 1
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variants:
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- name: TxBuffer
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description: Next transmit value is from Tx buffer
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value: 0
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- name: CRC
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description: Next transmit value is from Tx CRC register
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value: 1
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enum/DATLEN:
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bit_size: 2
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variants:
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- name: SixteenBit
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description: 16-bit data length
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value: 0
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- name: TwentyFourBit
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description: 24-bit data length
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value: 1
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- name: ThirtyTwoBit
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description: 32-bit data length
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value: 2
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enum/DS:
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bit_size: 4
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variants:
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- name: FourBit
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description: 4-bit
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value: 3
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- name: FiveBit
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description: 5-bit
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value: 4
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- name: SixBit
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description: 6-bit
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value: 5
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- name: SevenBit
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description: 7-bit
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value: 6
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- name: EightBit
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description: 8-bit
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value: 7
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- name: NineBit
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description: 9-bit
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value: 8
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- name: TenBit
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description: 10-bit
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value: 9
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- name: ElevenBit
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description: 11-bit
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value: 10
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- name: TwelveBit
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description: 12-bit
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value: 11
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- name: ThirteenBit
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description: 13-bit
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value: 12
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- name: FourteenBit
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description: 14-bit
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value: 13
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- name: FifteenBit
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description: 15-bit
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value: 14
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- name: SixteenBit
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description: 16-bit
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value: 15
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enum/FRF:
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bit_size: 1
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variants:
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- name: Motorola
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description: SPI Motorola mode
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value: 0
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- name: TI
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description: SPI TI mode
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value: 1
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enum/FRLVL:
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bit_size: 2
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variants:
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- name: Empty
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description: Rx FIFO Empty
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value: 0
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- name: Quarter
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description: Rx 1/4 FIFO
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value: 1
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- name: Half
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description: Rx 1/2 FIFO
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value: 2
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- name: Full
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description: Rx FIFO full
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value: 3
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enum/FRXTH:
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bit_size: 1
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variants:
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- name: Half
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description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
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value: 0
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- name: Quarter
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description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
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value: 1
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|
enum/FTLVL:
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bit_size: 2
|
|
variants:
|
|
- name: Empty
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|
description: Tx FIFO Empty
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|
value: 0
|
|
- name: Quarter
|
|
description: Tx 1/4 FIFO
|
|
value: 1
|
|
- name: Half
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|
description: Tx 1/2 FIFO
|
|
value: 2
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|
- name: Full
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|
description: Tx FIFO full
|
|
value: 3
|
|
enum/ISCFG:
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bit_size: 2
|
|
variants:
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|
- name: SlaveTx
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description: Slave - transmit
|
|
value: 0
|
|
- name: SlaveRx
|
|
description: Slave - receive
|
|
value: 1
|
|
- name: MasterTx
|
|
description: Master - transmit
|
|
value: 2
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|
- name: MasterRx
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|
description: Master - receive
|
|
value: 3
|
|
enum/ISMOD:
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|
bit_size: 1
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variants:
|
|
- name: SPIMode
|
|
description: SPI mode is selected
|
|
value: 0
|
|
- name: I2SMode
|
|
description: I2S mode is selected
|
|
value: 1
|
|
enum/ISSTD:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Philips
|
|
description: I2S Philips standard
|
|
value: 0
|
|
- name: MSB
|
|
description: MSB justified standard
|
|
value: 1
|
|
- name: LSB
|
|
description: LSB justified standard
|
|
value: 2
|
|
- name: PCM
|
|
description: PCM standard
|
|
value: 3
|
|
enum/LDMA_RX:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Even
|
|
description: Number of data to transfer for receive is even
|
|
value: 0
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|
- name: Odd
|
|
description: Number of data to transfer for receive is odd
|
|
value: 1
|
|
enum/LDMA_TX:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Even
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|
description: Number of data to transfer for transmit is even
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|
value: 0
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|
- name: Odd
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|
description: Number of data to transfer for transmit is odd
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|
value: 1
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|
enum/LSBFIRST:
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|
bit_size: 1
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|
variants:
|
|
- name: MSBFirst
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|
description: Data is transmitted/received with the MSB first
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|
value: 0
|
|
- name: LSBFirst
|
|
description: Data is transmitted/received with the LSB first
|
|
value: 1
|
|
enum/MSTR:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Slave
|
|
description: Slave configuration
|
|
value: 0
|
|
- name: Master
|
|
description: Master configuration
|
|
value: 1
|
|
enum/ODD:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Even
|
|
description: Real divider value is I2SDIV * 2
|
|
value: 0
|
|
- name: Odd
|
|
description: Real divider value is (I2SDIV * 2) + 1
|
|
value: 1
|
|
enum/PCMSYNC:
|
|
bit_size: 1
|
|
variants:
|
|
- name: Short
|
|
description: Short frame synchronisation
|
|
value: 0
|
|
- name: Long
|
|
description: Long frame synchronisation
|
|
value: 1
|
|
enum/RXONLY:
|
|
bit_size: 1
|
|
variants:
|
|
- name: FullDuplex
|
|
description: Full duplex (Transmit and receive)
|
|
value: 0
|
|
- name: OutputDisabled
|
|
description: Output disabled (Receive-only mode)
|
|
value: 1
|