523 lines
18 KiB
YAML
523 lines
18 KiB
YAML
---
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block/SYSCFG:
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description: register block
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items:
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- name: CFGR1
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description: configuration register 1
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byte_offset: 0
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fieldset: CFGR1
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- name: CFGR2
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description: configuration register 2
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byte_offset: 24
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fieldset: CFGR2
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- name: CFGR3
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description: configuration register 3
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byte_offset: 60
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fieldset: CFGR3
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- name: ITLINE0
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description: interrupt line 0 status register
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byte_offset: 128
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access: Read
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fieldset: ITLINE0
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- name: ITLINE2
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description: interrupt line 2 status register
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byte_offset: 136
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access: Read
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fieldset: ITLINE2
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- name: ITLINE3
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description: interrupt line 3 status register
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byte_offset: 140
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access: Read
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fieldset: ITLINE3
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- name: ITLINE4
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description: interrupt line 4 status register
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byte_offset: 144
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access: Read
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fieldset: ITLINE4
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- name: ITLINE5
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description: interrupt line 5 status register
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byte_offset: 148
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access: Read
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fieldset: ITLINE5
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- name: ITLINE6
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description: interrupt line 6 status register
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byte_offset: 152
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access: Read
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fieldset: ITLINE6
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- name: ITLINE7
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description: interrupt line 7 status register
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byte_offset: 156
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access: Read
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fieldset: ITLINE7
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- name: ITLINE9
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description: interrupt line 9 status register
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byte_offset: 164
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access: Read
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fieldset: ITLINE9
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- name: ITLINE10
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description: interrupt line 10 status register
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byte_offset: 168
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access: Read
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fieldset: ITLINE10
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- name: ITLINE11
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description: interrupt line 11 status register
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byte_offset: 172
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access: Read
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fieldset: ITLINE11
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- name: ITLINE12
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description: interrupt line 12 status register
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byte_offset: 176
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access: Read
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fieldset: ITLINE12
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- name: ITLINE13
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description: interrupt line 13 status register
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byte_offset: 180
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access: Read
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fieldset: ITLINE13
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- name: ITLINE14
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description: interrupt line 14 status register
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byte_offset: 184
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access: Read
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fieldset: ITLINE14
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- name: ITLINE16
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description: interrupt line 16 status register
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byte_offset: 192
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access: Read
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fieldset: ITLINE16
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- name: ITLINE19
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description: interrupt line 19 status register
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byte_offset: 204
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access: Read
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fieldset: ITLINE19
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- name: ITLINE21
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description: interrupt line 21 status register
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byte_offset: 212
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access: Read
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fieldset: ITLINE21
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- name: ITLINE22
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description: interrupt line 22 status register
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byte_offset: 216
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access: Read
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fieldset: ITLINE22
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- name: ITLINE23
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description: interrupt line 23 status register
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byte_offset: 220
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access: Read
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fieldset: ITLINE23
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- name: ITLINE25
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description: interrupt line 25 status register
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byte_offset: 228
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access: Read
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fieldset: ITLINE25
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- name: ITLINE27
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description: interrupt line 27 status register
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byte_offset: 236
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access: Read
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fieldset: ITLINE27
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- name: ITLINE28
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description: interrupt line 28 status register
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byte_offset: 240
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access: Read
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fieldset: ITLINE28
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fieldset/CFGR1:
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description: configuration register 1
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fields:
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- name: MEM_MODE
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description: Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details.
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bit_offset: 0
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bit_size: 2
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enum: MEM_MODE
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- name: PA11_RMP
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description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port."
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bit_offset: 3
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bit_size: 1
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- name: PA12_RMP
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description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port."
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bit_offset: 4
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bit_size: 1
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- name: IR_POL
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description: IR output polarity selection
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bit_offset: 5
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bit_size: 1
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- name: IR_MOD
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description: "IR Modulation Envelope signal selection\r This bitfield selects the signal for IR modulation envelope:"
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bit_offset: 6
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bit_size: 2
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enum: IR_MOD
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- name: I2C_PB6_FMP
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description: "Fast Mode Plus (FM+) enable for PB6\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB6 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 16
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bit_size: 1
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- name: I2C_PB7_FMP
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description: "Fast Mode Plus (FM+) enable for PB7\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB7 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 17
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bit_size: 1
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- name: I2C_PB8_FMP
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description: "Fast Mode Plus (FM+) enable for PB8\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB8 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 18
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bit_size: 1
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- name: I2C_PB9_FMP
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description: "Fast Mode Plus (FM+) enable for PB9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PB9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 19
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bit_size: 1
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- name: I2C1_FMP
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description: "Fast Mode Plus (FM+) enable for I2C1\r This bit is set and cleared by software. It enables I2C FM+ driving capability on I/O ports configured as I2C1 through GPIOx_AFR registers.\r With this bit in disable state, the I2C FM+ driving capability on I/O ports configured as I2C1 can be enabled through their corresponding I2Cx_FMP bit. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 20
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bit_size: 1
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- name: I2C_PA9_FMP
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description: "Fast Mode Plus (FM+) enable for PA9\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA9 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 22
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bit_size: 1
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- name: I2C_PA10_FMP
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description: "Fast Mode Plus (FM+) enable for PA10\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PA10 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 23
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bit_size: 1
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- name: I2C_PC14_FMP
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description: "Fast Mode Plus (FM+) enable for PC14\r This bit is set and cleared by software. It enables I2C FM+ driving capability on PC14 I/O port.\r With this bit in disable state, the I2C FM+ driving capability on this I/O port can be enabled through one of I2Cx_FMP bits. When I2C FM+ is enabled, the speed control is ignored."
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bit_offset: 24
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bit_size: 1
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fieldset/CFGR2:
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description: configuration register 2
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fields:
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- name: LOCKUP_LOCK
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description: "Cortex<Superscript><3E><Default <20> Font>-M0+ LOCKUP enable\r This bit is set by software and cleared by system reset. When set, it enables the connection of Cortex<Superscript><3E><Default <20> Font>-M0+ LOCKUP (HardFault) output to the TIM1/16/17 Break input."
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bit_offset: 0
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bit_size: 1
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fieldset/CFGR3:
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description: configuration register 3
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fields:
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- name: PINMUX0
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description: "Pin GPIO multiplexer 0\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r Pin F2 of WLCSP14 package GPIO assignment\r 1x: Reserved"
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bit_offset: 0
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bit_size: 2
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enum: PINMUX0
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- name: PINMUX1
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description: "Pin GPIO multiplexer 1\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
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bit_offset: 2
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bit_size: 2
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enum: PINMUX1
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- name: PINMUX2
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description: "Pin GPIO multiplexer 2\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved"
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bit_offset: 4
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bit_size: 2
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enum: PINMUX2
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- name: PINMUX3
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description: "Pin GPIO multiplexer 3\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
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bit_offset: 6
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bit_size: 2
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enum: PINMUX3
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- name: PINMUX4
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description: "Pin GPIO multiplexer 4\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved\r 1x: Reserved"
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bit_offset: 8
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bit_size: 2
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enum: PINMUX4
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- name: PINMUX5
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description: "Pin GPIO multiplexer 5\r This bit is set by software and cleared by system reset. It assigns a GPIO to a pin.\r 1x: Reserved"
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bit_offset: 10
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bit_size: 2
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enum: PINMUX5
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fieldset/ITLINE0:
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description: interrupt line 0 status register
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fields:
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- name: WWDG
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description: Window watchdog interrupt pending flag
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE10:
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description: interrupt line 10 status register
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fields:
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- name: DMA1_CH2
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description: DMA1 channel 2 interrupt request pending
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bit_offset: 0
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bit_size: 1
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- name: DMA1_CH3
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description: DMA1 channel 3 interrupt request pending
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bit_offset: 1
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bit_size: 1
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fieldset/ITLINE11:
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description: interrupt line 11 status register
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fields:
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- name: DMAMUX
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description: DMAMUX interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE12:
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description: interrupt line 12 status register
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fields:
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- name: ADC
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description: ADC interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE13:
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description: interrupt line 13 status register
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fields:
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- name: TIM1_CCU
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description: Timer 1 commutation interrupt request pending
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bit_offset: 0
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bit_size: 1
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- name: TIM1_TRG
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description: Timer 1 trigger interrupt request pending
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bit_offset: 1
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bit_size: 1
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- name: TIM1_UPD
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description: Timer 1 update interrupt request pending
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bit_offset: 2
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bit_size: 1
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- name: TIM1_BRK
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description: Timer 1 break interrupt request pending
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bit_offset: 3
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bit_size: 1
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fieldset/ITLINE14:
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description: interrupt line 14 status register
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fields:
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- name: TIM1_CC
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description: Timer 1 capture compare interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE16:
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description: interrupt line 16 status register
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fields:
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- name: TIM3
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description: Timer 3 interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE19:
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description: interrupt line 19 status register
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fields:
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- name: TIM14
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description: Timer 14 interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE2:
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description: interrupt line 2 status register
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fields:
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- name: RTC
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description: RTC interrupt request pending (EXTI line 19)
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bit_offset: 1
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bit_size: 1
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fieldset/ITLINE21:
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description: interrupt line 21 status register
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fields:
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- name: TIM16
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description: Timer 16 interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE22:
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description: interrupt line 22 status register
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fields:
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- name: TIM17
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description: Timer 17 interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE23:
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description: interrupt line 23 status register
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fields:
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- name: I2C1
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description: "I2C1 interrupt request pending, combined with EXTI line 23"
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE25:
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description: interrupt line 25 status register
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fields:
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- name: SPI1
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description: SPI1 interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE27:
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description: interrupt line 27 status register
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fields:
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- name: USART1
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description: "USART1 interrupt request pending, combined with EXTI line 25"
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE28:
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description: interrupt line 28 status register
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fields:
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- name: USART2
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description: USART2 interrupt request pending (EXTI line 26)
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE3:
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description: interrupt line 3 status register
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fields:
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- name: FLASH_ITF
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description: Flash interface interrupt request pending
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bit_offset: 1
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bit_size: 1
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fieldset/ITLINE4:
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description: interrupt line 4 status register
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fields:
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- name: RCC
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description: Reset and clock control interrupt request pending
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bit_offset: 0
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bit_size: 1
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fieldset/ITLINE5:
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description: interrupt line 5 status register
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fields:
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- name: EXTI
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description: EXTI
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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fieldset/ITLINE6:
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description: interrupt line 6 status register
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fields:
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- name: EXTI
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description: EXTI
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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fieldset/ITLINE7:
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description: interrupt line 7 status register
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fields:
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- name: EXTI
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description: EXTI
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bit_offset: 0
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bit_size: 1
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array:
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len: 12
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stride: 1
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fieldset/ITLINE9:
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description: interrupt line 9 status register
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fields:
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- name: DMA1_CH1
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description: DMA1 channel 1interrupt request pending
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bit_offset: 0
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bit_size: 1
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enum/IR_MOD:
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bit_size: 2
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variants:
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- name: TIM16
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description: TIM16
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value: 0
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- name: USART1
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description: USART1
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value: 1
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- name: USART2
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description: USART2
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value: 2
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enum/MEM_MODE:
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bit_size: 2
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variants:
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- name: MAIN_FLASH
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description: Main Flash memory mapped at address 0
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value: 0
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- name: SYSTEM_FLASH
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description: System Flash memory mapped at address 0
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value: 1
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- name: MAIN_FLASH_ALT
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description: Main Flash memory mapped at address 0 (alternate encoding)
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value: 2
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- name: SRAM
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description: Embedded SRAM mapped at address 0
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value: 3
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enum/PINMUX0:
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bit_size: 2
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variants:
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- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
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description: PB7
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value: 0
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- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
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description: PA1
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value: 0
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- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_1
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description: PC14
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value: 1
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- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_F2
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description: PA2
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value: 1
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enum/PINMUX1:
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bit_size: 2
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variants:
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- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
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description: PF2
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value: 0
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- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
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description: PF2
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value: 0
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- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
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description: PA0
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value: 1
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- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G3
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description: PA0
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value: 1
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- name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
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description: PA1
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value: 2
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- name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_4
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description: PA2
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value: 3
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enum/PINMUX2:
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bit_size: 2
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variants:
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- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
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description: PA8
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value: 0
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- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
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description: PA8
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value: 0
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- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_5
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description: PA11
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value: 1
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- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J1
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description: PA11
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value: 1
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enum/PINMUX3:
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bit_size: 2
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variants:
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- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
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description: PA14
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value: 0
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- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
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description: PA5
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value: 0
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- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
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description: PB6
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value: 1
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- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_H2
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description: PA6
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value: 1
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- name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_SO8_PIN_8
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description: PC15
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value: 2
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enum/PINMUX4:
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bit_size: 2
|
||
variants:
|
||
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
|
||
description: PA7
|
||
value: 0
|
||
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
|
||
description: PA7
|
||
value: 0
|
||
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_E2
|
||
description: PA12
|
||
value: 1
|
||
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_G1
|
||
description: PA12
|
||
value: 1
|
||
enum/PINMUX5:
|
||
bit_size: 2
|
||
variants:
|
||
- name: B_0x0_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
|
||
description: PA3
|
||
value: 0
|
||
- name: B_0x0_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
|
||
description: PA3
|
||
value: 0
|
||
- name: B_0x1_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
|
||
description: PA4
|
||
value: 1
|
||
- name: B_0x1_STM32C031X___GPIO_ASSIGNED_TO_WLCSP14_PIN_J3
|
||
description: PA4
|
||
value: 1
|
||
- name: B_0x2_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
|
||
description: PA5
|
||
value: 2
|
||
- name: B_0x3_STM32C011X___GPIO_ASSIGNED_TO_WLCSP12_PIN_F1
|
||
description: PA6
|
||
value: 3
|