1481 lines
38 KiB
YAML
1481 lines
38 KiB
YAML
---
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block/RCC:
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description: Reset and clock control
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items:
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- name: CR
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description: Clock control register
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byte_offset: 0
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fieldset: CR
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- name: ICSCR
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description: Internal clock sources calibration register
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byte_offset: 4
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fieldset: ICSCR
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- name: CFGR
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description: Clock configuration register
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byte_offset: 8
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fieldset: CFGR
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- name: PLLCFGR
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description: PLL configuration register
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byte_offset: 12
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fieldset: PLLCFGR
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- name: CIER
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description: Clock interrupt enable register
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byte_offset: 24
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fieldset: CIER
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- name: CIFR
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description: Clock interrupt flag register
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byte_offset: 28
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access: Read
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fieldset: CIFR
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- name: CICR
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description: Clock interrupt clear register
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byte_offset: 32
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access: Write
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fieldset: CICR
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- name: AHB1RSTR
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description: AHB1 peripheral reset register
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byte_offset: 40
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fieldset: AHB1RSTR
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- name: AHB2RSTR
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description: AHB2 peripheral reset register
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byte_offset: 44
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fieldset: AHB2RSTR
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- name: AHB3RSTR
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description: AHB3 peripheral reset register
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byte_offset: 48
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fieldset: AHB3RSTR
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- name: APB1RSTR1
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description: APB1 peripheral reset register 1
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byte_offset: 56
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fieldset: APB1RSTR1
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- name: APB1RSTR2
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description: APB1 peripheral reset register 2
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byte_offset: 60
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fieldset: APB1RSTR2
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- name: APB2RSTR
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description: APB2 peripheral reset register
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byte_offset: 64
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fieldset: APB2RSTR
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- name: AHB1ENR
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description: AHB1 peripheral clock enable register
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byte_offset: 72
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fieldset: AHB1ENR
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- name: AHB2ENR
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description: AHB2 peripheral clock enable register
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byte_offset: 76
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fieldset: AHB2ENR
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- name: AHB3ENR
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description: AHB3 peripheral clock enable register
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byte_offset: 80
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fieldset: AHB3ENR
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- name: APB1ENR1
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description: APB1ENR1
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byte_offset: 88
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fieldset: APB1ENR1
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- name: APB1ENR2
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description: APB1 peripheral clock enable register 2
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byte_offset: 92
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fieldset: APB1ENR2
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- name: APB2ENR
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description: APB2ENR
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byte_offset: 96
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fieldset: APB2ENR
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- name: AHB1SMENR
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description: AHB1 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 104
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fieldset: AHB1SMENR
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- name: AHB2SMENR
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description: AHB2 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 108
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fieldset: AHB2SMENR
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- name: AHB3SMENR
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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byte_offset: 112
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fieldset: AHB3SMENR
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- name: APB1SMENR1
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description: APB1SMENR1
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byte_offset: 120
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fieldset: APB1SMENR1
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- name: APB1SMENR2
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description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
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byte_offset: 124
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fieldset: APB1SMENR2
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- name: APB2SMENR
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description: APB2SMENR
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byte_offset: 128
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fieldset: APB2SMENR
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- name: CCIPR
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description: CCIPR
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byte_offset: 136
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fieldset: CCIPR
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- name: BDCR
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description: BDCR
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byte_offset: 144
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fieldset: BDCR
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- name: CSR
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description: CSR
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byte_offset: 148
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fieldset: CSR
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- name: CRRCR
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description: Clock recovery RC register
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byte_offset: 152
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fieldset: CRRCR
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- name: CCIPR2
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description: Peripherals independent clock configuration register
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byte_offset: 156
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fieldset: CCIPR2
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fieldset/AHB1ENR:
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description: AHB1 peripheral clock enable register
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fields:
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- name: DMA1EN
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description: DMA1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: DMA2EN
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description: DMA2 clock enable
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1EN
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description: DMAMUX clock enable
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bit_offset: 2
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bit_size: 1
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- name: CORDICEN
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description: CORDIC clock enable
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bit_offset: 3
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bit_size: 1
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- name: FMACEN
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description: FMAC clock enable
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bit_offset: 4
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bit_size: 1
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- name: FLASHEN
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description: Flash memory interface clock enable
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bit_offset: 8
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bit_size: 1
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- name: CRCEN
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description: CRC clock enable
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bit_offset: 12
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bit_size: 1
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fieldset/AHB1RSTR:
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description: AHB1 peripheral reset register
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fields:
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- name: DMA1RST
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description: DMA1 reset
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bit_offset: 0
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bit_size: 1
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- name: DMA2RST
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description: DMA2 reset
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1RST
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description: DMAMUX1RST
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bit_offset: 2
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bit_size: 1
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- name: CORDICRST
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description: CORDIC reset
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bit_offset: 3
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bit_size: 1
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- name: FMACRST
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description: FMAC reset
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bit_offset: 4
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bit_size: 1
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- name: FLASHRST
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description: Flash memory interface reset
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bit_offset: 8
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bit_size: 1
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- name: CRCRST
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description: CRC reset
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bit_offset: 12
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bit_size: 1
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fieldset/AHB1SMENR:
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description: AHB1 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: DMA1SMEN
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description: DMA1 clocks enable during Sleep and Stop modes
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bit_offset: 0
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bit_size: 1
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- name: DMA2SMEN
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description: DMA2 clocks enable during Sleep and Stop modes
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bit_offset: 1
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bit_size: 1
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- name: DMAMUX1SMEN
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description: DMAMUX clock enable during Sleep and Stop modes
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bit_offset: 2
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bit_size: 1
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- name: CORDICSMEN
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description: CORDIC clock enable during sleep mode
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bit_offset: 3
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bit_size: 1
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- name: FMACSMEN
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description: FMACSM clock enable
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bit_offset: 4
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bit_size: 1
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- name: FLASHSMEN
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description: Flash memory interface clocks enable during Sleep and Stop modes
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bit_offset: 8
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bit_size: 1
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- name: SRAM1SMEN
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description: SRAM1 interface clocks enable during Sleep and Stop modes
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bit_offset: 9
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bit_size: 1
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- name: CRCSMEN
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description: CRCSMEN
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bit_offset: 12
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bit_size: 1
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fieldset/AHB2ENR:
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description: AHB2 peripheral clock enable register
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fields:
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- name: GPIOAEN
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description: IO port A clock enable
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bit_offset: 0
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bit_size: 1
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- name: GPIOBEN
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description: IO port B clock enable
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bit_offset: 1
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bit_size: 1
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- name: GPIOCEN
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description: IO port C clock enable
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bit_offset: 2
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bit_size: 1
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- name: GPIODEN
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description: IO port D clock enable
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bit_offset: 3
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bit_size: 1
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- name: GPIOEEN
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description: IO port E clock enable
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bit_offset: 4
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bit_size: 1
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- name: GPIOFEN
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description: IO port F clock enable
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bit_offset: 5
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bit_size: 1
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- name: GPIOGEN
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description: IO port G clock enable
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bit_offset: 6
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bit_size: 1
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- name: ADC12EN
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description: ADC clock enable
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bit_offset: 13
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bit_size: 1
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- name: ADC345EN
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description: DCMI clock enable
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bit_offset: 14
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bit_size: 1
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- name: DAC1EN
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description: AES accelerator clock enable
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bit_offset: 16
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bit_size: 1
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- name: DAC2EN
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description: HASH clock enable
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bit_offset: 17
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bit_size: 1
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- name: DAC3EN
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description: Random Number Generator clock enable
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bit_offset: 18
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bit_size: 1
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- name: DAC4EN
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description: DAC4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: AESEN
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description: AES clock enable
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bit_offset: 24
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bit_size: 1
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- name: RNGEN
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description: Random Number Generator clock enable
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bit_offset: 26
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bit_size: 1
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fieldset/AHB2RSTR:
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description: AHB2 peripheral reset register
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fields:
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- name: GPIOARST
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description: IO port A reset
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bit_offset: 0
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bit_size: 1
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- name: GPIOBRST
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description: IO port B reset
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bit_offset: 1
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bit_size: 1
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- name: GPIOCRST
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description: IO port C reset
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bit_offset: 2
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bit_size: 1
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- name: GPIODRST
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description: IO port D reset
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bit_offset: 3
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bit_size: 1
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- name: GPIOERST
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description: IO port E reset
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bit_offset: 4
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bit_size: 1
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- name: GPIOFRST
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description: IO port F reset
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bit_offset: 5
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bit_size: 1
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- name: GPIOGRST
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description: IO port G reset
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bit_offset: 6
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bit_size: 1
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- name: ADC12RST
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description: ADC reset
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bit_offset: 13
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bit_size: 1
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- name: ADC345RST
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description: SAR ADC345 interface reset
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bit_offset: 14
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bit_size: 1
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- name: DAC1RST
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description: DAC1 interface reset
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bit_offset: 16
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bit_size: 1
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- name: DAC2RST
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description: DAC2 interface reset
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bit_offset: 17
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bit_size: 1
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- name: DAC3RST
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description: DAC3 interface reset
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bit_offset: 18
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bit_size: 1
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- name: DAC4RST
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description: DAC4 interface reset
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bit_offset: 19
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bit_size: 1
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- name: AESRST
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description: Cryptography module reset
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bit_offset: 24
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bit_size: 1
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- name: RNGRST
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description: Random Number Generator module reset
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bit_offset: 26
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bit_size: 1
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fieldset/AHB2SMENR:
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description: AHB2 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: GPIOASMEN
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description: IO port A clocks enable during Sleep and Stop modes
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bit_offset: 0
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bit_size: 1
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- name: GPIOBSMEN
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description: IO port B clocks enable during Sleep and Stop modes
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bit_offset: 1
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bit_size: 1
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- name: GPIOCSMEN
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description: IO port C clocks enable during Sleep and Stop modes
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bit_offset: 2
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bit_size: 1
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- name: GPIODSMEN
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description: IO port D clocks enable during Sleep and Stop modes
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bit_offset: 3
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bit_size: 1
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- name: GPIOESMEN
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description: IO port E clocks enable during Sleep and Stop modes
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bit_offset: 4
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bit_size: 1
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- name: GPIOFSMEN
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description: IO port F clocks enable during Sleep and Stop modes
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bit_offset: 5
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bit_size: 1
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- name: GPIOGSMEN
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description: IO port G clocks enable during Sleep and Stop modes
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bit_offset: 6
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bit_size: 1
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- name: CCMSRAMSMEN
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description: CCM SRAM interface clocks enable during Sleep and Stop modes
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bit_offset: 9
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bit_size: 1
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- name: SRAM2SMEN
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description: SRAM2 interface clocks enable during Sleep and Stop modes
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bit_offset: 10
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bit_size: 1
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- name: ADC12SMEN
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description: ADC clocks enable during Sleep and Stop modes
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bit_offset: 13
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bit_size: 1
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- name: ADC345SMEN
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description: DCMI clock enable during Sleep and Stop modes
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bit_offset: 14
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bit_size: 1
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- name: DAC1SMEN
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description: AES accelerator clocks enable during Sleep and Stop modes
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bit_offset: 16
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bit_size: 1
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- name: DAC2SMEN
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description: HASH clock enable during Sleep and Stop modes
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bit_offset: 17
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bit_size: 1
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- name: DAC3SMEN
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description: DAC3 clock enable during sleep mode
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bit_offset: 18
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bit_size: 1
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- name: DAC4SMEN
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description: DAC4 clock enable during sleep mode
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bit_offset: 19
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bit_size: 1
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- name: AESMEN
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description: Cryptography clock enable during sleep mode
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bit_offset: 24
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bit_size: 1
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- name: RNGEN
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description: Random Number Generator clock enable during sleep mode
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bit_offset: 26
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bit_size: 1
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fieldset/AHB3ENR:
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description: AHB3 peripheral clock enable register
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fields:
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- name: FMCEN
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description: Flexible memory controller clock enable
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bit_offset: 0
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bit_size: 1
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- name: QUADSPIEN
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description: QUADSPI memory interface clock enable
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bit_offset: 8
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bit_size: 1
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fieldset/AHB3RSTR:
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description: AHB3 peripheral reset register
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fields:
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- name: FMCRST
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description: Flexible memory controller reset
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bit_offset: 0
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bit_size: 1
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- name: QSPIRST
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description: Quad SPI 1 module reset
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bit_offset: 8
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bit_size: 1
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fieldset/AHB3SMENR:
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description: AHB3 peripheral clocks enable in Sleep and Stop modes register
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fields:
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- name: FMCSMEN
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description: Flexible memory controller clocks enable during Sleep and Stop modes
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bit_offset: 0
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bit_size: 1
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- name: QSPISMEN
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description: QUADSPI memory interface clock enable during Sleep and Stop modes
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bit_offset: 8
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bit_size: 1
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fieldset/APB1ENR1:
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description: APB1ENR1
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fields:
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- name: TIM2EN
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description: TIM2 timer clock enable
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bit_offset: 0
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bit_size: 1
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- name: TIM3EN
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description: TIM3 timer clock enable
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bit_offset: 1
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bit_size: 1
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- name: TIM4EN
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description: TIM4 timer clock enable
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bit_offset: 2
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bit_size: 1
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- name: TIM5EN
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description: TIM5 timer clock enable
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bit_offset: 3
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bit_size: 1
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- name: TIM6EN
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description: TIM6 timer clock enable
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bit_offset: 4
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bit_size: 1
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- name: TIM7EN
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description: TIM7 timer clock enable
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bit_offset: 5
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bit_size: 1
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- name: CRSEN
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description: CRSclock enable
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bit_offset: 8
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bit_size: 1
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- name: RTCAPBEN
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description: RTC APB clock enable
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bit_offset: 10
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bit_size: 1
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- name: WWDGEN
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description: Window watchdog clock enable
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bit_offset: 11
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bit_size: 1
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- name: SPI2EN
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description: SPI2 clock enable
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bit_offset: 14
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bit_size: 1
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- name: SPI3EN
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description: SPI3 clock enable
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bit_offset: 15
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bit_size: 1
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- name: USART2EN
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description: USART2 clock enable
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bit_offset: 17
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bit_size: 1
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- name: USART3EN
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description: USART3 clock enable
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bit_offset: 18
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bit_size: 1
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- name: UART4EN
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description: UART4 clock enable
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bit_offset: 19
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bit_size: 1
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- name: UART5EN
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description: UART5 clock enable
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bit_offset: 20
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bit_size: 1
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- name: I2C1EN
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description: I2C1 clock enable
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bit_offset: 21
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bit_size: 1
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- name: I2C2EN
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description: I2C2 clock enable
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bit_offset: 22
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bit_size: 1
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- name: USBEN
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description: USB device clock enable
|
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bit_offset: 23
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bit_size: 1
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- name: FDCANEN
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description: FDCAN clock enable
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bit_offset: 25
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bit_size: 1
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- name: PWREN
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description: Power interface clock enable
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bit_offset: 28
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bit_size: 1
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- name: I2C3EN
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description: I2C3 clock enable
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bit_offset: 30
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bit_size: 1
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- name: LPTIM1EN
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description: Low power timer 1 clock enable
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bit_offset: 31
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bit_size: 1
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fieldset/APB1ENR2:
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description: APB1 peripheral clock enable register 2
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fields:
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- name: LPUART1EN
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description: Low power UART 1 clock enable
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bit_offset: 0
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bit_size: 1
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- name: I2C4EN
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description: I2C4 clock enable
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bit_offset: 1
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bit_size: 1
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- name: UCPD1EN
|
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description: UCPD1 clock enable
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bit_offset: 8
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bit_size: 1
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fieldset/APB1RSTR1:
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description: APB1 peripheral reset register 1
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fields:
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- name: TIM2RST
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description: TIM2 timer reset
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bit_offset: 0
|
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bit_size: 1
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- name: TIM3RST
|
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description: TIM3 timer reset
|
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bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4RST
|
|
description: TIM3 timer reset
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5RST
|
|
description: TIM5 timer reset
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6RST
|
|
description: TIM6 timer reset
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7RST
|
|
description: TIM7 timer reset
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CRSRST
|
|
description: Clock recovery system reset
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: SPI2RST
|
|
description: SPI2 reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI3RST
|
|
description: SPI3 reset
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: USART2RST
|
|
description: USART2 reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3RST
|
|
description: USART3 reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4RST
|
|
description: UART4 reset
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5RST
|
|
description: UART5 reset
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1RST
|
|
description: I2C1 reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2RST
|
|
description: I2C2 reset
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: USBRST
|
|
description: USBD reset
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: FDCANRST
|
|
description: FDCAN reset
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PWRRST
|
|
description: Power interface reset
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: I2C3RST
|
|
description: I2C3 interface reset
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPTIM1RST
|
|
description: Low Power Timer 1 reset
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1RSTR2:
|
|
description: APB1 peripheral reset register 2
|
|
fields:
|
|
- name: LPUART1RST
|
|
description: Low-power UART 1 reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: I2C4RST
|
|
description: I2C4 reset
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: UCPD1RST
|
|
description: UCPD1 reset
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/APB1SMENR1:
|
|
description: APB1SMENR1
|
|
fields:
|
|
- name: TIM2SMEN
|
|
description: TIM2 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM3SMEN
|
|
description: TIM3 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: TIM4SMEN
|
|
description: TIM4 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: TIM5SMEN
|
|
description: TIM5 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: TIM6SMEN
|
|
description: TIM6 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: TIM7SMEN
|
|
description: TIM7 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CRSSMEN
|
|
description: CRS clock enable during sleep mode
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: RTCAPBSMEN
|
|
description: RTC APB clock enable during Sleep and Stop modes
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: WWDGSMEN
|
|
description: Window watchdog clocks enable during Sleep and Stop modes
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI2SMEN
|
|
description: SPI2 clocks enable during Sleep and Stop modes
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SP3SMEN
|
|
description: SPI3 clocks enable during Sleep and Stop modes
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: USART2SMEN
|
|
description: USART2 clocks enable during Sleep and Stop modes
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: USART3SMEN
|
|
description: USART3 clocks enable during Sleep and Stop modes
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: UART4SMEN
|
|
description: UART4 clocks enable during Sleep and Stop modes
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: UART5SMEN
|
|
description: UART5 clocks enable during Sleep and Stop modes
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: I2C1SMEN
|
|
description: I2C1 clocks enable during Sleep and Stop modes
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: I2C2SMEN
|
|
description: I2C2 clocks enable during Sleep and Stop modes
|
|
bit_offset: 22
|
|
bit_size: 1
|
|
- name: USBSMEN
|
|
description: USB device clocks enable during Sleep and Stop modes
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: FDCANSMEN
|
|
description: FDCAN clock enable during sleep mode
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PWRSMEN
|
|
description: Power interface clocks enable during Sleep and Stop modes
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: I2C3SMEN
|
|
description: I2C3 clocks enable during Sleep and Stop modes
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPTIM1SMEN
|
|
description: Low Power Timer1 clock enable during sleep mode
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/APB1SMENR2:
|
|
description: APB1 peripheral clocks enable in Sleep and Stop modes register 2
|
|
fields:
|
|
- name: LPUART1SMEN
|
|
description: Low power UART 1 clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: I2C4SMEN
|
|
description: I2C4 clocks enable during Sleep and Stop modes
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: UCPD1SMEN
|
|
description: UCPD1 clocks enable during Sleep and Stop modes
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
fieldset/APB2ENR:
|
|
description: APB2ENR
|
|
fields:
|
|
- name: SYSCFGEN
|
|
description: SYSCFG clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM1EN
|
|
description: TIM1 timer clock enable
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1EN
|
|
description: SPI1 clock enable
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TIM8EN
|
|
description: TIM8 timer clock enable
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: USART1EN
|
|
description: USART1clock enable
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI4EN
|
|
description: SPI 4 clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: TIM15EN
|
|
description: TIM15 timer clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16EN
|
|
description: TIM16 timer clock enable
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17EN
|
|
description: TIM17 timer clock enable
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TIM20EN
|
|
description: Timer 20 clock enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1EN
|
|
description: SAI1 clock enable
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: HRTIM1EN
|
|
description: HRTIMER clock enable
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
fieldset/APB2RSTR:
|
|
description: APB2 peripheral reset register
|
|
fields:
|
|
- name: SYSCFGRST
|
|
description: System configuration (SYSCFG) reset
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM1RST
|
|
description: TIM1 timer reset
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1RST
|
|
description: SPI1 reset
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TIM8RST
|
|
description: TIM8 timer reset
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: USART1RST
|
|
description: USART1 reset
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI4RST
|
|
description: SPI 4 reset
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: TIM15RST
|
|
description: TIM15 timer reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16RST
|
|
description: TIM16 timer reset
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17RST
|
|
description: TIM17 timer reset
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TIM20RST
|
|
description: Timer 20 reset
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1RST
|
|
description: Serial audio interface 1 (SAI1) reset
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: HRTIM1RST
|
|
description: HRTIMER reset
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
fieldset/APB2SMENR:
|
|
description: APB2SMENR
|
|
fields:
|
|
- name: SYSCFGSMEN
|
|
description: SYSCFG clocks enable during Sleep and Stop modes
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: TIM1SMEN
|
|
description: TIM1 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 11
|
|
bit_size: 1
|
|
- name: SPI1SMEN
|
|
description: SPI1 clocks enable during Sleep and Stop modes
|
|
bit_offset: 12
|
|
bit_size: 1
|
|
- name: TIM8SMEN
|
|
description: TIM8 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 13
|
|
bit_size: 1
|
|
- name: USART1SMEN
|
|
description: USART1clocks enable during Sleep and Stop modes
|
|
bit_offset: 14
|
|
bit_size: 1
|
|
- name: SPI4SMEN
|
|
description: SPI4 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: TIM15SMEN
|
|
description: TIM15 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: TIM16SMEN
|
|
description: TIM16 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: TIM17SMEN
|
|
description: TIM17 timer clocks enable during Sleep and Stop modes
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: TIM20SMEN
|
|
description: Timer 20clock enable during sleep mode
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: SAI1SMEN
|
|
description: SAI1 clock enable during sleep mode
|
|
bit_offset: 21
|
|
bit_size: 1
|
|
- name: HRTIM1SMEN
|
|
description: HRTIMER clock enable during sleep mode
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
fieldset/BDCR:
|
|
description: BDCR
|
|
fields:
|
|
- name: LSEON
|
|
description: LSE oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDY
|
|
description: LSE oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: LSEBYP
|
|
description: LSE oscillator bypass
|
|
bit_offset: 2
|
|
bit_size: 1
|
|
- name: LSEDRV
|
|
description: SE oscillator drive capability
|
|
bit_offset: 3
|
|
bit_size: 2
|
|
enum: LSEDRV
|
|
- name: LSECSSON
|
|
description: LSECSSON
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSD
|
|
description: LSECSSD
|
|
bit_offset: 6
|
|
bit_size: 1
|
|
- name: RTCSEL
|
|
description: RTC clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
enum: RTCSEL
|
|
- name: RTCEN
|
|
description: RTC clock enable
|
|
bit_offset: 15
|
|
bit_size: 1
|
|
- name: BDRST
|
|
description: RTC domain software reset
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: LSCOEN
|
|
description: Low speed clock output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: LSCOSEL
|
|
description: Low speed clock output selection
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CCIPR:
|
|
description: CCIPR
|
|
fields:
|
|
- name: USART1SEL
|
|
description: USART1 clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: USART2SEL
|
|
description: USART2 clock source selection
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
- name: USART3SEL
|
|
description: USART3 clock source selection
|
|
bit_offset: 4
|
|
bit_size: 2
|
|
- name: UART4SEL
|
|
description: UART4 clock source selection
|
|
bit_offset: 6
|
|
bit_size: 2
|
|
- name: UART5SEL
|
|
description: UART5 clock source selection
|
|
bit_offset: 8
|
|
bit_size: 2
|
|
- name: LPUART1SEL
|
|
description: LPUART1 clock source selection
|
|
bit_offset: 10
|
|
bit_size: 2
|
|
- name: I2C1SEL
|
|
description: I2C1 clock source selection
|
|
bit_offset: 12
|
|
bit_size: 2
|
|
- name: I2C2SEL
|
|
description: I2C2 clock source selection
|
|
bit_offset: 14
|
|
bit_size: 2
|
|
- name: I2C3SEL
|
|
description: I2C3 clock source selection
|
|
bit_offset: 16
|
|
bit_size: 2
|
|
- name: LPTIM1SEL
|
|
description: Low power timer 1 clock source selection
|
|
bit_offset: 18
|
|
bit_size: 2
|
|
- name: SAI1SEL
|
|
description: Low power timer 2 clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
- name: I2S23SEL
|
|
description: SAI1 clock source selection
|
|
bit_offset: 22
|
|
bit_size: 2
|
|
- name: FDCANSEL
|
|
description: SAI2 clock source selection
|
|
bit_offset: 24
|
|
bit_size: 2
|
|
- name: CLK48SEL
|
|
description: 48 MHz clock source selection
|
|
bit_offset: 26
|
|
bit_size: 2
|
|
- name: ADC12SEL
|
|
description: ADCs clock source selection
|
|
bit_offset: 28
|
|
bit_size: 2
|
|
- name: ADC345SEL
|
|
description: ADC3/4/5 clock source selection
|
|
bit_offset: 30
|
|
bit_size: 2
|
|
fieldset/CCIPR2:
|
|
description: Peripherals independent clock configuration register
|
|
fields:
|
|
- name: I2C4SEL
|
|
description: I2C4 clock source selection
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
- name: QSPISEL
|
|
description: Octospi clock source selection
|
|
bit_offset: 20
|
|
bit_size: 2
|
|
fieldset/CFGR:
|
|
description: Clock configuration register
|
|
fields:
|
|
- name: SW
|
|
description: System clock switch
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: SWS
|
|
description: System clock switch status
|
|
bit_offset: 2
|
|
bit_size: 2
|
|
enum: SW
|
|
- name: HPRE
|
|
description: AHB prescaler
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
enum: HPRE
|
|
- name: PPRE1
|
|
description: PB low-speed prescaler (APB1)
|
|
bit_offset: 8
|
|
bit_size: 3
|
|
enum: PPRE
|
|
- name: PPRE2
|
|
description: APB high-speed prescaler (APB2)
|
|
bit_offset: 11
|
|
bit_size: 3
|
|
- name: MCOSEL
|
|
description: Microcontroller clock output
|
|
bit_offset: 24
|
|
bit_size: 4
|
|
enum: MCOSEL
|
|
- name: MCOPRE
|
|
description: Microcontroller clock output prescaler
|
|
bit_offset: 28
|
|
bit_size: 3
|
|
enum: MCOPRE
|
|
fieldset/CICR:
|
|
description: Clock interrupt clear register
|
|
fields:
|
|
- name: LSIRDYC
|
|
description: LSI ready interrupt clear
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYC
|
|
description: LSE ready interrupt clear
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYC
|
|
description: HSI ready interrupt clear
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYC
|
|
description: HSE ready interrupt clear
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYC
|
|
description: PLL ready interrupt clear
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSC
|
|
description: Clock security system interrupt clear
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSC
|
|
description: LSE Clock security system interrupt clear
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYC
|
|
description: HSI48 oscillator ready interrupt clear
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CIER:
|
|
description: Clock interrupt enable register
|
|
fields:
|
|
- name: LSIRDYIE
|
|
description: LSI ready interrupt enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYIE
|
|
description: LSE ready interrupt enable
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYIE
|
|
description: HSI ready interrupt enable
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYIE
|
|
description: HSE ready interrupt enable
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYIE
|
|
description: PLL ready interrupt enable
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: LSECSSIE
|
|
description: LSE clock security system interrupt enable
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYIE
|
|
description: HSI48 ready interrupt enable
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CIFR:
|
|
description: Clock interrupt flag register
|
|
fields:
|
|
- name: LSIRDYF
|
|
description: LSI ready interrupt flag
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSERDYF
|
|
description: LSE ready interrupt flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSIRDYF
|
|
description: HSI ready interrupt flag
|
|
bit_offset: 3
|
|
bit_size: 1
|
|
- name: HSERDYF
|
|
description: HSE ready interrupt flag
|
|
bit_offset: 4
|
|
bit_size: 1
|
|
- name: PLLRDYF
|
|
description: PLL ready interrupt flag
|
|
bit_offset: 5
|
|
bit_size: 1
|
|
- name: CSSF
|
|
description: Clock security system interrupt flag
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: LSECSSF
|
|
description: LSE Clock security system interrupt flag
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSI48RDYF
|
|
description: HSI48 ready interrupt flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
fieldset/CR:
|
|
description: Clock control register
|
|
fields:
|
|
- name: HSION
|
|
description: HSI clock enable
|
|
bit_offset: 8
|
|
bit_size: 1
|
|
- name: HSIKERON
|
|
description: HSI always enable for peripheral kernels
|
|
bit_offset: 9
|
|
bit_size: 1
|
|
- name: HSIRDY
|
|
description: HSI clock ready flag
|
|
bit_offset: 10
|
|
bit_size: 1
|
|
- name: HSEON
|
|
description: HSE clock enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: HSERDY
|
|
description: HSE clock ready flag
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: HSEBYP
|
|
description: HSE crystal oscillator bypass
|
|
bit_offset: 18
|
|
bit_size: 1
|
|
- name: CSSON
|
|
description: Clock security system enable
|
|
bit_offset: 19
|
|
bit_size: 1
|
|
- name: PLLON
|
|
description: Main PLL enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLRDY
|
|
description: Main PLL clock ready flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
fieldset/CRRCR:
|
|
description: Clock recovery RC register
|
|
fields:
|
|
- name: HSI48ON
|
|
description: HSI48 clock enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: HSI48RDY
|
|
description: HSI48 clock ready flag
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: HSI48CAL
|
|
description: HSI48 clock calibration
|
|
bit_offset: 7
|
|
bit_size: 9
|
|
fieldset/CSR:
|
|
description: CSR
|
|
fields:
|
|
- name: LSION
|
|
description: LSI oscillator enable
|
|
bit_offset: 0
|
|
bit_size: 1
|
|
- name: LSIRDY
|
|
description: LSI oscillator ready
|
|
bit_offset: 1
|
|
bit_size: 1
|
|
- name: RMVF
|
|
description: Remove reset flag
|
|
bit_offset: 23
|
|
bit_size: 1
|
|
- name: OBLRSTF
|
|
description: Option byte loader reset flag
|
|
bit_offset: 25
|
|
bit_size: 1
|
|
- name: PINRSTF
|
|
description: Pad reset flag
|
|
bit_offset: 26
|
|
bit_size: 1
|
|
- name: BORRSTF
|
|
description: BOR flag
|
|
bit_offset: 27
|
|
bit_size: 1
|
|
- name: SFTRSTF
|
|
description: Software reset flag
|
|
bit_offset: 28
|
|
bit_size: 1
|
|
- name: IWDGRSTF
|
|
description: Independent window watchdog reset flag
|
|
bit_offset: 29
|
|
bit_size: 1
|
|
- name: WWDGRSTF
|
|
description: Window watchdog reset flag
|
|
bit_offset: 30
|
|
bit_size: 1
|
|
- name: LPWRRSTF
|
|
description: Low-power reset flag
|
|
bit_offset: 31
|
|
bit_size: 1
|
|
fieldset/ICSCR:
|
|
description: Internal clock sources calibration register
|
|
fields:
|
|
- name: HSICAL0
|
|
description: Internal High Speed clock Calibration
|
|
bit_offset: 16
|
|
bit_size: 8
|
|
- name: HSITRIM
|
|
description: Internal High Speed clock trimming
|
|
bit_offset: 24
|
|
bit_size: 7
|
|
fieldset/PLLCFGR:
|
|
description: PLL configuration register
|
|
fields:
|
|
- name: PLLSRC
|
|
description: "Main PLL, PLLSAI1 and PLLSAI2 entry clock source"
|
|
bit_offset: 0
|
|
bit_size: 2
|
|
enum: PLLSRC
|
|
- name: PLLM
|
|
description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock
|
|
bit_offset: 4
|
|
bit_size: 4
|
|
- name: PLLN
|
|
description: Main PLL multiplication factor for VCO
|
|
bit_offset: 8
|
|
bit_size: 7
|
|
- name: PLLPEN
|
|
description: Main PLL PLLSAI3CLK output enable
|
|
bit_offset: 16
|
|
bit_size: 1
|
|
- name: PLLP
|
|
description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
|
|
bit_offset: 17
|
|
bit_size: 1
|
|
- name: PLLQEN
|
|
description: Main PLL PLLUSB1CLK output enable
|
|
bit_offset: 20
|
|
bit_size: 1
|
|
- name: PLLQ
|
|
description: Main PLL division factor for PLLUSB1CLK(48 MHz clock)
|
|
bit_offset: 21
|
|
bit_size: 2
|
|
- name: PLLREN
|
|
description: Main PLL PLLCLK output enable
|
|
bit_offset: 24
|
|
bit_size: 1
|
|
- name: PLLR
|
|
description: Main PLL division factor for PLLCLK (system clock)
|
|
bit_offset: 25
|
|
bit_size: 2
|
|
- name: PLLPDIV
|
|
description: Main PLL division factor for PLLSAI2CLK
|
|
bit_offset: 27
|
|
bit_size: 5
|
|
enum/HPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: SYSCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: SYSCLK is divided by 2
|
|
value: 8
|
|
- name: Div4
|
|
description: SYSCLK is divided by 4
|
|
value: 9
|
|
- name: Div8
|
|
description: SYSCLK is divided by 8
|
|
value: 10
|
|
- name: Div16
|
|
description: SYSCLK is divided by 16
|
|
value: 11
|
|
- name: Div64
|
|
description: SYSCLK is divided by 64
|
|
value: 12
|
|
- name: Div128
|
|
description: SYSCLK is divided by 128
|
|
value: 13
|
|
- name: Div256
|
|
description: SYSCLK is divided by 256
|
|
value: 14
|
|
- name: Div512
|
|
description: SYSCLK is divided by 512
|
|
value: 15
|
|
enum/LSEDRV:
|
|
bit_size: 2
|
|
variants:
|
|
- name: Low
|
|
description: Low driving capability
|
|
value: 0
|
|
- name: MediumLow
|
|
description: Medium low driving capability
|
|
value: 1
|
|
- name: MediumHigh
|
|
description: Medium high driving capability
|
|
value: 2
|
|
- name: High
|
|
description: High driving capability
|
|
value: 3
|
|
enum/MCOPRE:
|
|
bit_size: 3
|
|
variants:
|
|
- name: Div1
|
|
description: MCO1 not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: MCO clock is divided by 2
|
|
value: 1
|
|
- name: Div4
|
|
description: MCO clock is divided by 4
|
|
value: 2
|
|
- name: Div8
|
|
description: MCO clock is divided by 8
|
|
value: 3
|
|
- name: Div16
|
|
description: MCO clock is divided divided by 16
|
|
value: 4
|
|
enum/MCOSEL:
|
|
bit_size: 4
|
|
variants:
|
|
- name: NoClock
|
|
description: "No clock, MCO output disabled"
|
|
value: 0
|
|
- name: SYSCLK
|
|
description: SYSCLK selected as MCO source
|
|
value: 1
|
|
- name: HSI16
|
|
description: HSI16 selected as MCO source
|
|
value: 3
|
|
- name: HSE
|
|
description: HSE selected as MCO source
|
|
value: 4
|
|
- name: PLLCLK
|
|
description: Main PLLCLK selected as MCO source
|
|
value: 5
|
|
- name: LSI
|
|
description: LSI selected as MCO source
|
|
value: 6
|
|
- name: LSE
|
|
description: LSE selected as MCO source
|
|
value: 7
|
|
- name: HSI48
|
|
description: HSI48 selected as MCO source
|
|
value: 8
|
|
enum/PLLSRC:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock selected as PLL entry clock source
|
|
value: 0
|
|
- name: HSI16
|
|
description: HSI16 selected as PLL entry clock source
|
|
value: 2
|
|
- name: HSE
|
|
description: HSE selected as PLL entry clock source
|
|
value: 3
|
|
enum/PPRE:
|
|
bit_size: 4
|
|
variants:
|
|
- name: Div1
|
|
description: HCLK not divided
|
|
value: 0
|
|
- name: Div2
|
|
description: HCLK is divided by 2
|
|
value: 4
|
|
- name: Div4
|
|
description: HCLK is divided by 4
|
|
value: 5
|
|
- name: Div8
|
|
description: HCLK is divided by 8
|
|
value: 6
|
|
- name: Div16
|
|
description: HCLK is divided by 16
|
|
value: 7
|
|
enum/RTCSEL:
|
|
bit_size: 2
|
|
variants:
|
|
- name: NoClock
|
|
description: No clock used as RTC clock
|
|
value: 0
|
|
- name: LSE
|
|
description: LSE used as RTC clock
|
|
value: 1
|
|
- name: LSI
|
|
description: LSI used as RTC clock
|
|
value: 2
|
|
- name: HSE_Div32
|
|
description: HSE divided by 32 used as RTC clock
|
|
value: 3
|
|
enum/SW:
|
|
bit_size: 2
|
|
variants:
|
|
- name: HSI16
|
|
description: HSI16 selected as system clock
|
|
value: 1
|
|
- name: HSE
|
|
description: HSE selected as system clock
|
|
value: 2
|
|
- name: PLLRCLK
|
|
description: PLLRCLK selected as system clock
|
|
value: 3
|