514 lines
12 KiB
YAML
514 lines
12 KiB
YAML
---
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block/LPUART:
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description: Lower power Universal asynchronous receiver transmitter
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items:
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- name: CR1
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description: Control register 1
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byte_offset: 0
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fieldset: CR1
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- name: CR2
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description: Control register 2
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byte_offset: 4
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fieldset: CR2
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- name: CR3
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description: Control register 3
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byte_offset: 8
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fieldset: CR3
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- name: BRR
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description: Baud rate register
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byte_offset: 12
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fieldset: BRR
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- name: RQR
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description: Request register
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byte_offset: 24
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access: Write
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fieldset: RQR
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- name: ISR
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description: Interrupt & status register
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byte_offset: 28
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access: Read
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fieldset: ISR
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- name: ICR
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description: Interrupt flag clear register
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byte_offset: 32
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access: Write
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fieldset: ICR
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- name: RDR
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description: Receive data register
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byte_offset: 36
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access: Read
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fieldset: RDR
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- name: TDR
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description: Transmit data register
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byte_offset: 40
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fieldset: TDR
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- name: PRESC
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description: Prescaler register
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byte_offset: 44
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fieldset: PRESC
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fieldset/BRR:
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description: Baud rate register
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fields:
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- name: BRR
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description: BRR
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bit_offset: 0
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bit_size: 20
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fieldset/CR1:
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description: Control register 1
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fields:
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- name: UE
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description: USART enable
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bit_offset: 0
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bit_size: 1
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- name: UESM
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description: USART enable in Stop mode
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bit_offset: 1
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bit_size: 1
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- name: RE
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description: Receiver enable
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bit_offset: 2
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bit_size: 1
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- name: TE
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description: Transmitter enable
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bit_offset: 3
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bit_size: 1
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- name: IDLEIE
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description: IDLE interrupt enable
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bit_offset: 4
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bit_size: 1
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- name: RXNEIE
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description: RXNE interrupt enable
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bit_offset: 5
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bit_size: 1
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- name: TCIE
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description: Transmission complete interrupt enable
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bit_offset: 6
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bit_size: 1
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- name: TXEIE
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description: interrupt enable
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bit_offset: 7
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bit_size: 1
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- name: PEIE
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description: PE interrupt enable
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bit_offset: 8
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bit_size: 1
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- name: PS
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description: Parity selection
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bit_offset: 9
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bit_size: 1
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enum: PS
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- name: PCE
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description: Parity control enable
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bit_offset: 10
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bit_size: 1
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- name: WAKE
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description: Receiver wakeup method
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bit_offset: 11
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bit_size: 1
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enum: WAKE
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- name: M0
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description: Word length
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bit_offset: 12
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bit_size: 1
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enum: M0
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- name: MME
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description: Mute mode enable
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bit_offset: 13
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bit_size: 1
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- name: CMIE
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description: Character match interrupt enable
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bit_offset: 14
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bit_size: 1
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- name: DEDT
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description: Driver Enable de-assertion time
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bit_offset: 16
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bit_size: 5
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- name: DEAT
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description: Driver Enable assertion time
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bit_offset: 21
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bit_size: 5
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- name: M1
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description: Word length
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bit_offset: 28
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bit_size: 1
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enum: M1
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- name: FIFOEN
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description: FIFO mode enable
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bit_offset: 29
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bit_size: 1
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- name: TXFEIE
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description: TXFIFO empty interrupt enable
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bit_offset: 30
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bit_size: 1
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- name: RXFFIE
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description: RXFIFO Full interrupt enable
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bit_offset: 31
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bit_size: 1
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fieldset/CR2:
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description: Control register 2
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fields:
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- name: ADDM7
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description: 7-bit Address Detection/4-bit Address Detection
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bit_offset: 4
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bit_size: 1
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enum: ADDM7
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- name: STOP
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description: STOP bits
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bit_offset: 12
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bit_size: 2
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enum: STOP
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- name: SWAP
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description: Swap TX/RX pins
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bit_offset: 15
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bit_size: 1
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- name: RXINV
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description: RX pin active level inversion
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bit_offset: 16
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bit_size: 1
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- name: TXINV
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description: TX pin active level inversion
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bit_offset: 17
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bit_size: 1
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- name: DATAINV
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description: Binary data inversion
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bit_offset: 18
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bit_size: 1
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- name: MSBFIRST
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description: Most significant bit first
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bit_offset: 19
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bit_size: 1
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enum: MSBFIRST
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- name: ADD
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description: Address of the USART node
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bit_offset: 24
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bit_size: 8
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fieldset/CR3:
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description: Control register 3
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fields:
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- name: EIE
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description: Error interrupt enable
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bit_offset: 0
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bit_size: 1
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- name: HDSEL
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description: Half-duplex selection
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bit_offset: 3
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bit_size: 1
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- name: DMAR
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description: DMA enable receiver
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bit_offset: 6
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bit_size: 1
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- name: DMAT
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description: DMA enable transmitter
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bit_offset: 7
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bit_size: 1
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- name: RTSE
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description: RTS enable
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bit_offset: 8
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bit_size: 1
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- name: CTSE
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description: CTS enable
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bit_offset: 9
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bit_size: 1
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- name: CTSIE
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description: CTS interrupt enable
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bit_offset: 10
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bit_size: 1
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- name: OVRDIS
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description: Overrun Disable
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bit_offset: 12
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bit_size: 1
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- name: DDRE
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description: DMA Disable on Reception Error
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bit_offset: 13
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bit_size: 1
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- name: DEM
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description: Driver enable mode
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bit_offset: 14
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bit_size: 1
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- name: DEP
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description: Driver enable polarity selection
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bit_offset: 15
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bit_size: 1
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enum: DEP
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- name: WUS
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description: Wakeup from Stop mode interrupt flag selection
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bit_offset: 20
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bit_size: 2
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enum: WUS
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- name: WUFIE
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description: Wakeup from Stop mode interrupt enable
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bit_offset: 22
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bit_size: 1
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- name: TXFTIE
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description: TXFIFO threshold interrupt enable
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bit_offset: 23
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bit_size: 1
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- name: RXFTCFG
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description: Receive FIFO threshold configuration
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bit_offset: 25
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bit_size: 3
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- name: RXFTIE
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description: RXFIFO threshold interrupt enable
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bit_offset: 28
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bit_size: 1
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- name: TXFTCFG
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description: TXFIFO threshold configuration
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bit_offset: 29
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bit_size: 3
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fieldset/ICR:
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description: Interrupt flag clear register
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fields:
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- name: PECF
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description: Parity error clear flag
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bit_offset: 0
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bit_size: 1
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- name: FECF
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description: Framing error clear flag
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bit_offset: 1
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bit_size: 1
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- name: NCF
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description: Noise detected clear flag
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bit_offset: 2
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bit_size: 1
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- name: ORECF
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description: Overrun error clear flag
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bit_offset: 3
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bit_size: 1
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- name: IDLECF
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description: Idle line detected clear flag
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bit_offset: 4
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bit_size: 1
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- name: TCCF
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description: Transmission complete clear flag
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bit_offset: 6
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bit_size: 1
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- name: CTSCF
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description: CTS clear flag
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bit_offset: 9
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bit_size: 1
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- name: CMCF
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description: Character match clear flag
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bit_offset: 17
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bit_size: 1
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- name: WUCF
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description: Wakeup from Stop mode clear flag
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bit_offset: 20
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bit_size: 1
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fieldset/ISR:
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description: Interrupt & status register
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fields:
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- name: PE
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description: PE
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bit_offset: 0
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bit_size: 1
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- name: FE
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description: FE
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bit_offset: 1
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bit_size: 1
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- name: NE
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description: NE
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bit_offset: 2
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bit_size: 1
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- name: ORE
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description: ORE
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bit_offset: 3
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bit_size: 1
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- name: IDLE
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description: IDLE
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bit_offset: 4
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bit_size: 1
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- name: RXNE
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description: RXNE
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bit_offset: 5
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bit_size: 1
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- name: TC
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description: TC
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bit_offset: 6
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bit_size: 1
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- name: TXE
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description: TXE
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bit_offset: 7
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bit_size: 1
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- name: CTSIF
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description: CTSIF
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bit_offset: 9
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bit_size: 1
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- name: CTS
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description: CTS
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bit_offset: 10
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bit_size: 1
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- name: BUSY
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description: BUSY
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bit_offset: 16
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bit_size: 1
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- name: CMF
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description: CMF
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bit_offset: 17
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bit_size: 1
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- name: SBKF
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description: SBKF
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bit_offset: 18
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bit_size: 1
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- name: RWU
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description: RWU
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bit_offset: 19
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bit_size: 1
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- name: WUF
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description: WUF
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bit_offset: 20
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bit_size: 1
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- name: TEACK
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description: TEACK
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bit_offset: 21
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bit_size: 1
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- name: REACK
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description: REACK
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bit_offset: 22
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bit_size: 1
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- name: TXFE
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description: TXFIFO Empty
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bit_offset: 23
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bit_size: 1
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- name: RXFF
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description: RXFIFO Full
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bit_offset: 24
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bit_size: 1
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- name: RXFT
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description: RXFIFO threshold flag
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bit_offset: 26
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bit_size: 1
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- name: TXFT
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description: TXFIFO threshold flag
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bit_offset: 27
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bit_size: 1
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fieldset/PRESC:
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description: Prescaler register
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fields:
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- name: PRESCALER
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description: Clock prescaler
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bit_offset: 0
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bit_size: 4
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fieldset/RDR:
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description: Receive data register
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fields:
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- name: RDR
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description: Receive data value
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bit_offset: 0
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bit_size: 9
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fieldset/RQR:
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description: Request register
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fields:
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- name: SBKRQ
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description: Send break request
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bit_offset: 1
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bit_size: 1
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- name: MMRQ
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description: Mute mode request
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bit_offset: 2
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bit_size: 1
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- name: RXFRQ
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description: Receive data flush request
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bit_offset: 3
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bit_size: 1
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- name: TXFRQ
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description: Transmit data flush request
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bit_offset: 4
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bit_size: 1
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fieldset/TDR:
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description: Transmit data register
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fields:
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- name: TDR
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description: Transmit data value
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bit_offset: 0
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bit_size: 9
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enum/ADDM7:
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bit_size: 1
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variants:
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- name: Bit4
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description: 4-bit address detection
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value: 0
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- name: Bit7
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description: 7-bit address detection
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value: 1
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enum/DEP:
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bit_size: 1
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variants:
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- name: High
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description: DE signal is active high
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value: 0
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- name: Low
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description: DE signal is active low
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value: 1
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enum/M0:
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bit_size: 1
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variants:
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- name: Bit8
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description: "1 start bit, 8 data bits, n stop bits"
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value: 0
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- name: Bit9
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description: "1 start bit, 9 data bits, n stop bits"
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value: 1
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enum/M1:
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bit_size: 1
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variants:
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- name: M0
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description: Use M0 to set the data bits
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value: 0
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- name: Bit7
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description: "1 start bit, 7 data bits, n stop bits"
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value: 1
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enum/MSBFIRST:
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bit_size: 1
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variants:
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- name: LSB
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description: "data is transmitted/received with data bit 0 first, following the start bit"
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value: 0
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- name: MSB
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description: "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"
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value: 1
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enum/PS:
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bit_size: 1
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variants:
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- name: Even
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description: Even parity
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value: 0
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- name: Odd
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description: Odd parity
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value: 1
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enum/STOP:
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bit_size: 2
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variants:
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- name: Stop1
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description: 1 stop bit
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value: 0
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- name: Stop0p5
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description: 0.5 stop bit
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value: 1
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- name: Stop2
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description: 2 stop bit
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value: 2
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- name: Stop1p5
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description: 1.5 stop bit
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value: 3
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enum/WAKE:
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bit_size: 1
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variants:
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- name: Idle
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description: Idle line
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value: 0
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- name: Address
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description: Address mask
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value: 1
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enum/WUS:
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bit_size: 2
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variants:
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- name: Address
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description: WUF active on address match
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value: 0
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- name: Start
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description: WuF active on Start bit detection
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value: 2
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- name: RXNE
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description: WUF active on RXNE
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value: 3
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