# stm32f100
# stm32f412
# stm32f413
# stm32f423
# stm32l1
---
block/FSMC:
  description: Flexible static memory controller
  items:
    - name: BCR
      description: SRAM/NOR-Flash chip-select control register 1-4
      array:
        len: 4
        stride: 8
      byte_offset: 0
      fieldset: BCR
    - name: BTR
      description: SRAM/NOR-Flash chip-select timing register 1-4
      array:
        len: 4
        stride: 8
      byte_offset: 4
      fieldset: BTR
    - name: BWTR
      description: SRAM/NOR-Flash write timing registers 1-4
      array:
        len: 4
        stride: 8
      byte_offset: 260
      fieldset: BWTR
fieldset/BCR:
  description: SRAM/NOR-Flash chip-select control register
  fields:
    - name: MBKEN
      description: Memory bank enable bit
      bit_offset: 0
      bit_size: 1
    - name: MUXEN
      description: Address/data multiplexing enable bit
      bit_offset: 1
      bit_size: 1
    - name: MTYP
      description: Memory type
      bit_offset: 2
      bit_size: 2
      enum: MTYP
    - name: MWID
      description: Memory data bus width
      bit_offset: 4
      bit_size: 2
      enum: MWID
    - name: FACCEN
      description: Flash access enable
      bit_offset: 6
      bit_size: 1
    - name: BURSTEN
      description: Burst enable bit
      bit_offset: 8
      bit_size: 1
    - name: WAITPOL
      description: Wait signal polarity bit
      bit_offset: 9
      bit_size: 1
      enum: WAITPOL
    - name: WRAPMOD
      description: WRAPMOD
      bit_offset: 10
      bit_size: 1
    - name: WAITCFG
      description: Wait timing configuration
      bit_offset: 11
      bit_size: 1
      enum: WAITCFG
    - name: WREN
      description: Write enable bit
      bit_offset: 12
      bit_size: 1
    - name: WAITEN
      description: Wait enable bit
      bit_offset: 13
      bit_size: 1
    - name: EXTMOD
      description: Extended mode enable
      bit_offset: 14
      bit_size: 1
    - name: ASYNCWAIT
      description: Wait signal during asynchronous transfers
      bit_offset: 15
      bit_size: 1
    - name: CPSIZE
      description: CRAM page size
      bit_offset: 16
      bit_size: 3
      enum: CPSIZE
    - name: CBURSTRW
      description: Write burst enable
      bit_offset: 19
      bit_size: 1
fieldset/BTR:
  description: SRAM/NOR-Flash chip-select timing register
  fields:
    - name: ADDSET
      description: Address setup phase duration
      bit_offset: 0
      bit_size: 4
    - name: ADDHLD
      description: Address-hold phase duration
      bit_offset: 4
      bit_size: 4
    - name: DATAST
      description: Data-phase duration
      bit_offset: 8
      bit_size: 8
    - name: BUSTURN
      description: Bus turnaround phase duration
      bit_offset: 16
      bit_size: 4
    - name: CLKDIV
      description: Clock divide ratio (for FMC_CLK signal)
      bit_offset: 20
      bit_size: 4
    - name: DATLAT
      description: Data latency for synchronous memory
      bit_offset: 24
      bit_size: 4
    - name: ACCMOD
      description: Access mode
      bit_offset: 28
      bit_size: 2
      enum: ACCMOD
fieldset/BWTR:
  description: SRAM/NOR-Flash write timing registers
  fields:
    - name: ADDSET
      description: Address setup phase duration
      bit_offset: 0
      bit_size: 4
    - name: ADDHLD
      description: Address-hold phase duration
      bit_offset: 4
      bit_size: 4
    - name: DATAST
      description: Data-phase duration
      bit_offset: 8
      bit_size: 8
    - name: BUSTURN
      description: Bus turnaround phase duration
      bit_offset: 16
      bit_size: 4
    - name: ACCMOD
      description: Access mode
      bit_offset: 28
      bit_size: 2
      enum: ACCMOD
enum/ACCMOD:
  bit_size: 2
  variants:
    - name: A
      description: Access mode A
      value: 0
    - name: B
      description: Access mode B
      value: 1
    - name: C
      description: Access mode C
      value: 2
    - name: D
      description: Access mode D
      value: 3
enum/CPSIZE:
  bit_size: 3
  variants:
    - name: NoBurstSplit
      description: No burst split when crossing page boundary
      value: 0
    - name: Bytes128
      description: 128 bytes CRAM page size
      value: 1
    - name: Bytes256
      description: 256 bytes CRAM page size
      value: 2
    - name: Bytes512
      description: 512 bytes CRAM page size
      value: 3
    - name: Bytes1024
      description: 1024 bytes CRAM page size
      value: 4
enum/MTYP:
  bit_size: 2
  variants:
    - name: SRAM
      description: SRAM memory type
      value: 0
    - name: PSRAM
      description: PSRAM (CRAM) memory type
      value: 1
    - name: Flash
      description: NOR Flash/OneNAND Flash
      value: 2
enum/MWID:
  bit_size: 2
  variants:
    - name: Bits8
      description: Memory data bus width 8 bits
      value: 0
    - name: Bits16
      description: Memory data bus width 16 bits
      value: 1
    - name: Bits32
      description: Memory data bus width 32 bits
      value: 2
enum/WAITCFG:
  bit_size: 1
  variants:
    - name: BeforeWaitState
      description: NWAIT signal is active one data cycle before wait state
      value: 0
    - name: DuringWaitState
      description: NWAIT signal is active during wait state
      value: 1
enum/WAITPOL:
  bit_size: 1
  variants:
    - name: ActiveLow
      description: NWAIT active low
      value: 0
    - name: ActiveHigh
      description: NWAIT active high
      value: 1