PA0:
  EVENTOUT: 15
  TIM2_CH1: 1
  TIM2_ETR: 1
  TSC_G1_IO1: 3
  USART2_CTS: 7
PA1:
  EVENTOUT: 15
  RTC_REFIN: 0
  TIM15_CH1N: 9
  TIM2_CH2: 1
  TSC_G1_IO2: 3
  USART2_DE: 7
  USART2_RTS: 7
PA10:
  COMP6_OUT: 8
  EVENTOUT: 15
  I2C2_SDA: 4
  I2S2_ext_SD: 5
  SPI2_MISO: 5
  TIM17_BKIN: 1
  TIM1_CH3: 6
  TIM2_CH4: 10
  TSC_G4_IO2: 3
  USART1_RX: 7
PA11:
  CAN_RX: 9
  EVENTOUT: 15
  I2S2_SD: 5
  SPI2_MOSI: 5
  TIM1_BKIN2: 12
  TIM1_CH1N: 6
  TIM1_CH4: 11
  USART1_CTS: 7
PA12:
  CAN_TX: 9
  COMP2_OUT: 8
  EVENTOUT: 15
  I2S_CKIN: 5
  TIM16_CH1: 1
  TIM1_CH2N: 6
  TIM1_ETR: 11
  USART1_DE: 7
  USART1_RTS: 7
PA13:
  EVENTOUT: 15
  IR_OUT: 5
  SYS_JTMS-SWDIO: 0
  TIM16_CH1N: 1
  TSC_G4_IO3: 3
  USART3_CTS: 7
PA14:
  EVENTOUT: 15
  I2C1_SDA: 4
  SYS_JTCK-SWCLK: 0
  TIM1_BKIN: 6
  TSC_G4_IO4: 3
  USART2_TX: 7
PA15:
  EVENTOUT: 15
  I2C1_SCL: 4
  I2S3_WS: 6
  SPI3_NSS: 6
  SYS_JTDI: 0
  TIM1_BKIN: 9
  TIM2_CH1: 1
  TIM2_ETR: 1
  TSC_SYNC: 3
  USART2_RX: 7
PA2:
  COMP2_OUT: 8
  EVENTOUT: 15
  TIM15_CH1: 9
  TIM2_CH3: 1
  TSC_G1_IO3: 3
  USART2_TX: 7
PA3:
  EVENTOUT: 15
  TIM15_CH2: 9
  TIM2_CH4: 1
  TSC_G1_IO4: 3
  USART2_RX: 7
PA4:
  EVENTOUT: 15
  I2S3_WS: 6
  SPI3_NSS: 6
  TSC_G2_IO1: 3
  USART2_CK: 7
PA5:
  EVENTOUT: 15
  TIM2_CH1: 1
  TIM2_ETR: 1
  TSC_G2_IO2: 3
PA6:
  EVENTOUT: 15
  TIM16_CH1: 1
  TIM1_BKIN: 6
  TSC_G2_IO3: 3
PA7:
  EVENTOUT: 15
  TIM17_CH1: 1
  TIM1_CH1N: 6
  TSC_G2_IO4: 3
PA8:
  EVENTOUT: 15
  I2C2_SMBA: 4
  I2C3_SCL: 3
  I2S2_MCK: 5
  RCC_MCO: 0
  TIM1_CH1: 6
  USART1_CK: 7
PA9:
  EVENTOUT: 15
  I2C2_SCL: 4
  I2C3_SMBA: 2
  I2S3_MCK: 5
  TIM15_BKIN: 9
  TIM1_CH2: 6
  TIM2_CH3: 10
  TSC_G4_IO1: 3
  USART1_TX: 7
PB0:
  EVENTOUT: 15
  TIM1_CH2N: 6
  TSC_G3_IO2: 3
PB1:
  COMP4_OUT: 8
  EVENTOUT: 15
  TIM1_CH3N: 6
  TSC_G3_IO3: 3
PB10:
  EVENTOUT: 15
  TIM2_CH3: 1
  TSC_SYNC: 3
  USART3_TX: 7
PB11:
  EVENTOUT: 15
  TIM2_CH4: 1
  TSC_G6_IO1: 3
  USART3_RX: 7
PB12:
  EVENTOUT: 15
  I2C2_SMBA: 4
  I2S2_WS: 5
  SPI2_NSS: 5
  TIM1_BKIN: 6
  TSC_G6_IO2: 3
  USART3_CK: 7
PB13:
  EVENTOUT: 15
  I2S2_CK: 5
  SPI2_SCK: 5
  TIM1_CH1N: 6
  TSC_G6_IO3: 3
  USART3_CTS: 7
PB14:
  EVENTOUT: 15
  I2S2_ext_SD: 5
  SPI2_MISO: 5
  TIM15_CH1: 1
  TIM1_CH2N: 6
  TSC_G6_IO4: 3
  USART3_DE: 7
  USART3_RTS: 7
PB15:
  EVENTOUT: 15
  I2S2_SD: 5
  RTC_REFIN: 0
  SPI2_MOSI: 5
  TIM15_CH1N: 2
  TIM15_CH2: 1
  TIM1_CH3N: 4
PB2:
  EVENTOUT: 15
  TSC_G3_IO4: 3
PB3:
  EVENTOUT: 15
  I2S3_CK: 6
  SPI3_SCK: 6
  SYS_JTDO-TRACESWO: 0
  TIM2_CH2: 1
  TSC_G5_IO1: 3
  USART2_TX: 7
PB4:
  EVENTOUT: 15
  I2S3_ext_SD: 6
  SPI3_MISO: 6
  SYS_NJTRST: 0
  TIM16_CH1: 1
  TIM17_BKIN: 10
  TSC_G5_IO2: 3
  USART2_RX: 7
PB5:
  EVENTOUT: 15
  I2C1_SMBA: 4
  I2C3_SDA: 8
  I2S3_SD: 6
  SPI3_MOSI: 6
  TIM16_BKIN: 1
  TIM17_CH1: 10
  USART2_CK: 7
PB6:
  EVENTOUT: 15
  I2C1_SCL: 4
  TIM16_CH1N: 1
  TSC_G5_IO3: 3
  USART1_TX: 7
PB7:
  EVENTOUT: 15
  I2C1_SDA: 4
  TIM17_CH1N: 1
  TSC_G5_IO4: 3
  USART1_RX: 7
PB8:
  CAN_RX: 9
  EVENTOUT: 15
  I2C1_SCL: 4
  TIM16_CH1: 1
  TIM1_BKIN: 12
  TSC_SYNC: 3
  USART3_RX: 7
PB9:
  CAN_TX: 9
  COMP2_OUT: 8
  EVENTOUT: 15
  I2C1_SDA: 4
  IR_OUT: 6
  TIM17_CH1: 1
  USART3_TX: 7
PC0:
  EVENTOUT: 1
  TIM1_CH1: 2
PC1:
  EVENTOUT: 1
  TIM1_CH2: 2
PC10:
  EVENTOUT: 1
  I2S3_CK: 6
  SPI3_SCK: 6
  USART3_TX: 7
PC11:
  EVENTOUT: 1
  I2S3_ext_SD: 6
  SPI3_MISO: 6
  USART3_RX: 7
PC12:
  EVENTOUT: 1
  I2S3_SD: 6
  SPI3_MOSI: 6
  USART3_CK: 7
PC13:
  TIM1_CH1N: 4
PC14: {}
PC15: {}
PC2:
  EVENTOUT: 1
  TIM1_CH3: 2
PC3:
  EVENTOUT: 1
  TIM1_BKIN2: 6
  TIM1_CH4: 2
PC4:
  EVENTOUT: 1
  TIM1_ETR: 2
  USART1_TX: 7
PC5:
  EVENTOUT: 1
  TIM15_BKIN: 2
  TSC_G3_IO1: 3
  USART1_RX: 7
PC6:
  COMP6_OUT: 7
  EVENTOUT: 1
  I2S2_MCK: 6
PC7:
  EVENTOUT: 1
  I2S3_MCK: 6
PC8:
  EVENTOUT: 1
PC9:
  EVENTOUT: 1
  I2C3_SDA: 3
  I2S_CKIN: 5
PD2:
  EVENTOUT: 1
PF0:
  I2C2_SDA: 4
  I2S2_WS: 5
  SPI2_NSS: 5
  TIM1_CH3N: 6
PF1:
  I2C2_SCL: 4
  I2S2_CK: 5
  SPI2_SCK: 5