block/TIM_1CH: extends: TIM_CORE description: 1-channel timers items: - name: CR1 description: control register 1 byte_offset: 0 fieldset: CR1_1CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_1CH - name: SR description: status register byte_offset: 16 fieldset: SR_1CH - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_1CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Input_1CH - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Output_1CH - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_1CH - name: CCR description: capture/compare register x (x=1) (Dither mode disabled) array: len: 1 stride: 4 byte_offset: 52 fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1) (Dither mode enabled) array: len: 1 stride: 4 byte_offset: 52 fieldset: CCR_DITHER_1CH - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL_1CH - name: OR description: |- Option register 1 Note: Check Reference Manual to parse this register content byte_offset: 104 block/TIM_1CH_CMP: extends: TIM_1CH description: 1-channel with one complementary output timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_1CH_CMP - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_1CH_CMP - name: SR description: status register byte_offset: 16 fieldset: SR_1CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_1CH_CMP - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_1CH_CMP - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR_1CH_CMP - name: BDTR description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP - name: DTR2 description: break and dead-time register byte_offset: 84 fieldset: DTR2_1CH_CMP - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_1CH_CMP - name: AF2 description: alternate function register 2 byte_offset: 100 fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 block/TIM_2CH: extends: TIM_1CH description: 2-channel timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_2CH - name: SMCR description: slave mode control register byte_offset: 8 fieldset: SMCR_2CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_2CH - name: SR description: status register byte_offset: 16 fieldset: SR_2CH - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_2CH - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Input_2CH - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 1 stride: 4 byte_offset: 24 fieldset: CCMR_Output_2CH - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_2CH - name: CCR description: capture/compare register x (x=1-2) (Dither mode disabled) array: len: 2 stride: 4 byte_offset: 52 fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1-2) (Dither mode enabled) array: len: 2 stride: 4 byte_offset: 52 fieldset: CCR_DITHER_1CH - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL_2CH block/TIM_2CH_CMP: extends: TIM_1CH_CMP description: 2-channel with one complementary output timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_2CH_CMP - name: SMCR description: slave mode control register byte_offset: 8 fieldset: SMCR_2CH_CMP - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_2CH_CMP - name: SR description: status register byte_offset: 16 fieldset: SR_2CH_CMP - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_2CH_CMP - name: CCMR_Input description: capture/compare mode register 1 (input mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Input_1CH - name: CCMR_Output description: capture/compare mode register 1 (output mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Output_1CH - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_2CH_CMP - name: CCR description: capture/compare register x (x=1-2) array: len: 2 stride: 4 byte_offset: 52 fieldset: CCR_1CH - name: BDTR description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL_2CH block/TIM_ADV: extends: TIM_2CH_CMP description: Advanced Control timers items: - name: CR1 description: control register 1 byte_offset: 0 fieldset: CR1_GP16 - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_ADV - name: SMCR description: slave mode control register byte_offset: 8 fieldset: SMCR_ADV - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_ADV - name: SR description: status register byte_offset: 16 fieldset: SR_ADV - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_ADV - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Input_2CH - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Output_GP16 - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_ADV - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR_ADV - name: CCR description: capture/compare register x (x=1-4) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_1CH - name: BDTR description: break and dead-time register byte_offset: 68 fieldset: BDTR_ADV - name: CCR5 description: capture/compare register 5 (Dither mode disabled) byte_offset: 72 fieldset: CCR5_ADV - name: CCR5_DITHER description: capture/compare register 5 (Dither mode enabled) byte_offset: 72 fieldset: CCR5_DITHER_ADV - name: CCR6 description: capture/compare register 6 (Dither mode disabled) byte_offset: 76 fieldset: CCR_1CH - name: CCR6_DITHER description: capture/compare register 6 (Dither mode enabled) byte_offset: 76 fieldset: CCR_DITHER_1CH - name: CCMR3 description: capture/compare mode register 3 byte_offset: 80 fieldset: CCMR3_ADV - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_ADV - name: AF2 description: alternate function register 2 byte_offset: 100 fieldset: AF2_ADV block/TIM_BASIC: extends: TIM_BASIC_NO_CR2 description: Basic timers items: - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_BASIC block/TIM_BASIC_NO_CR2: extends: TIM_CORE description: Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP items: - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_BASIC_NO_CR2 block/TIM_CORE: description: Virtual timer for common part of TIM_BASIC and TIM_1CH items: - name: CR1 description: control register 1 byte_offset: 0 fieldset: CR1_CORE - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_CORE - name: SR description: status register byte_offset: 16 fieldset: SR_CORE - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_CORE - name: CNT description: counter byte_offset: 36 fieldset: CNT_CORE - name: PSC description: prescaler byte_offset: 40 fieldset: PSC_CORE - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 fieldset: ARR_CORE - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 fieldset: ARR_DITHER_CORE block/TIM_GP16: extends: TIM_2CH description: General purpose 16-bit timers items: - name: CR1 description: control register 1 byte_offset: 0 fieldset: CR1_GP16 - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_GP16 - name: SMCR description: slave mode control register byte_offset: 8 fieldset: SMCR_GP16 - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_GP16 - name: SR description: status register byte_offset: 16 fieldset: SR_GP16 - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_GP16 - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Input_2CH - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Output_GP16 - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER_GP16 - name: CCR description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_1CH - name: CCR_DITHER description: capture/compare register x (x=1-4) (Dither mode enabled) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_DITHER_1CH - name: ECR description: encoder control register byte_offset: 88 fieldset: ECR_GP16 - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_GP16 - name: AF2 description: alternate function register 2 byte_offset: 100 fieldset: AF2_1CH_CMP - name: DCR description: DMA control register byte_offset: 988 fieldset: DCR_1CH_CMP - name: DMAR description: DMA address for full transfer byte_offset: 992 block/TIM_GP32: extends: TIM_GP16 description: General purpose 32-bit timers items: - name: CNT description: counter (Dither mode disabled) byte_offset: 36 - name: CNT_DITHER description: counter (Dither mode enbled) byte_offset: 36 fieldset: CNT_DITHER_GP32 - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 fieldset: ARR_DITHER_GP32 - name: CCR description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 - name: CCR_DITHER description: capture/compare register x (x=1-4) (Dither mode enabled) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_DITHER_GP32 fieldset/AF1_1CH_CMP: description: alternate function register 1 fields: - name: BKINE description: TIMx_BKIN input enable bit_offset: 0 bit_size: 1 - name: BKCMPE description: TIM_BRK_CMPx (x=1-8) enable bit_offset: 1 bit_size: 1 array: len: 8 stride: 1 - name: BKINP description: TIMx_BKIN input polarity bit_offset: 9 bit_size: 1 enum: BKINP - name: BKCMPP description: TIM_BRK_CMPx (x=1-4) input polarity bit_offset: 10 bit_size: 1 array: len: 4 stride: 1 enum: BKINP fieldset/AF1_ADV: extends: AF1_1CH_CMP description: alternate function register 1 fields: - name: ETRSEL description: etr_in source selection bit_offset: 14 bit_size: 4 fieldset/AF1_GP16: description: alternate function register 1 fields: - name: ETRSEL description: etr_in source selection bit_offset: 14 bit_size: 4 fieldset/AF2_1CH_CMP: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 fieldset/AF2_ADV: extends: AF2_1CH_CMP description: alternate function register 2 fields: - name: BK2INE description: TIMx_BKIN2 input enable bit_offset: 0 bit_size: 1 - name: BK2CMPE description: TIM_BRK2_CMPx (x=1-8) enable bit_offset: 1 bit_size: 1 array: len: 8 stride: 1 - name: BK2INP description: TIMx_BK2IN input polarity bit_offset: 9 bit_size: 1 enum: BKINP - name: BK2CMPP description: TIM_BRK2_CMPx (x=1-4) input polarity bit_offset: 10 bit_size: 1 array: len: 4 stride: 1 enum: BKINP fieldset/ARR_CORE: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 fieldset/ARR_DITHER_CORE: description: auto-reload register (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: ARR description: Auto-reload value bit_offset: 4 bit_size: 16 fieldset/ARR_DITHER_GP32: description: auto-reload register (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: ARR description: Auto-reload value bit_offset: 4 bit_size: 28 fieldset/BDTR_1CH_CMP: description: break and dead-time register fields: - name: DTG description: Dead-time generator setup bit_offset: 0 bit_size: 8 - name: LOCK description: Lock configuration bit_offset: 8 bit_size: 2 enum: LOCK - name: OSSI description: Off-state selection for Idle mode bit_offset: 10 bit_size: 1 enum: OSSI - name: OSSR description: Off-state selection for Run mode bit_offset: 11 bit_size: 1 enum: OSSR - name: BKE description: Break x (x=1) enable bit_offset: 12 bit_size: 1 array: len: 1 stride: 12 - name: BKP description: Break x (x=1) polarity bit_offset: 13 bit_size: 1 array: len: 1 stride: 12 enum: BKP - name: AOE description: Automatic output enable bit_offset: 14 bit_size: 1 - name: MOE description: Main output enable bit_offset: 15 bit_size: 1 - name: BKF description: Break x (x=1) filter bit_offset: 16 bit_size: 4 array: len: 1 stride: 4 enum: FilterValue - name: BKDSRM description: Break x (x=1) Disarm bit_offset: 26 bit_size: 1 array: len: 1 stride: 1 enum: BKDSRM - name: BKBID description: Break x (x=1) bidirectional bit_offset: 28 bit_size: 1 array: len: 1 stride: 1 enum: BKBID fieldset/BDTR_ADV: extends: BDTR_1CH_CMP description: break and dead-time register fields: - name: BKE description: Break x (x=1,2) enable bit_offset: 12 bit_size: 1 array: len: 2 stride: 12 - name: BKP description: Break x (x=1,2) polarity bit_offset: 13 bit_size: 1 array: len: 2 stride: 12 enum: BKP - name: BKF description: Break x (x=1,2) filter bit_offset: 16 bit_size: 4 array: len: 2 stride: 4 enum: FilterValue - name: BKDSRM description: Break x (x=1,2) Disarm bit_offset: 26 bit_size: 1 array: len: 2 stride: 1 enum: BKDSRM - name: BKBID description: Break x (x=1,2) bidirectional bit_offset: 28 bit_size: 1 array: len: 2 stride: 1 enum: BKBID fieldset/CCER_1CH: description: capture/compare enable register fields: - name: CCE description: Capture/Compare x (x=1) output enable bit_offset: 0 bit_size: 1 array: len: 1 stride: 4 - name: CCP description: Capture/Compare x (x=1) output Polarity bit_offset: 1 bit_size: 1 array: len: 1 stride: 4 - name: CCNP description: Capture/Compare x (x=1) output Polarity bit_offset: 3 bit_size: 1 array: len: 1 stride: 4 fieldset/CCER_1CH_CMP: extends: CCER_1CH description: capture/compare enable register fields: - name: CCNE description: Capture/Compare x (x=1) complementary output enable bit_offset: 2 bit_size: 1 array: len: 1 stride: 4 fieldset/CCER_2CH: extends: CCER_1CH description: capture/compare enable register fields: - name: CCE description: Capture/Compare x (x=1-2) output enable bit_offset: 0 bit_size: 1 array: len: 2 stride: 4 - name: CCP description: Capture/Compare x (x=1-2) output Polarity bit_offset: 1 bit_size: 1 array: len: 2 stride: 4 - name: CCNP description: Capture/Compare x (x=1-2) output Polarity bit_offset: 3 bit_size: 1 array: len: 2 stride: 4 fieldset/CCER_2CH_CMP: extends: CCER_2CH description: capture/compare enable register fields: - name: CCNE description: Capture/Compare x (x=1) complementary output enable bit_offset: 2 bit_size: 1 array: len: 1 stride: 4 fieldset/CCER_ADV: extends: CCER_2CH_CMP description: capture/compare enable register fields: - name: CCE description: Capture/Compare x (x=1-6) output enable bit_offset: 0 bit_size: 1 array: len: 6 stride: 4 - name: CCP description: Capture/Compare x (x=1-6) output Polarity bit_offset: 1 bit_size: 1 array: len: 6 stride: 4 - name: CCNE description: Capture/Compare x (x=1-4) complementary output enable bit_offset: 2 bit_size: 1 array: len: 4 stride: 4 - name: CCNP description: Capture/Compare x (x=1-4) output Polarity bit_offset: 3 bit_size: 1 array: len: 4 stride: 4 fieldset/CCER_GP16: description: capture/compare enable register fields: - name: CCE description: Capture/Compare x (x=1-4) output enable bit_offset: 0 bit_size: 1 array: len: 4 stride: 4 - name: CCP description: Capture/Compare x (x=1-4) output Polarity bit_offset: 1 bit_size: 1 array: len: 4 stride: 4 - name: CCNP description: Capture/Compare x (x=1-4) output Polarity bit_offset: 3 bit_size: 1 array: len: 4 stride: 4 fieldset/CCMR3_ADV: description: capture/compare mode register 3 fields: - name: OCFE description: Output compare x (x=5,6) fast enable bit_offset: 2 bit_size: 1 array: len: 2 stride: 8 - name: OCPE description: Output compare x (x=5,6) preload enable bit_offset: 3 bit_size: 1 array: len: 2 stride: 8 - name: OCM description: Output compare x (x=5,6) mode bit_offset: - start: 4 end: 6 - start: 16 end: 16 bit_size: 4 array: len: 2 stride: 8 enum: OCM - name: OCCE description: Output compare x (x=5,6) clear enable bit_offset: 7 bit_size: 1 array: len: 2 stride: 8 fieldset/CCMR_Input_1CH: description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 1 stride: 8 enum: CCMR_Input_CCS - name: ICPSC description: Input capture y prescaler bit_offset: 2 bit_size: 2 array: len: 1 stride: 8 - name: ICF description: Input capture y filter bit_offset: 4 bit_size: 4 array: len: 1 stride: 8 enum: FilterValue fieldset/CCMR_Input_2CH: extends: CCMR_Input_1CH description: capture/compare mode register x (x=1) (input mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 2 stride: 8 enum: CCMR_Input_CCS - name: ICPSC description: Input capture y prescaler bit_offset: 2 bit_size: 2 array: len: 2 stride: 8 - name: ICF description: Input capture y filter bit_offset: 4 bit_size: 4 array: len: 2 stride: 8 enum: FilterValue fieldset/CCMR_Output_1CH: description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 1 stride: 8 enum: CCMR_Output_CCS - name: OCFE description: Output compare y fast enable bit_offset: 2 bit_size: 1 array: len: 1 stride: 8 - name: OCPE description: Output compare y preload enable bit_offset: 3 bit_size: 1 array: len: 1 stride: 8 - name: OCM description: Output compare y mode bit_offset: - start: 4 end: 6 - start: 16 end: 16 bit_size: 4 array: len: 1 stride: 8 enum: OCM fieldset/CCMR_Output_2CH: extends: CCMR_Output_1CH description: capture/compare mode register x (x=1) (output mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 2 stride: 8 enum: CCMR_Output_CCS - name: OCFE description: Output compare y fast enable bit_offset: 2 bit_size: 1 array: len: 2 stride: 8 - name: OCPE description: Output compare y preload enable bit_offset: 3 bit_size: 1 array: len: 2 stride: 8 - name: OCM description: Output compare y mode bit_offset: - start: 4 end: 6 - start: 16 end: 16 bit_size: 4 array: len: 2 stride: 8 enum: OCM fieldset/CCMR_Output_GP16: extends: CCMR_Output_2CH description: capture/compare mode register x (x=1-2) (output mode) fields: - name: OCCE description: Output compare y clear enable bit_offset: 7 bit_size: 1 array: len: 2 stride: 8 fieldset/CCR5_ADV: extends: CCR_1CH description: capture/compare register 5 (Dither mode disabled) fields: - name: GC5C description: Group channel 5 and channel x (x=1-3) bit_offset: 29 bit_size: 1 array: len: 3 stride: 1 enum: GC5C fieldset/CCR5_DITHER_ADV: extends: CCR_DITHER_1CH description: capture/compare register 5 (Dither mode enabled) fields: - name: GC5C description: Group channel 5 and channel x (x=1-3) bit_offset: 29 bit_size: 1 array: len: 3 stride: 1 enum: GC5C fieldset/CCR_1CH: description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 fieldset/CCR_DITHER_1CH: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 4 - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 16 fieldset/CCR_DITHER_GP32: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 28 fieldset/CNT_CORE: description: counter fields: - name: CNT description: counter value bit_offset: 0 bit_size: 16 - name: UIFCPY description: UIF copy bit_offset: 31 bit_size: 1 fieldset/CNT_DITHER_GP32: description: counter (Dither mode enabled) fields: - name: CNT description: counter value bit_offset: 0 bit_size: 31 - name: UIFCPY description: UIF copy bit_offset: 31 bit_size: 1 fieldset/CR1_1CH: extends: CR1_CORE description: control register 1 fields: - name: CKD description: Clock division bit_offset: 8 bit_size: 2 enum: CKD fieldset/CR1_CORE: description: control register 1 fields: - name: CEN description: Counter enable bit_offset: 0 bit_size: 1 - name: UDIS description: Update disable bit_offset: 1 bit_size: 1 - name: URS description: Update request source bit_offset: 2 bit_size: 1 enum: URS - name: OPM description: One-pulse mode enbaled bit_offset: 3 bit_size: 1 - name: ARPE description: Auto-reload preload enable bit_offset: 7 bit_size: 1 - name: UIFREMAP description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - name: DITHEN description: Dithering enable bit_offset: 12 bit_size: 1 fieldset/CR1_GP16: extends: CR1_CORE description: control register 1 fields: - name: DIR description: Direction bit_offset: 4 bit_size: 1 enum: DIR - name: CMS description: Center-aligned mode selection bit_offset: 5 bit_size: 2 enum: CMS - name: CKD description: Clock division bit_offset: 8 bit_size: 2 enum: CKD fieldset/CR2_1CH_CMP: description: control register 2 fields: - name: CCPC description: Capture/compare preloaded control bit_offset: 0 bit_size: 1 - name: CCUS description: Capture/compare control update selection bit_offset: 2 bit_size: 1 - name: CCDS description: Capture/compare DMA selection bit_offset: 3 bit_size: 1 enum: CCDS - name: OIS description: Output Idle state x (x=1) bit_offset: 8 bit_size: 1 array: len: 1 stride: 2 - name: OISN description: Output Idle state x (x=1) bit_offset: 9 bit_size: 1 array: len: 1 stride: 2 fieldset/CR2_2CH: description: control register 2 fields: - name: MMS description: Master mode selection bit_offset: - start: 4 end: 6 - start: 25 end: 25 bit_size: 4 enum: MMS - name: TI1S description: TI1 selection bit_offset: 7 bit_size: 1 enum: TI1S fieldset/CR2_2CH_CMP: extends: CR2_1CH_CMP description: control register 2 fields: - name: MMS description: Master mode selection bit_offset: - start: 4 end: 6 - start: 25 end: 25 bit_size: 4 enum: MMS - name: TI1S description: TI1 selection bit_offset: 7 bit_size: 1 enum: TI1S - name: OIS description: Output Idle state x (x=1,2) bit_offset: 8 bit_size: 1 array: len: 2 stride: 2 fieldset/CR2_ADV: extends: CR2_2CH_CMP description: control register 2 fields: - name: OIS description: Output Idle state x (x=1-6) bit_offset: 8 bit_size: 1 array: len: 6 stride: 2 - name: OISN description: Output Idle state x N x (x=1-4) bit_offset: 9 bit_size: 1 array: len: 4 stride: 2 - name: MMS2 description: Master mode selection 2 bit_offset: 20 bit_size: 4 enum: MMS2 fieldset/CR2_BASIC: description: control register 2 fields: - name: MMS description: Master mode selection bit_offset: - start: 4 end: 6 - start: 25 end: 25 bit_size: 4 enum: MMS fieldset/CR2_GP16: extends: CR2_BASIC description: control register 2 fields: - name: CCDS description: Capture/compare DMA selection bit_offset: 3 bit_size: 1 enum: CCDS - name: TI1S description: TI1 selection bit_offset: 7 bit_size: 1 enum: TI1S fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA description: DMA base address bit_offset: 0 bit_size: 5 - name: DBL description: DMA burst length bit_offset: 8 bit_size: 5 - name: DBSS description: DMA burst source selection bit_offset: 16 bit_size: 4 enum: DBSS fieldset/DIER_1CH: extends: DIER_CORE description: DMA/Interrupt enable register fields: - name: CCIE description: Capture/Compare x (x=1) interrupt enable bit_offset: 1 bit_size: 1 array: len: 1 stride: 1 fieldset/DIER_1CH_CMP: extends: DIER_1CH description: DMA/Interrupt enable register fields: - name: COMIE description: COM interrupt enable bit_offset: 5 bit_size: 1 - name: BIE description: Break interrupt enable bit_offset: 7 bit_size: 1 - name: UDE description: Update DMA request enable bit_offset: 8 bit_size: 1 - name: CCDE description: Capture/Compare x (x=1) DMA request enable bit_offset: 9 bit_size: 1 array: len: 1 stride: 1 fieldset/DIER_2CH: extends: DIER_1CH description: DMA/Interrupt enable register fields: - name: CCIE description: Capture/Compare x (x=1-2) interrupt enable bit_offset: 1 bit_size: 1 array: len: 2 stride: 1 - name: TIE description: Trigger interrupt enable bit_offset: 6 bit_size: 1 fieldset/DIER_2CH_CMP: extends: DIER_1CH_CMP description: DMA/Interrupt enable register fields: - name: COMDE description: COM DMA request enable bit_offset: 13 bit_size: 1 - name: TDE description: Trigger DMA request enable bit_offset: 14 bit_size: 1 fieldset/DIER_ADV: extends: DIER_2CH_CMP description: DMA/Interrupt enable register fields: - name: CCIE description: Capture/Compare x (x=1-4) interrupt enable bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: BIE description: Break interrupt enable bit_offset: 7 bit_size: 1 - name: CCDE description: Capture/Compare x (x=1) DMA request enable bit_offset: 9 bit_size: 1 array: len: 4 stride: 1 - name: IDXIE description: Index interrupt enable bit_offset: 20 bit_size: 1 - name: DIRIE description: Direction change interrupt enable bit_offset: 21 bit_size: 1 - name: IERRIE description: Index error interrupt enable bit_offset: 22 bit_size: 1 - name: TERRIE description: Transition error interrupt enable bit_offset: 23 bit_size: 1 fieldset/DIER_BASIC_NO_CR2: extends: DIER_CORE description: DMA/Interrupt enable register fields: - name: UDE description: Update DMA request enable bit_offset: 8 bit_size: 1 fieldset/DIER_CORE: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 fieldset/DIER_GP16: extends: DIER_BASIC_NO_CR2 description: DMA/Interrupt enable register fields: - name: CCIE description: Capture/Compare x (x=1-4) interrupt enable bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: TIE description: Trigger interrupt enable bit_offset: 6 bit_size: 1 - name: CCDE description: Capture/Compare x (x=1-4) DMA request enable bit_offset: 9 bit_size: 1 array: len: 4 stride: 1 - name: TDE description: Trigger DMA request enable bit_offset: 14 bit_size: 1 - name: IDXIE description: Index interrupt enable bit_offset: 20 bit_size: 1 - name: DIRIE description: Direction change interrupt enable bit_offset: 21 bit_size: 1 - name: IERRIE description: Index error interrupt enable bit_offset: 22 bit_size: 1 - name: TERRIE description: Transition error interrupt enable bit_offset: 23 bit_size: 1 fieldset/DTR2_1CH_CMP: description: deadtime register 2 fields: - name: DTGF description: Dead-time falling edge generator setup bit_offset: 0 bit_size: 8 - name: DTAE description: Deadtime asymmetric enable bit_offset: 16 bit_size: 1 enum: DTAE - name: DTPE description: Deadtime preload enable bit_offset: 17 bit_size: 1 fieldset/ECR_GP16: description: encoder control register fields: - name: IE description: Index enable bit_offset: 0 bit_size: 1 - name: IDIR description: Index direction bit_offset: 1 bit_size: 2 enum: IDIR - name: IBLK description: Index blanking bit_offset: 3 bit_size: 2 enum: IBLK - name: FIDX description: First index bit_offset: 5 bit_size: 1 enum: FIDX - name: IPOS description: Index positioning bit_offset: 6 bit_size: 2 - name: PW description: Pulse width bit_offset: 16 bit_size: 8 - name: PWPRSC description: Pulse width prescaler bit_offset: 24 bit_size: 2 fieldset/EGR_1CH: extends: EGR_CORE description: event generation register fields: - name: CCG description: Capture/compare x (x=1) generation bit_offset: 1 bit_size: 1 array: len: 1 stride: 1 fieldset/EGR_1CH_CMP: extends: EGR_1CH description: event generation register fields: - name: COMG description: Capture/Compare control update generation bit_offset: 5 bit_size: 1 - name: BG description: Break x (x=1) generation bit_offset: 7 bit_size: 1 array: len: 1 stride: 1 fieldset/EGR_2CH: extends: EGR_1CH description: event generation register fields: - name: CCG description: Capture/compare x (x=1-2) generation bit_offset: 1 bit_size: 1 array: len: 2 stride: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 fieldset/EGR_2CH_CMP: extends: EGR_1CH_CMP description: event generation register fields: - name: CCG description: Capture/compare x (x=1,2) generation bit_offset: 1 bit_size: 1 array: len: 2 stride: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 fieldset/EGR_ADV: extends: EGR_2CH_CMP description: event generation register fields: - name: CCG description: Capture/compare x (x=1-4) generation bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: BG description: Break x (x=1-2) generation bit_offset: 7 bit_size: 1 array: len: 2 stride: 1 fieldset/EGR_CORE: description: event generation register fields: - name: UG description: Update generation bit_offset: 0 bit_size: 1 fieldset/EGR_GP16: extends: EGR_CORE description: event generation register fields: - name: CCG description: Capture/compare x (x=1-4) generation bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 fieldset/PSC_CORE: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 fieldset/RCR_1CH_CMP: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 8 fieldset/RCR_ADV: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 16 fieldset/SMCR_2CH: description: slave mode control register fields: - name: SMS description: Slave mode selection bit_offset: - start: 0 end: 2 - start: 16 end: 16 bit_size: 4 enum: SMS - name: TS description: Trigger selection bit_offset: - start: 4 end: 6 - start: 20 end: 21 bit_size: 5 enum: TS - name: MSM description: Master/Slave mode bit_offset: 7 bit_size: 1 enum: MSM fieldset/SMCR_2CH_CMP: extends: SMCR_2CH description: slave mode control register fields: - name: SMSPE description: SMS preload enable bit_offset: 24 bit_size: 1 fieldset/SMCR_ADV: extends: SMCR_2CH_CMP description: slave mode control register fields: - name: OCCS description: OCREF clear selection bit_offset: 3 bit_size: 1 enum: OCCS - name: ETF description: External trigger filter bit_offset: 8 bit_size: 4 enum: FilterValue - name: ETPS description: External trigger prescaler bit_offset: 12 bit_size: 2 enum: ETPS - name: ECE description: External clock mode 2 enable bit_offset: 14 bit_size: 1 - name: ETP description: External trigger polarity bit_offset: 15 bit_size: 1 enum: ETP - name: SMSPS description: SMS preload source bit_offset: 25 bit_size: 1 enum: SMSPS fieldset/SMCR_GP16: extends: SMCR_2CH description: slave mode control register fields: - name: ETF description: External trigger filter bit_offset: 8 bit_size: 4 enum: FilterValue - name: ETPS description: External trigger prescaler bit_offset: 12 bit_size: 2 enum: ETPS - name: ECE description: External clock mode 2 enable bit_offset: 14 bit_size: 1 - name: ETP description: External trigger polarity bit_offset: 15 bit_size: 1 enum: ETP - name: SMSPE description: SMS preload enable bit_offset: 24 bit_size: 1 - name: SMSPS description: SMS preload source bit_offset: 25 bit_size: 1 enum: SMSPS fieldset/SR_1CH: extends: SR_CORE description: status register fields: - name: CCIF description: Capture/compare x (x=1) interrupt flag bit_offset: 1 bit_size: 1 array: len: 1 stride: 1 - name: CCOF description: Capture/Compare x (x=1) overcapture flag bit_offset: 9 bit_size: 1 array: len: 1 stride: 1 fieldset/SR_1CH_CMP: extends: SR_1CH description: status register fields: - name: COMIF description: COM interrupt flag bit_offset: 5 bit_size: 1 - name: BIF description: Break x (x=1) interrupt flag bit_offset: 7 bit_size: 1 array: len: 1 stride: 1 fieldset/SR_2CH: extends: SR_1CH description: status register fields: - name: CCIF description: Capture/compare x (x=1-2) interrupt flag bit_offset: 1 bit_size: 1 array: len: 2 stride: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - name: CCOF description: Capture/Compare x (x=1-2) overcapture flag bit_offset: 9 bit_size: 1 array: len: 2 stride: 1 fieldset/SR_2CH_CMP: extends: SR_1CH_CMP description: status register fields: - name: CCIF description: Capture/compare x (x=1,2) interrupt flag bit_offset: 1 bit_size: 1 array: len: 2 stride: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - name: CCOF description: Capture/Compare x (x=1,2) overcapture flag bit_offset: 9 bit_size: 1 array: len: 2 stride: 1 fieldset/SR_ADV: extends: SR_2CH_CMP description: status register fields: - name: CCIF description: Capture/compare x (x=1-4) interrupt flag bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: BIF description: Break x (x=1,2) interrupt flag bit_offset: 7 bit_size: 1 array: len: 2 stride: 1 - name: CCOF description: Capture/Compare x (x=1-4) overcapture flag bit_offset: 9 bit_size: 1 array: len: 4 stride: 1 - name: SBIF description: System break interrupt flag bit_offset: 13 bit_size: 1 - name: CCIF5 description: Capture/compare 5 interrupt flag bit_offset: 16 bit_size: 1 - name: CCIF6 description: Capture/compare 6 interrupt flag bit_offset: 17 bit_size: 1 - name: IDXIF description: Index interrupt flag bit_offset: 20 bit_size: 1 - name: DIRIF description: Direction change interrupt flag bit_offset: 21 bit_size: 1 - name: IERRIF description: Index error interrupt flag bit_offset: 22 bit_size: 1 - name: TERRIF description: Transition error interrupt flag bit_offset: 23 bit_size: 1 fieldset/SR_CORE: description: status register fields: - name: UIF description: Update interrupt flag bit_offset: 0 bit_size: 1 fieldset/SR_GP16: extends: SR_CORE description: status register fields: - name: CCIF description: Capture/compare x (x=1-4) interrupt flag bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - name: CCOF description: Capture/Compare x (x=1-4) overcapture flag bit_offset: 9 bit_size: 1 array: len: 4 stride: 1 - name: IDXIF description: Index interrupt flag bit_offset: 20 bit_size: 1 - name: DIRIF description: Direction change interrupt flag bit_offset: 21 bit_size: 1 - name: IERRIF description: Index error interrupt flag bit_offset: 22 bit_size: 1 - name: TERRIF description: Transition error interrupt flag bit_offset: 23 bit_size: 1 fieldset/TISEL_1CH: description: input selection register fields: - name: TISEL description: Selects TIM_TIx (x=1) input bit_offset: 0 bit_size: 4 array: len: 1 stride: 8 fieldset/TISEL_2CH: extends: TISEL_1CH description: input selection register fields: - name: TISEL description: Selects TIM_TIx (x=1-2) input bit_offset: 0 bit_size: 4 array: len: 2 stride: 8 fieldset/TISEL_GP16: description: input selection register fields: - name: TISEL description: Selects TIM_TIx (x=1-4) input bit_offset: 0 bit_size: 4 array: len: 4 stride: 8 enum/BKBID: bit_size: 1 variants: - name: Input description: Break input tim_brk in input mode value: 0 - name: Bidirectional description: Break input tim_brk in bidirectional mode value: 1 enum/BKDSRM: bit_size: 1 variants: - name: Armed description: Break input tim_brk is armed value: 0 - name: Disarmed description: Break input tim_brk is disarmed value: 1 enum/BKINP: bit_size: 1 variants: - name: NotInverted description: input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1) value: 0 - name: Inverted description: input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1) value: 1 enum/BKP: bit_size: 1 variants: - name: ActiveLow description: Break input tim_brk is active low value: 0 - name: ActiveHigh description: Break input tim_brk is active high value: 1 enum/CCDS: bit_size: 1 variants: - name: OnCompare description: CCx DMA request sent when CCx event occurs value: 0 - name: OnUpdate description: CCx DMA request sent when update event occurs value: 1 enum/CCMR_Input_CCS: bit_size: 2 variants: - name: TI4 description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' value: 1 - name: TI3 description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) value: 2 - name: TRC description: CCx channel is configured as input, ICx is mapped on TRC value: 3 enum/CCMR_Output_CCS: bit_size: 2 variants: - name: Output description: CCx channel is configured as output value: 0 enum/CKD: bit_size: 2 variants: - name: Div1 description: t_DTS = t_CK_INT value: 0 - name: Div2 description: t_DTS = 2 × t_CK_INT value: 1 - name: Div4 description: t_DTS = 4 × t_CK_INT value: 2 enum/CMS: bit_size: 2 variants: - name: EdgeAligned description: The counter counts up or down depending on the direction bit value: 0 - name: CenterAligned1 description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. value: 1 - name: CenterAligned2 description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. value: 2 - name: CenterAligned3 description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. value: 3 enum/DBSS: bit_size: 4 variants: - name: Update description: Update value: 1 - name: CC1 description: CC1 value: 2 - name: CC2 description: CC2 value: 3 - name: CC3 description: CC3 value: 4 - name: CC4 description: CC4 value: 5 - name: COM description: COM value: 6 - name: Trigger description: Trigger value: 7 enum/DIR: bit_size: 1 variants: - name: Up description: Counter used as upcounter value: 0 - name: Down description: Counter used as downcounter value: 1 enum/DTAE: bit_size: 1 variants: - name: Identical description: Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register value: 0 - name: Distinct description: Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits. value: 1 enum/ETP: bit_size: 1 variants: - name: NotInverted description: ETR is noninverted, active at high level or rising edge value: 0 - name: Inverted description: ETR is inverted, active at low level or falling edge value: 1 enum/ETPS: bit_size: 2 variants: - name: Div1 description: Prescaler OFF value: 0 - name: Div2 description: ETRP frequency divided by 2 value: 1 - name: Div4 description: ETRP frequency divided by 4 value: 2 - name: Div8 description: ETRP frequency divided by 8 value: 3 enum/FIDX: bit_size: 1 variants: - name: AlwaysActive description: Index is always active value: 0 - name: FirstOnly description: the first Index only resets the counter value: 1 enum/FilterValue: bit_size: 4 variants: - name: NoFilter description: No filter, sampling is done at fDTS value: 0 - name: FCK_INT_N2 description: fSAMPLING=fCK_INT, N=2 value: 1 - name: FCK_INT_N4 description: fSAMPLING=fCK_INT, N=4 value: 2 - name: FCK_INT_N8 description: fSAMPLING=fCK_INT, N=8 value: 3 - name: FDTS_Div2_N6 description: fSAMPLING=fDTS/2, N=6 value: 4 - name: FDTS_Div2_N8 description: fSAMPLING=fDTS/2, N=8 value: 5 - name: FDTS_Div4_N6 description: fSAMPLING=fDTS/4, N=6 value: 6 - name: FDTS_Div4_N8 description: fSAMPLING=fDTS/4, N=8 value: 7 - name: FDTS_Div8_N6 description: fSAMPLING=fDTS/8, N=6 value: 8 - name: FDTS_Div8_N8 description: fSAMPLING=fDTS/8, N=8 value: 9 - name: FDTS_Div16_N5 description: fSAMPLING=fDTS/16, N=5 value: 10 - name: FDTS_Div16_N6 description: fSAMPLING=fDTS/16, N=6 value: 11 - name: FDTS_Div16_N8 description: fSAMPLING=fDTS/16, N=8 value: 12 - name: FDTS_Div32_N5 description: fSAMPLING=fDTS/32, N=5 value: 13 - name: FDTS_Div32_N6 description: fSAMPLING=fDTS/32, N=6 value: 14 - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 enum/GC5C: bit_size: 1 variants: - name: NoEffect description: No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3) value: 0 - name: LogicalAND description: TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF value: 1 enum/IBLK: bit_size: 2 variants: - name: AlwaysActive description: Index always active value: 0 - name: CC3P description: Index disabled when tim_ti3 input is active, as per CC3P bitfield value: 1 - name: CC4P description: Index disabled when tim_ti4 input is active, as per CC4P bitfield value: 2 enum/IDIR: bit_size: 2 variants: - name: Both description: Index resets the counter whatever the direction value: 0 - name: Up description: Index resets the counter when up-counting only value: 1 - name: Down description: Index resets the counter when down-counting only value: 2 enum/LOCK: bit_size: 2 variants: - name: Disabled description: No bit is write protected value: 0 - name: Level1 description: DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written value: 1 - name: Level2 description: LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written. value: 2 - name: Level3 description: LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written. value: 3 enum/MMS: bit_size: 4 variants: - name: Reset description: The UG bit from the TIMx_EGR register is used as trigger output value: 0 - name: Enable description: The counter enable signal, CNT_EN, is used as trigger output value: 1 - name: Update description: The update event is selected as trigger output value: 2 - name: ComparePulse description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred value: 3 - name: CompareOC1 description: OC1REF signal is used as trigger output value: 4 - name: CompareOC2 description: OC2REF signal is used as trigger output value: 5 - name: CompareOC3 description: OC3REF signal is used as trigger output value: 6 - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 - name: EncoderClockOutput description: The encoder clock signal is used as trigger output value: 8 enum/MMS2: bit_size: 4 variants: - name: Reset description: The UG bit from the TIMx_EGR register is used as TRGO2 value: 0 - name: Enable description: The counter enable signal, CNT_EN, is used as TRGO2 value: 1 - name: Update description: The update event is selected as TRGO2 value: 2 - name: ComparePulse description: TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred value: 3 - name: CompareOC1 description: OC1REF signal is used as TRGO2 value: 4 - name: CompareOC2 description: OC2REF signal is used as TRGO2 value: 5 - name: CompareOC3 description: OC3REF signal is used as TRGO2 value: 6 - name: CompareOC4 description: OC4REF signal is used as TRGO2 value: 7 - name: CompareOC5 description: OC5REF signal is used as TRGO2 value: 8 - name: CompareOC6 description: OC6REF signal is used as TRGO2 value: 9 - name: ComparePulse_OC4 description: OC4REF rising or falling edges generate pulses on TRGO2 value: 10 - name: ComparePulse_OC6 description: OC6REF rising or falling edges generate pulses on TRGO2 value: 11 - name: ComparePulse_OC4_Or_OC6_Rising description: OC4REF or OC6REF rising edges generate pulses on TRGO2 value: 12 - name: ComparePulse_OC4_Rising_Or_OC6_Falling description: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 value: 13 - name: ComparePulse_OC5_Or_OC6_Rising description: OC5REF or OC6REF rising edges generate pulses on TRGO2 value: 14 - name: ComparePulse_OC5_Rising_Or_OC6_Falling description: OC5REF rising or OC6REF falling edges generate pulses on TRGO2 value: 15 enum/MSM: bit_size: 1 variants: - name: NoSync description: No action value: 0 - name: Sync description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. value: 1 enum/OCCS: bit_size: 1 variants: - name: Input description: tim_ocref_clr_int is connected to the tim_ocref_clr input value: 0 - name: ETRF description: tim_ocref_clr_int is connected to tim_etrf value: 1 enum/OCM: bit_size: 4 variants: - name: Frozen description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs value: 0 - name: ActiveOnMatch description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register value: 1 - name: InactiveOnMatch description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register value: 2 - name: Toggle description: OCyREF toggles when TIMx_CNT=TIMx_CCRy value: 3 - name: ForceInactive description: OCyREF is forced low value: 4 - name: ForceActive description: OCyREF is forced high value: 5 - name: PwmMode1 description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active value: 6 - name: PwmMode2 description: Inversely to PwmMode1 value: 7 - name: Retrigerrable_OPM_Mode_1 description: |- In up-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update. value: 8 - name: Retrigerrable_OPM_Mode_2 description: |- In up-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down- counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. value: 9 - name: _reserved1 description: _reserved1 value: 10 - name: _reserved2 description: _reserved2 value: 11 - name: Combined_PWM_Mode_1 description: |- tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref. value: 12 - name: Combined_PWM_Mode_2 description: |- tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref. value: 13 - name: Asymmetric_PWM_Mode_1 description: |- tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down. value: 14 - name: Asymmetric_PWM_Mode_2 description: |- tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down. value: 15 enum/OSSI: bit_size: 1 variants: - name: Disabled description: When inactive, OC/OCN outputs are disabled value: 0 - name: IdleLevel description: When inactive, OC/OCN outputs are forced to idle level value: 1 enum/OSSR: bit_size: 1 variants: - name: Disabled description: When inactive, OC/OCN outputs are disabled value: 0 - name: IdleLevel description: When inactive, OC/OCN outputs are enabled with their inactive level value: 1 enum/SMS: bit_size: 4 variants: - name: Disabled description: Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock. value: 0 - name: Encoder_Mode_1 description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. value: 1 - name: Encoder_Mode_2 description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. value: 2 - name: Encoder_Mode_3 description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. value: 3 - name: Reset_Mode description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. value: 4 - name: Gated_Mode description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. value: 5 - name: Trigger_Mode description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. value: 6 - name: Ext_Clock_Mode description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. value: 7 - name: Combined_Reset_Trigger description: Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter. value: 8 - name: Combined_Gated_Trigger description: The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops and is reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. value: 9 - name: Encoder_Up_X2 description: Encoder mode, Clock plus direction, x2 mode. value: 10 - name: Encoder_Up_X1 description: Encoder mode, Clock plus direction, x1 mode, tim_ti2fp2 edge sensitivity is set by CC2P value: 11 - name: Encoder_Dir_X2 description: Encoder mode, Directional Clock, x2 mode. value: 12 - name: Encoder_Dir_X1 description: Encoder mode, Directional Clock, x1 mode, tim_ti1fp1 and tim_ti2fp2 edge sensitivity is set by CC1P and CC2P. value: 13 - name: Quadrature_Encoder_Mode_X1_TI1PF1 description: Quadrature encoder mode, x1 mode, counting on tim_ti1fp1 edges only, edge sensitivity is set by CC1P. value: 14 - name: Quadrature_Encoder_Mode_X1_TI2PF2 description: Quadrature encoder mode, x1 mode, counting on tim_ti2fp2 edges only, edge sensitivity is set by CC2P. value: 15 enum/SMSPS: bit_size: 1 variants: - name: Update description: The transfer is triggered by the Timer’s Update event value: 0 - name: Index description: The transfer is triggered by the Index event value: 1 enum/TI1S: bit_size: 1 variants: - name: Normal description: The TIMx_CH1 pin is connected to TI1 input value: 0 - name: XOR description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input value: 1 enum/TS: bit_size: 5 variants: - name: ITR0 description: Internal Trigger 0 value: 0 - name: ITR1 description: Internal Trigger 1 value: 1 - name: ITR2 description: Internal Trigger 2 value: 2 - name: ITR3 description: Internal Trigger 3 value: 3 - name: TI1F_ED description: TI1 Edge Detector value: 4 - name: TI1FP1 description: Filtered Timer Input 1 value: 5 - name: TI2FP2 description: Filtered Timer Input 2 value: 6 - name: ETRF description: External Trigger input value: 7 - name: ITR4 description: Internal Trigger 4 value: 8 - name: ITR5 description: Internal Trigger 5 value: 9 - name: ITR6 description: Internal Trigger 6 value: 10 - name: ITR7 description: Internal Trigger 7 value: 11 - name: ITR8 description: Internal Trigger 8 value: 12 - name: ITR9 description: Internal Trigger 9 value: 13 - name: ITR10 description: Internal Trigger 10 value: 14 - name: ITR11 description: Internal Trigger 11 value: 15 - name: ITR12 description: Internal Trigger 12 value: 16 - name: ITR13 description: Internal Trigger 13 value: 17 - name: ITR14 description: Internal Trigger 14 value: 18 - name: ITR15 description: Internal Trigger 15 value: 19 enum/URS: bit_size: 1 variants: - name: AnyEvent description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request value: 0 - name: CounterOnly description: Only counter overflow/underflow generates an update interrupt or DMA request value: 1