---
block/PWR:
  description: Power control
  items:
    - name: CR
      description: power control register
      byte_offset: 0
      fieldset: CR
    - name: CSR
      description: power control/status register
      byte_offset: 4
      fieldset: CSR
fieldset/CR:
  description: power control register
  fields:
    - name: LPDS
      description: Low-power deep sleep
      bit_offset: 0
      bit_size: 1
    - name: PDDS
      description: Power down deepsleep
      bit_offset: 1
      bit_size: 1
      enum: PDDS
    - name: CWUF
      description: Clear wakeup flag
      bit_offset: 2
      bit_size: 1
    - name: CSBF
      description: Clear standby flag
      bit_offset: 3
      bit_size: 1
    - name: PVDE
      description: Power voltage detector enable
      bit_offset: 4
      bit_size: 1
    - name: PLS
      description: PVD level selection
      bit_offset: 5
      bit_size: 3
    - name: DBP
      description: Disable backup domain write protection
      bit_offset: 8
      bit_size: 1
    - name: FPDS
      description: Flash power down in Stop mode
      bit_offset: 9
      bit_size: 1
fieldset/CSR:
  description: power control/status register
  fields:
    - name: WUF
      description: Wakeup flag
      bit_offset: 0
      bit_size: 1
    - name: SBF
      description: Standby flag
      bit_offset: 1
      bit_size: 1
    - name: PVDO
      description: PVD output
      bit_offset: 2
      bit_size: 1
    - name: BRR
      description: Backup regulator ready
      bit_offset: 3
      bit_size: 1
    - name: EWUP
      description: Enable WKUP pin
      bit_offset: 8
      bit_size: 1
    - name: BRE
      description: Backup regulator enable
      bit_offset: 9
      bit_size: 1
enum/PDDS:
  bit_size: 1
  variants:
    - name: STOP_MODE
      description: Enter Stop mode when the CPU enters deepsleep
      value: 0
    - name: STANDBY_MODE
      description: Enter Standby mode when the CPU enters deepsleep
      value: 1