block/SYSCFG: description: System configuration controller items: - name: CFGR1 description: configuration register 1 byte_offset: 0 fieldset: CFGR1 - name: EXTICR description: external interrupt configuration register 1 array: len: 4 stride: 4 byte_offset: 8 fieldset: EXTICR - name: CFGR2 description: configuration register 2 byte_offset: 24 fieldset: CFGR2 fieldset/CFGR1: description: configuration register 1 fields: - name: MEM_MODE description: Memory mapping selection bits bit_offset: 0 bit_size: 2 enum: MEM_MODE - name: PA11_PA12_RMP description: | PA11 and PA12 remapping bit for small packages (28 and 20 pins) 0: Pin pair PA9/PA10 mapped on the pins 1: Pin pair PA11/PA12 mapped instead of PA9/PA10 bit_offset: 4 bit_size: 1 - name: IR_MOD description: IR Modulation Envelope signal selection bit_offset: 6 bit_size: 2 enum: IR_MOD - name: ADC_DMA_RMP description: | ADC DMA remapping bit 0: ADC DMA request mapped on DMA channel 1 1: ADC DMA request mapped on DMA channel 2 bit_offset: 8 bit_size: 1 - name: USART1_TX_DMA_RMP description: | USART1_TX DMA remapping bit 0: USART1_TX DMA request mapped on DMA channel 2 1: USART1_TX DMA request mapped on DMA channel 4 bit_offset: 9 bit_size: 1 - name: USART1_RX_DMA_RMP description: | USART1_RX DMA request remapping bit 0: USART1_RX DMA request mapped on DMA channel 3 1: USART1_RX DMA request mapped on DMA channel 5 bit_offset: 10 bit_size: 1 - name: TIM16_DMA_RMP description: | TIM16 DMA request remapping bit 0: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4 bit_offset: 11 bit_size: 1 - name: TIM17_DMA_RMP description: | TIM17 DMA request remapping bit 0: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2 bit_offset: 12 bit_size: 1 - name: TIM16_DMA_RMP2 description: | TIM16 alternate DMA request remapping bit 0: TIM16 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6 bit_offset: 13 bit_size: 1 - name: TIM17_DMA_RMP2 description: | TIM17 alternate DMA request remapping bit 0: TIM17 DMA request mapped according to TIM16_DMA_RMP bit 1: TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7 bit_offset: 14 bit_size: 1 - name: I2C_PB6_FMP description: | Fast Mode Plus (FM plus) driving capability activation bits. 0: PB6 pin operate in standard mode 1: I2C FM+ mode enabled on PB6 and the Speed control is bypassed bit_offset: 16 bit_size: 1 enum: FMP - name: I2C_PB7_FMP description: | Fast Mode Plus (FM+) driving capability activation bits. 0: PB7 pin operate in standard mode 1: I2C FM+ mode enabled on PB7 and the Speed control is bypassed bit_offset: 17 bit_size: 1 enum: FMP - name: I2C_PB8_FMP description: | Fast Mode Plus (FM+) driving capability activation bits. 0: PB8 pin operate in standard mode 1: I2C FM+ mode enabled on PB8 and the Speed control is bypassed bit_offset: 18 bit_size: 1 enum: FMP - name: I2C_PB9_FMP description: | Fast Mode Plus (FM+) driving capability activation bits. 0: PB9 pin operate in standard mode 1: I2C FM+ mode enabled on PB9 and the Speed control is bypassed bit_offset: 19 bit_size: 1 enum: FMP - name: I2C1_FMP description: | FM+ driving capability activation for I2C1 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers bit_offset: 20 bit_size: 1 enum: FMP - name: I2C2_FMP description: | FM+ driving capability activation for I2C2 0: FM+ mode is controlled by I2C_Pxx_FMP bits only 1: FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers bit_offset: 21 bit_size: 1 enum: FMP - name: I2C_PA9_FMP description: | Fast Mode Plus (FM+) driving capability activation bits 0: PA9 pin operate in standard mode 1: I2C FM+ mode enabled on PA9 and the Speed control is bypassed bit_offset: 22 bit_size: 1 enum: FMP - name: I2C_PA10_FMP description: | Fast Mode Plus (FM+) driving capability activation bits 0: PA10 pin operate in standard mode 1: I2C FM+ mode enabled on PA10 and the Speed control is bypassed bit_offset: 23 bit_size: 1 enum: FMP - name: SPI2_DMA_RMP description: | SPI2 DMA request remapping bit 0: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively 1: SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 24 bit_size: 1 - name: USART2_DMA_RMP description: | USART2 DMA request remapping bit 0: USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively 1: USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively bit_offset: 25 bit_size: 1 - name: USART3_DMA_RMP description: | USART3 DMA request remapping bit 0: USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0) 1: USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively bit_offset: 26 bit_size: 1 - name: I2C1_DMA_RMP description: | I2C1 DMA request remapping bit 0: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively 1: I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively bit_offset: 27 bit_size: 1 - name: TIM1_DMA_RMP description: | TIM1 DMA request remapping bit 0: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively 1: TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 bit_offset: 28 bit_size: 1 - name: TIM2_DMA_RMP description: | TIM2 DMA request remapping bit 0: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively 1: TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 bit_offset: 29 bit_size: 1 - name: TIM3_DMA_RMP description: | TIM3 DMA request remapping bit 0: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 1: TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 bit_offset: 30 bit_size: 1 fieldset/CFGR2: description: configuration register 2 fields: - name: LOCKUP_LOCK description: Cortex-M0 LOCKUP bit enable bit bit_offset: 0 bit_size: 1 - name: SRAM_PARITY_LOCK description: SRAM parity lock bit bit_offset: 1 bit_size: 1 - name: PVD_LOCK description: PVD lock enable bit bit_offset: 2 bit_size: 1 - name: SRAM_PEF description: SRAM parity flag bit_offset: 8 bit_size: 1 fieldset/EXTICR: description: external interrupt configuration register 1 fields: - name: EXTI description: EXTI configuration bits bit_offset: 0 bit_size: 4 array: len: 4 stride: 4 enum/FMP: bit_size: 1 variants: - name: Standard description: PA10 pin operate in standard mode value: 0 - name: FMP description: I2C FM+ mode enabled on PA10 and the Speed control is bypassed value: 1 enum/IR_MOD: bit_size: 2 variants: - name: TIM16 description: TIM16 selected value: 0 - name: USART1 description: USART1 selected value: 1 - name: USART4 description: USART4 selected value: 2 enum/MEM_MODE: bit_size: 2 variants: - name: MainFlash description: Main Flash memory mapped at 0x0000_0000 value: 0 - name: SystemFlash description: System Flash memory mapped at 0x0000_0000 value: 1 - name: MainFlash2 description: Main Flash memory mapped at 0x0000_0000 value: 2 - name: SRAM description: Embedded SRAM mapped at 0x0000_0000 value: 3