block/ADC: description: Analog to Digital Converter items: - name: ISR description: interrupt and status register byte_offset: 0 fieldset: ISR - name: IER description: interrupt enable register byte_offset: 4 fieldset: IER - name: CR description: control register byte_offset: 8 fieldset: CR - name: CFGR description: configuration register 1 byte_offset: 12 fieldset: CFGR - name: CFGR2 description: configuration register 2 byte_offset: 16 fieldset: CFGR2 - name: SMPR description: sampling time register 1-2 array: len: 2 stride: 4 byte_offset: 20 fieldset: SMPR - name: PCSEL description: pre channel selection register byte_offset: 28 fieldset: PCSEL - name: SQR1 description: group regular sequencer ranks register 1 byte_offset: 48 fieldset: SQR1 - name: SQR2 description: group regular sequencer ranks register 2 byte_offset: 52 fieldset: SQR2 - name: SQR3 description: group regular sequencer ranks register 3 byte_offset: 56 fieldset: SQR3 - name: SQR4 description: group regular sequencer ranks register 4 byte_offset: 60 fieldset: SQR4 - name: DR description: group regular conversion data register byte_offset: 64 access: Read fieldset: DR - name: JSQR description: group injected sequencer register byte_offset: 76 fieldset: JSQR - name: OFR description: offset number 1-4 register array: len: 4 stride: 4 byte_offset: 96 fieldset: OFR - name: GCOMP description: gain compensation register byte_offset: 112 fieldset: ADC_GCOMP - name: JDR description: group injected sequencer rank 1-4 register array: len: 4 stride: 4 byte_offset: 128 access: Read fieldset: JDR - name: AWD2CR description: analog watchdog 2 configuration register byte_offset: 160 fieldset: AWD2CR - name: AWD3CR description: analog watchdog 3 configuration register byte_offset: 164 fieldset: AWD3CR - name: LTR1 description: ADC watchdog threshold register 1. byte_offset: 168 fieldset: LTR1 - name: HTR1 description: ADC watchdog threshold register 1. byte_offset: 172 fieldset: HTR1 - name: LTR2 description: ADC watchdog lower threshold register 2. byte_offset: 176 fieldset: LTR2 - name: HTR2 description: ADC watchdog higher threshold register 2. byte_offset: 180 fieldset: HTR2 - name: LTR3 description: ADC watchdog lower threshold register 3. byte_offset: 184 fieldset: LTR3 - name: HTR3 description: ADC watchdog higher threshold register 3. byte_offset: 188 fieldset: HTR3 - name: DIFSEL description: channel differential or single-ended mode selection register byte_offset: 192 fieldset: DIFSEL - name: CALFACT description: calibration factors register byte_offset: 196 fieldset: CALFACT - name: CALFACT2 description: Calibration Factor register 2 byte_offset: 200 fieldset: CALFACT2 fieldset/AWD2CR: description: analog watchdog 2 configuration register fields: - name: AWD2CH description: analog watchdog 2 monitored channel selection bit_offset: 0 bit_size: 1 array: len: 20 stride: 1 fieldset/AWD3CR: description: ADC analog watchdog 3 configuration register. fields: - name: AWD3CH description: analog watchdog 3 monitored channel selection bit_offset: 1 bit_size: 1 array: len: 20 stride: 1 fieldset/CALFACT: description: ADC user control register. fields: - name: I_APB_ADDR description: Delayed write access address This bitfield contains the address that is being written during delayed write accesses. bit_offset: 0 bit_size: 8 - name: I_APB_DATA description: Delayed write access data This bitfield contains the data that are being written during delayed write accesses. bit_offset: 8 bit_size: 8 - name: VALIDITY description: Delayed write access status bit This bit indicates the communication status between the ADC digital and analog blocks. bit_offset: 16 bit_size: 1 - name: LATCH_COEF description: Calibration factor latch enable bit This bit latches the calibration factor in the CALFACT[31:0] bits. bit_offset: 24 bit_size: 1 - name: CAPTURE_COEF description: Calibration factor capture enable bit This bit enables the internal calibration factor capture. bit_offset: 25 bit_size: 1 fieldset/CALFACT2: description: ADC calibration factor register. fields: - name: CALFACT description: 'Linearity or offset calibration factor These bits can be written either by hardware or by software. They contain the 32-bit offset or linearity calibration factor. When CAPTURE_COEF is set to 1, the calibration factor of the analog block is read back and stored in CALFACT[31:0], indexed by CALINDEX[3:0] bits. When LATCH_COEF is set to 1, the calibration factor of the analog block is updated with the value programmed in CALFACT[31:0], indexed by CALINDEX[3:0] bits. To read all calibration factors, perform nine accesses to the ADC_CALFACT2 register. To write all calibration factors, perform eight accesses to the ADC_CALFACT2 register. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).' bit_offset: 0 bit_size: 32 fieldset/CFGR: description: configuration register 1 fields: - name: DMNGT description: 'Data management configuration This bit is set and cleared by software to select how the ADC interface output data are managed. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 0 bit_size: 2 - name: RES description: 'Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 2 bit_size: 2 - name: EXTSEL description: 'External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Refer to the ADC external trigger for regular channels in signals for details on trigger mapping. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 5 bit_size: 5 - name: EXTEN description: 'External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 10 bit_size: 2 - name: OVRMOD description: 'Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 12 bit_size: 1 - name: CONT description: 'Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 13 bit_size: 1 - name: AUTDLY description: 'Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 14 bit_size: 1 - name: DISCEN description: 'Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 16 bit_size: 1 - name: DISCNUM description: 'Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 17 bit_size: 3 - name: JDISCEN description: 'Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.' bit_offset: 20 bit_size: 1 - name: AWD1SGL description: 'Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 22 bit_size: 1 - name: AWD1EN description: 'Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 23 bit_size: 1 - name: JAWD1EN description: 'Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).' bit_offset: 24 bit_size: 1 - name: JAUTO description: 'Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing).' bit_offset: 25 bit_size: 1 - name: AWD1CH description: 'Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... Others: Reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. Software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 26 bit_size: 5 fieldset/CFGR2: description: configuration register 2 fields: - name: ROVSE description: 'Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 0 bit_size: 1 - name: JOVSE description: 'Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 1 bit_size: 1 - name: OVSS description: 'Oversampling right shift This bit field is set and cleared by software to define the right shifting applied to the raw oversampling result. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 5 bit_size: 4 - name: TROVS description: 'Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 9 bit_size: 1 - name: ROVSM description: 'Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 10 bit_size: 1 - name: BULB description: 'Bulb sampling mode This bit is set and cleared by software to select the bulb sampling mode. SMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 13 bit_size: 1 - name: SWTRIG description: 'Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 14 bit_size: 1 - name: SMPTRIG description: 'Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN[1:0] bits must be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN[1:0] bits is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 15 bit_size: 1 - name: OSR description: 'Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2: 3x ... 1023: 1024x Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 16 bit_size: 10 - name: LFTRIG description: 'Low-frequency trigger This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 27 bit_size: 1 - name: LSHIFT description: 'Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 28 bit_size: 4 fieldset/CR: description: ADC control register. fields: - name: ADEN description: 'ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator).' bit_offset: 0 bit_size: 1 - name: ADDIS description: 'ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 1 bit_size: 1 - name: ADSTART description: 'ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN[1:0], a conversion starts immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware:. in Single conversion mode (CONT = 0, DISCEN = 0) when software trigger is selected (EXTEN[1:0] = 0x0): at the assertion of the end of regular conversion sequence (EOS) flag. In Discontinuous conversion mode (CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN[1:0] = 0x0): at the end of conversion (EOC) flag. in all other cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).' bit_offset: 2 bit_size: 1 - name: JADSTART description: 'ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN[1:0], a conversion starts immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the end of injected conversion sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time as JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In Auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared).' bit_offset: 3 bit_size: 1 - name: ADSTP description: 'ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).' bit_offset: 4 bit_size: 1 - name: JADSTP description: 'ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC). In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP).' bit_offset: 5 bit_size: 1 - name: ADCALLIN description: 'Linearity calibration This bit is set and cleared by software to enable the linearity calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).' bit_offset: 16 bit_size: 1 - name: CALINDEX description: 'Calibration factor This bitfield controls the calibration factor to be read or written. Calibration index 0 is dedicated to single-ended and differential offsets, calibration index 1 to 7 to the linearity calibration factors, and index 8 to the internal offset: Others: Reserved, must not be used Note: ADC_CALFACT2[31:0] correspond to the location of CALINDEX[3:0] calibration factor data (see for details).' bit_offset: 24 bit_size: 4 - name: ADVREGEN description: ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). bit_offset: 28 bit_size: 1 - name: DEEPPWD description: 'Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).' bit_offset: 29 bit_size: 1 - name: ADCAL description: 'ADC calibration This bit is set by software to start the ADC calibration. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0.' bit_offset: 31 bit_size: 1 fieldset/DIFSEL: description: ADC differential mode selection register. fields: - name: DIFSEL description: 'Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow selecting if a channel is configured as single ended or differential mode. DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).' bit_offset: 0 bit_size: 20 fieldset/DR: description: ADC regular Data Register. fields: - name: RDATA description: Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in. bit_offset: 0 bit_size: 32 fieldset/ADC_GCOMP: description: ADC gain compensation register. fields: - name: GCOMPCOEFF description: 'Gain compensation coefficient These bits are set and cleared by software to program the gain compensation coefficient. ... ... The coefficient is divided by 4096 to get the gain factor ranging from 0 to 3.999756. Note: This gain compensation is only applied when GCOMP bit of ADCx_CFGR2 register is 1.' bit_offset: 0 bit_size: 14 - name: GCOMP description: 'Gain compensation mode This bit is set and cleared by software to enable the gain compensation mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 31 bit_size: 1 fieldset/HTR1: description: ADC watchdog threshold register 1. fields: - name: HTR1 description: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). bit_offset: 0 bit_size: 25 - name: AWDFILT1 description: 'Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 29 bit_size: 3 fieldset/HTR2: description: ADC watchdog higher threshold register 2. fields: - name: HTR2 description: Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). bit_offset: 0 bit_size: 25 fieldset/HTR3: description: ADC watchdog higher threshold register 3. fields: - name: HTR3 description: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). bit_offset: 0 bit_size: 25 fieldset/IER: description: ADC interrupt enable register. fields: - name: ADRDYIE description: 'ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 0 bit_size: 1 - name: EOSMPIE description: 'End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 1 bit_size: 1 - name: EOCIE description: 'End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 2 bit_size: 1 - name: EOSIE description: 'End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 3 bit_size: 1 - name: OVRIE description: 'Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 4 bit_size: 1 - name: JEOCIE description: 'End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: Software is allowed to write this bit only when JADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 5 bit_size: 1 - name: JEOSIE description: 'End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: Software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing).' bit_offset: 6 bit_size: 1 - name: AWD1IE description: 'Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 7 bit_size: 1 - name: AWD2IE description: 'Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 8 bit_size: 1 - name: AWD3IE description: 'Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: Software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 9 bit_size: 1 fieldset/ISR: description: ADC interrupt and status register. fields: - name: ADRDY description: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. bit_offset: 0 bit_size: 1 - name: EOSMP description: End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase. bit_offset: 1 bit_size: 1 - name: EOC description: End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. bit_offset: 2 bit_size: 1 - name: EOS description: End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it. bit_offset: 3 bit_size: 1 - name: OVR description: ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it. bit_offset: 4 bit_size: 1 - name: JEOC description: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register. bit_offset: 5 bit_size: 1 - name: JEOS description: Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it. bit_offset: 6 bit_size: 1 - name: AWD1 description: Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_LTR1, & ADC_HTR1 register. It is cleared by software. writing 1 to it. bit_offset: 7 bit_size: 1 - name: AWD2 description: Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_LTR2 & ADC_HTR2 register. It is cleared by software writing 1 to it. bit_offset: 8 bit_size: 1 - name: AWD3 description: Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_LTR3 & ADC_HTR3 register. It is cleared by software writing 1 to it. bit_offset: 9 bit_size: 1 - name: LDORDY description: ADC voltage regulator ready This bit is set by hardware. It indicates that the ADC internal supply is ready. The ADC is available after tADCVREG_SETUP time. bit_offset: 12 bit_size: 1 fieldset/JDR: description: ADC injected data register. fields: - name: JDATA description: Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in. bit_offset: 0 bit_size: 32 fieldset/JSQR: description: ADC injected sequence register. fields: - name: JL description: 'Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.' bit_offset: 0 bit_size: 2 - name: JEXTSEL description: 'External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Refer to the ADC external trigger for injected channels in internal signals for details on trigger mapping. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing.' bit_offset: 2 bit_size: 5 - name: JEXTEN description: group injected external trigger polarity bit_offset: 7 bit_size: 2 - name: JSQ1 description: group injected sequencer rank 1-4 bit_offset: 9 bit_size: 5 array: len: 4 stride: 6 fieldset/LTR1: description: ADC watchdog threshold register 1. fields: - name: LTR1 description: Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). bit_offset: 0 bit_size: 25 fieldset/LTR2: description: ADC watchdog lower threshold register 2. fields: - name: LTR2 description: Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). bit_offset: 0 bit_size: 25 fieldset/LTR3: description: ADC watchdog lower threshold register 3. fields: - name: LTR3 description: Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). bit_offset: 0 bit_size: 25 fieldset/OFR: description: offset number x register fields: - name: OFFSET description: 'Data offset y for the channel programmed into OFFSETy_CH[4:0] bits These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (regular or injected). The channel to which the data offset y applies must be programmed to the OFFSETy_CH[4:0] bits. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[21:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offsets (OFFSETy) point to the same channel, only the offset with the lowest y value is considered for the subtraction. For example, if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[25:0] that is subtracted when converting channel 4.' bit_offset: 0 bit_size: 24 - name: POSOFF description: 'offset sign This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 24 bit_size: 1 - name: USAT description: 'Unsigned saturation enable This bit is written by software to enable or disable the unsigned saturation feature. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 25 bit_size: 1 - name: SSAT description: 'Signed saturation enable This bit is written by software to enable or disable the Signed saturation feature. (see OFFSETy_CH, OVSS, LSHIFT, USAT, SSAT) for details). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).' bit_offset: 26 bit_size: 1 - name: OFFSET_CH description: 'Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into OFFSETy[25:0] bits applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If OFFSETy_EN bit is set, it is not allowed to select the same channel in different ADC_OFRy registers.' bit_offset: 27 bit_size: 5 fieldset/PCSEL: description: channel preselection register fields: - name: PCSEL description: Channel x (VINP[i]) pre selection bit_offset: 0 bit_size: 1 array: len: 20 stride: 1 fieldset/SMPR: description: sampling time register n fields: - name: SMP description: channel n * 10 + x sampling time bit_offset: 0 bit_size: 3 array: len: 10 stride: 3 fieldset/SQR1: description: group regular sequencer ranks register 1 fields: - name: L description: 'Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing).' bit_offset: 0 bit_size: 4 - name: SQ description: group regular sequencer rank 1-4 bit_offset: 6 bit_size: 5 array: len: 4 stride: 6 fieldset/SQR2: description: group regular sequencer ranks register 2 fields: - name: SQ description: group regular sequencer rank 5-9 bit_offset: 0 bit_size: 5 array: len: 5 stride: 6 fieldset/SQR3: description: group regular sequencer ranks register 3 fields: - name: SQ description: group regular sequencer rank 10-14 bit_offset: 0 bit_size: 5 array: len: 5 stride: 6 fieldset/SQR4: description: group regular sequencer ranks register 4 fields: - name: SQ description: group regular sequencer rank 15-16 bit_offset: 0 bit_size: 5 array: len: 2 stride: 6