block/TIM_BASIC: description: Basic timers items: - name: CR1 description: control register 1 byte_offset: 0 fieldset: CR1_BASIC - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2_BASIC - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER_BASIC - name: SR description: status register byte_offset: 16 fieldset: SR_BASIC - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR_BASIC - name: CNT description: counter byte_offset: 36 fieldset: CNT_BASIC - name: PSC description: prescaler byte_offset: 40 fieldset: PSC_BASIC - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 fieldset: ARR_BASIC - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 fieldset: ARR_DITHER_BASIC fieldset/ARR_BASIC: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 fieldset/ARR_DITHER_BASIC: description: auto-reload register (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: ARR description: Auto-reload value bit_offset: 4 bit_size: 16 fieldset/CNT_BASIC: description: counter fields: - name: CNT description: counter value bit_offset: 0 bit_size: 16 - name: UIFCPY description: UIF copy bit_offset: 31 bit_size: 1 fieldset/CR1_BASIC: description: control register 1 fields: - name: CEN description: Counter enable bit_offset: 0 bit_size: 1 - name: UDIS description: Update disable bit_offset: 1 bit_size: 1 - name: URS description: Update request source bit_offset: 2 bit_size: 1 enum: URS - name: OPM description: One-pulse mode enbaled bit_offset: 3 bit_size: 1 - name: ARPE description: Auto-reload preload enable bit_offset: 7 bit_size: 1 - name: UIFREMAP description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - name: DITHEN description: Dithering enable bit_offset: 12 bit_size: 1 fieldset/CR2_BASIC: description: control register 2 fields: - name: MMS description: Master mode selection bit_offset: 4 bit_size: 3 enum: MMS fieldset/DIER_BASIC: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 - name: UDE description: Update DMA request enable bit_offset: 8 bit_size: 1 fieldset/EGR_BASIC: description: event generation register fields: - name: UG description: Update generation bit_offset: 0 bit_size: 1 fieldset/PSC_BASIC: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 fieldset/SR_BASIC: description: status register fields: - name: UIF description: Update interrupt flag bit_offset: 0 bit_size: 1 enum/MMS: bit_size: 3 variants: - name: Reset description: The UG bit from the TIMx_EGR register is used as trigger output value: 0 - name: Enable description: The counter enable signal, CNT_EN, is used as trigger output value: 1 - name: Update description: The update event is selected as trigger output value: 2 - name: ComparePulse description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred value: 3 - name: CompareOC1 description: OC1REF signal is used as trigger output value: 4 - name: CompareOC2 description: OC2REF signal is used as trigger output value: 5 - name: CompareOC3 description: OC3REF signal is used as trigger output value: 6 - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 enum/URS: bit_size: 1 variants: - name: AnyEvent description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request value: 0 - name: CounterOnly description: Only counter overflow/underflow generates an update interrupt or DMA request value: 1