---
block/DMA2D:
  description: DMA2D
  items:
    - name: CR
      description: DMA2D control register
      byte_offset: 0
      fieldset: CR
    - name: ISR
      description: DMA2D Interrupt Status Register
      byte_offset: 4
      access: Read
      fieldset: ISR
    - name: IFCR
      description: DMA2D interrupt flag clear register
      byte_offset: 8
      fieldset: IFCR
    - name: FGMAR
      description: DMA2D foreground memory address register
      byte_offset: 12
      fieldset: FGMAR
    - name: FGOR
      description: DMA2D foreground offset register
      byte_offset: 16
      fieldset: FGOR
    - name: BGMAR
      description: DMA2D background memory address register
      byte_offset: 20
      fieldset: BGMAR
    - name: BGOR
      description: DMA2D background offset register
      byte_offset: 24
      fieldset: BGOR
    - name: FGPFCCR
      description: DMA2D foreground PFC control register
      byte_offset: 28
      fieldset: FGPFCCR
    - name: FGCOLR
      description: DMA2D foreground color register
      byte_offset: 32
      fieldset: FGCOLR
    - name: BGPFCCR
      description: DMA2D background PFC control register
      byte_offset: 36
      fieldset: BGPFCCR
    - name: BGCOLR
      description: DMA2D background color register
      byte_offset: 40
      fieldset: BGCOLR
    - name: FGCMAR
      description: DMA2D foreground CLUT memory address register
      byte_offset: 44
      fieldset: FGCMAR
    - name: BGCMAR
      description: DMA2D background CLUT memory address register
      byte_offset: 48
      fieldset: BGCMAR
    - name: OPFCCR
      description: DMA2D output PFC control register
      byte_offset: 52
      fieldset: OPFCCR
    - name: OCOLR
      description: DMA2D output color register
      byte_offset: 56
      fieldset: OCOLR
    - name: OMAR
      description: DMA2D output memory address register
      byte_offset: 60
      fieldset: OMAR
    - name: OOR
      description: DMA2D output offset register
      byte_offset: 64
      fieldset: OOR
    - name: NLR
      description: DMA2D number of line register
      byte_offset: 68
      fieldset: NLR
    - name: LWR
      description: DMA2D line watermark register
      byte_offset: 72
      fieldset: LWR
    - name: AMTCR
      description: DMA2D AXI master timer configuration register
      byte_offset: 76
      fieldset: AMTCR
fieldset/AMTCR:
  description: DMA2D AXI master timer configuration register
  fields:
    - name: EN
      description: Enable Enables the dead time functionality.
      bit_offset: 0
      bit_size: 1
      enum: EN
    - name: DT
      description: Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses.
      bit_offset: 8
      bit_size: 8
fieldset/BGCMAR:
  description: DMA2D background CLUT memory address register
  fields:
    - name: MA
      description: "Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned."
      bit_offset: 0
      bit_size: 32
fieldset/BGCOLR:
  description: DMA2D background color register
  fields:
    - name: BLUE
      description: "Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 0
      bit_size: 8
    - name: GREEN
      description: "Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 8
      bit_size: 8
    - name: RED
      description: "Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 16
      bit_size: 8
fieldset/BGMAR:
  description: DMA2D background memory address register
  fields:
    - name: MA
      description: "Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned."
      bit_offset: 0
      bit_size: 32
fieldset/BGOR:
  description: DMA2D background offset register
  fields:
    - name: LO
      description: "Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even."
      bit_offset: 0
      bit_size: 16
fieldset/BGPFCCR:
  description: DMA2D background PFC control register
  fields:
    - name: CM
      description: "Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
      bit_offset: 0
      bit_size: 4
      enum: BGPFCCR_CM
    - name: CCM
      description: "CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only."
      bit_offset: 4
      bit_size: 1
      enum: BGPFCCR_CCM
    - name: START
      description: "Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer)."
      bit_offset: 5
      bit_size: 1
      enum: BGPFCCR_START
    - name: CS
      description: "CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1."
      bit_offset: 8
      bit_size: 8
    - name: AM
      description: "Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
      bit_offset: 16
      bit_size: 2
      enum: BGPFCCR_AM
    - name: AI
      description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
      bit_offset: 20
      bit_size: 1
      enum: BGPFCCR_AI
    - name: RBS
      description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
      bit_offset: 21
      bit_size: 1
      enum: BGPFCCR_RBS
    - name: ALPHA
      description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 24
      bit_size: 8
fieldset/CR:
  description: DMA2D control register
  fields:
    - name: START
      description: Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers
      bit_offset: 0
      bit_size: 1
      enum: CR_START
    - name: SUSP
      description: Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset.
      bit_offset: 1
      bit_size: 1
      enum: SUSP
    - name: ABORT
      description: Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset.
      bit_offset: 2
      bit_size: 1
      enum: ABORT
    - name: TEIE
      description: Transfer error interrupt enable This bit is set and cleared by software.
      bit_offset: 8
      bit_size: 1
      enum: TEIE
    - name: TCIE
      description: Transfer complete interrupt enable This bit is set and cleared by software.
      bit_offset: 9
      bit_size: 1
      enum: TCIE
    - name: TWIE
      description: Transfer watermark interrupt enable This bit is set and cleared by software.
      bit_offset: 10
      bit_size: 1
      enum: TWIE
    - name: CAEIE
      description: CLUT access error interrupt enable This bit is set and cleared by software.
      bit_offset: 11
      bit_size: 1
      enum: CAEIE
    - name: CTCIE
      description: CLUT transfer complete interrupt enable This bit is set and cleared by software.
      bit_offset: 12
      bit_size: 1
      enum: CTCIE
    - name: CEIE
      description: Configuration Error Interrupt Enable This bit is set and cleared by software.
      bit_offset: 13
      bit_size: 1
      enum: CEIE
    - name: MODE
      description: DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing.
      bit_offset: 16
      bit_size: 2
      enum: MODE
fieldset/FGCMAR:
  description: DMA2D foreground CLUT memory address register
  fields:
    - name: MA
      description: "Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned."
      bit_offset: 0
      bit_size: 32
fieldset/FGCOLR:
  description: DMA2D foreground color register
  fields:
    - name: BLUE
      description: "Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only."
      bit_offset: 0
      bit_size: 8
    - name: GREEN
      description: "Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only."
      bit_offset: 8
      bit_size: 8
    - name: RED
      description: "Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 16
      bit_size: 8
fieldset/FGMAR:
  description: DMA2D foreground memory address register
  fields:
    - name: MA
      description: "Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned."
      bit_offset: 0
      bit_size: 32
fieldset/FGOR:
  description: DMA2D foreground offset register
  fields:
    - name: LO
      description: "Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even."
      bit_offset: 0
      bit_size: 16
fieldset/FGPFCCR:
  description: DMA2D foreground PFC control register
  fields:
    - name: CM
      description: "Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
      bit_offset: 0
      bit_size: 4
      enum: FGPFCCR_CM
    - name: CCM
      description: "CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only."
      bit_offset: 4
      bit_size: 1
      enum: FGPFCCR_CCM
    - name: START
      description: "Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer)."
      bit_offset: 5
      bit_size: 1
      enum: FGPFCCR_START
    - name: CS
      description: "CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1."
      bit_offset: 8
      bit_size: 8
    - name: AM
      description: "Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless"
      bit_offset: 16
      bit_size: 2
      enum: FGPFCCR_AM
    - name: CSS
      description: "Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless"
      bit_offset: 18
      bit_size: 2
    - name: AI
      description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
      bit_offset: 20
      bit_size: 1
      enum: FGPFCCR_AI
    - name: RBS
      description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
      bit_offset: 21
      bit_size: 1
      enum: FGPFCCR_RBS
    - name: ALPHA
      description: "Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only."
      bit_offset: 24
      bit_size: 8
fieldset/IFCR:
  description: DMA2D interrupt flag clear register
  fields:
    - name: CTEIF
      description: Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
      bit_offset: 0
      bit_size: 1
      enum: CTEIF
    - name: CTCIF
      description: Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
      bit_offset: 1
      bit_size: 1
      enum: CTCIF
    - name: CTWIF
      description: Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
      bit_offset: 2
      bit_size: 1
      enum: CTWIF
    - name: CAECIF
      description: Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
      bit_offset: 3
      bit_size: 1
      enum: CAECIF
    - name: CCTCIF
      description: Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
      bit_offset: 4
      bit_size: 1
      enum: CCTCIF
    - name: CCEIF
      description: Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
      bit_offset: 5
      bit_size: 1
      enum: CCEIF
fieldset/ISR:
  description: DMA2D Interrupt Status Register
  fields:
    - name: TEIF
      description: Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading).
      bit_offset: 0
      bit_size: 1
    - name: TCIF
      description: Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only).
      bit_offset: 1
      bit_size: 1
    - name: TWIF
      description: Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred.
      bit_offset: 2
      bit_size: 1
    - name: CAEIF
      description: CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D.
      bit_offset: 3
      bit_size: 1
    - name: CTCIF
      description: CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete.
      bit_offset: 4
      bit_size: 1
    - name: CEIF
      description: "Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed."
      bit_offset: 5
      bit_size: 1
fieldset/LWR:
  description: DMA2D line watermark register
  fields:
    - name: LW
      description: "Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 0
      bit_size: 16
fieldset/NLR:
  description: DMA2D number of line register
  fields:
    - name: NL
      description: "Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 0
      bit_size: 16
    - name: PL
      description: "Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even."
      bit_offset: 16
      bit_size: 14
fieldset/OCOLR:
  description: DMA2D output color register
  fields:
    - name: BLUE
      description: "Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 0
      bit_size: 8
    - name: GREEN
      description: "Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 8
      bit_size: 8
    - name: RED
      description: "Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 16
      bit_size: 8
    - name: ALPHA
      description: "Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 24
      bit_size: 8
fieldset/OMAR:
  description: DMA2D output memory address register
  fields:
    - name: MA
      description: "Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned."
      bit_offset: 0
      bit_size: 32
fieldset/OOR:
  description: DMA2D output offset register
  fields:
    - name: LO
      description: "Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only."
      bit_offset: 0
      bit_size: 16
fieldset/OPFCCR:
  description: DMA2D output PFC control register
  fields:
    - name: CM
      description: "Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless"
      bit_offset: 0
      bit_size: 3
      enum: OPFCCR_CM
    - name: SB
      description: Swap Bytes
      bit_offset: 8
      bit_size: 1
      enum: SB
    - name: AI
      description: "Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only."
      bit_offset: 20
      bit_size: 1
      enum: OPFCCR_AI
    - name: RBS
      description: "Red Blue Swap This bit allows to swap the R & B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only."
      bit_offset: 21
      bit_size: 1
      enum: OPFCCR_RBS
enum/ABORT:
  bit_size: 1
  variants:
    - name: AbortRequest
      description: Transfer abort requested
      value: 1
enum/BGPFCCR_AI:
  bit_size: 1
  variants:
    - name: RegularAlpha
      description: Regular alpha
      value: 0
    - name: InvertedAlpha
      description: Inverted alpha
      value: 1
enum/BGPFCCR_AM:
  bit_size: 2
  variants:
    - name: NoModify
      description: No modification of alpha channel
      value: 0
    - name: Replace
      description: "Replace with value in ALPHA[7:0]"
      value: 1
    - name: Multiply
      description: "Multiply with value in ALPHA[7:0]"
      value: 2
enum/BGPFCCR_CCM:
  bit_size: 1
  variants:
    - name: ARGB8888
      description: CLUT color format ARGB8888
      value: 0
    - name: RGB888
      description: CLUT color format RGB888
      value: 1
enum/BGPFCCR_CM:
  bit_size: 4
  variants:
    - name: ARGB8888
      description: Color mode ARGB8888
      value: 0
    - name: RGB888
      description: Color mode RGB888
      value: 1
    - name: RGB565
      description: Color mode RGB565
      value: 2
    - name: ARGB1555
      description: Color mode ARGB1555
      value: 3
    - name: ARGB4444
      description: Color mode ARGB4444
      value: 4
    - name: L8
      description: Color mode L8
      value: 5
    - name: AL44
      description: Color mode AL44
      value: 6
    - name: AL88
      description: Color mode AL88
      value: 7
    - name: L4
      description: Color mode L4
      value: 8
    - name: A8
      description: Color mode A8
      value: 9
    - name: A4
      description: Color mode A4
      value: 10
enum/BGPFCCR_RBS:
  bit_size: 1
  variants:
    - name: Regular
      description: No Red Blue Swap (RGB or ARGB)
      value: 0
    - name: Swap
      description: Red Blue Swap (BGR or ABGR)
      value: 1
enum/BGPFCCR_START:
  bit_size: 1
  variants:
    - name: Start
      description: Start the automatic loading of the CLUT
      value: 1
enum/CAECIF:
  bit_size: 1
  variants:
    - name: Clear
      description: Clear the CAEIF flag in the ISR register
      value: 1
enum/CAEIE:
  bit_size: 1
  variants:
    - name: Disabled
      description: CAE interrupt disabled
      value: 0
    - name: Enabled
      description: CAE interrupt enabled
      value: 1
enum/CCEIF:
  bit_size: 1
  variants:
    - name: Clear
      description: Clear the CEIF flag in the ISR register
      value: 1
enum/CCTCIF:
  bit_size: 1
  variants:
    - name: Clear
      description: Clear the CTCIF flag in the ISR register
      value: 1
enum/CEIE:
  bit_size: 1
  variants:
    - name: Disabled
      description: CE interrupt disabled
      value: 0
    - name: Enabled
      description: CE interrupt enabled
      value: 1
enum/CR_START:
  bit_size: 1
  variants:
    - name: Start
      description: Launch the DMA2D
      value: 1
enum/CTCIE:
  bit_size: 1
  variants:
    - name: Disabled
      description: CTC interrupt disabled
      value: 0
    - name: Enabled
      description: CTC interrupt enabled
      value: 1
enum/CTCIF:
  bit_size: 1
  variants:
    - name: Clear
      description: Clear the TCIF flag in the ISR register
      value: 1
enum/CTEIF:
  bit_size: 1
  variants:
    - name: Clear
      description: Clear the TEIF flag in the ISR register
      value: 1
enum/CTWIF:
  bit_size: 1
  variants:
    - name: Clear
      description: Clear the TWIF flag in the ISR register
      value: 1
enum/EN:
  bit_size: 1
  variants:
    - name: Disabled
      description: Disabled AHB/AXI dead-time functionality
      value: 0
    - name: Enabled
      description: Enabled AHB/AXI dead-time functionality
      value: 1
enum/FGPFCCR_AI:
  bit_size: 1
  variants:
    - name: RegularAlpha
      description: Regular alpha
      value: 0
    - name: InvertedAlpha
      description: Inverted alpha
      value: 1
enum/FGPFCCR_AM:
  bit_size: 2
  variants:
    - name: NoModify
      description: No modification of alpha channel
      value: 0
    - name: Replace
      description: "Replace with value in ALPHA[7:0]"
      value: 1
    - name: Multiply
      description: "Multiply with value in ALPHA[7:0]"
      value: 2
enum/FGPFCCR_CCM:
  bit_size: 1
  variants:
    - name: ARGB8888
      description: CLUT color format ARGB8888
      value: 0
    - name: RGB888
      description: CLUT color format RGB888
      value: 1
enum/FGPFCCR_CM:
  bit_size: 4
  variants:
    - name: ARGB8888
      description: Color mode ARGB8888
      value: 0
    - name: RGB888
      description: Color mode RGB888
      value: 1
    - name: RGB565
      description: Color mode RGB565
      value: 2
    - name: ARGB1555
      description: Color mode ARGB1555
      value: 3
    - name: ARGB4444
      description: Color mode ARGB4444
      value: 4
    - name: L8
      description: Color mode L8
      value: 5
    - name: AL44
      description: Color mode AL44
      value: 6
    - name: AL88
      description: Color mode AL88
      value: 7
    - name: L4
      description: Color mode L4
      value: 8
    - name: A8
      description: Color mode A8
      value: 9
    - name: A4
      description: Color mode A4
      value: 10
    - name: YCbCr
      description: Color mode YCbCr
      value: 11
enum/FGPFCCR_RBS:
  bit_size: 1
  variants:
    - name: Regular
      description: No Red Blue Swap (RGB or ARGB)
      value: 0
    - name: Swap
      description: Red Blue Swap (BGR or ABGR)
      value: 1
enum/FGPFCCR_START:
  bit_size: 1
  variants:
    - name: Start
      description: Start the automatic loading of the CLUT
      value: 1
enum/MODE:
  bit_size: 2
  variants:
    - name: MemoryToMemory
      description: Memory-to-memory (FG fetch only)
      value: 0
    - name: MemoryToMemoryPFC
      description: Memory-to-memory with PFC (FG fetch only with FG PFC active)
      value: 1
    - name: MemoryToMemoryPFCBlending
      description: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
      value: 2
    - name: RegisterToMemory
      description: Register-to-memory
      value: 3
enum/OPFCCR_AI:
  bit_size: 1
  variants:
    - name: RegularAlpha
      description: Regular alpha
      value: 0
    - name: InvertedAlpha
      description: Inverted alpha
      value: 1
enum/OPFCCR_CM:
  bit_size: 3
  variants:
    - name: ARGB8888
      description: ARGB8888
      value: 0
    - name: RGB888
      description: RGB888
      value: 1
    - name: RGB565
      description: RGB565
      value: 2
    - name: ARGB1555
      description: ARGB1555
      value: 3
    - name: ARGB4444
      description: ARGB4444
      value: 4
enum/OPFCCR_RBS:
  bit_size: 1
  variants:
    - name: Regular
      description: No Red Blue Swap (RGB or ARGB)
      value: 0
    - name: Swap
      description: Red Blue Swap (BGR or ABGR)
      value: 1
enum/SB:
  bit_size: 1
  variants:
    - name: Regular
      description: Regular byte order
      value: 0
    - name: SwapBytes
      description: Bytes are swapped two by two
      value: 1
enum/SUSP:
  bit_size: 1
  variants:
    - name: NotSuspended
      description: Transfer not suspended
      value: 0
    - name: Suspended
      description: Transfer suspended
      value: 1
enum/TCIE:
  bit_size: 1
  variants:
    - name: Disabled
      description: TC interrupt disabled
      value: 0
    - name: Enabled
      description: TC interrupt enabled
      value: 1
enum/TEIE:
  bit_size: 1
  variants:
    - name: Disabled
      description: TE interrupt disabled
      value: 0
    - name: Enabled
      description: TE interrupt enabled
      value: 1
enum/TWIE:
  bit_size: 1
  variants:
    - name: Disabled
      description: TW interrupt disabled
      value: 0
    - name: Enabled
      description: TW interrupt enabled
      value: 1