block/RCC: description: Reset and clock control items: - byte_offset: 0 description: Clock control register fieldset: CR name: CR - byte_offset: 4 description: Internal clock sources calibration register fieldset: ICSCR name: ICSCR - byte_offset: 12 description: Clock configuration register fieldset: CFGR name: CFGR - access: Read byte_offset: 16 description: Clock interrupt enable register fieldset: CIER name: CIER - access: Read byte_offset: 20 description: Clock interrupt flag register fieldset: CIFR name: CIFR - access: Read byte_offset: 24 description: Clock interrupt clear register fieldset: CICR name: CICR - byte_offset: 28 description: GPIO reset register fieldset: IOPRSTR name: IOPRSTR - byte_offset: 32 description: AHB peripheral reset register fieldset: AHBRSTR name: AHBRSTR - byte_offset: 36 description: APB2 peripheral reset register fieldset: APB2RSTR name: APB2RSTR - byte_offset: 40 description: APB1 peripheral reset register fieldset: APB1RSTR name: APB1RSTR - byte_offset: 44 description: GPIO clock enable register fieldset: IOPENR name: IOPENR - byte_offset: 48 description: AHB peripheral clock enable register fieldset: AHBENR name: AHBENR - byte_offset: 52 description: APB2 peripheral clock enable register fieldset: APB2ENR name: APB2ENR - byte_offset: 56 description: APB1 peripheral clock enable register fieldset: APB1ENR name: APB1ENR - byte_offset: 60 description: GPIO clock enable in sleep mode register fieldset: IOPSMEN name: IOPSMEN - byte_offset: 64 description: AHB peripheral clock enable in sleep mode register fieldset: AHBSMENR name: AHBSMENR - byte_offset: 68 description: APB2 peripheral clock enable in sleep mode register fieldset: APB2SMENR name: APB2SMENR - byte_offset: 72 description: APB1 peripheral clock enable in sleep mode register fieldset: APB1SMENR name: APB1SMENR - byte_offset: 76 description: Clock configuration register fieldset: CCIPR name: CCIPR - byte_offset: 80 description: Control and status register fieldset: CSR name: CSR - byte_offset: 8 description: Clock recovery RC register fieldset: CRRCR name: CRRCR enum/CRYPRSTW: bit_size: 1 variants: - description: Reset the module name: Reset value: 1 enum/CSSHSECW: bit_size: 1 variants: - description: Clear interrupt flag name: Clear value: 1 enum/CSSHSEF: bit_size: 1 variants: - description: No clock security interrupt caused by HSE clock failure name: NoClock value: 0 - description: Clock security interrupt caused by HSE clock failure name: Clock value: 1 enum/CSSLSE: bit_size: 1 variants: - description: LSE CSS interrupt disabled name: Disabled value: 0 - description: LSE CSS interrupt enabled name: Enabled value: 1 enum/CSSLSED: bit_size: 1 variants: - description: No failure detected on LSE (32 kHz oscillator) name: NoFailure value: 0 - description: Failure detected on LSE (32 kHz oscillator) name: Failure value: 1 enum/CSSLSEF: bit_size: 1 variants: - description: No failure detected on LSE clock failure name: NoFailure value: 0 - description: Failure detected on LSE clock failure name: Failure value: 1 enum/DBGRSTW: bit_size: 1 variants: - description: Reset the module name: Reset value: 1 enum/HPRE: bit_size: 4 variants: - description: system clock not divided name: Div1 value: 0 - description: system clock divided by 2 name: Div2 value: 8 - description: system clock divided by 4 name: Div4 value: 9 - description: system clock divided by 8 name: Div8 value: 10 - description: system clock divided by 16 name: Div16 value: 11 - description: system clock divided by 64 name: Div64 value: 12 - description: system clock divided by 128 name: Div128 value: 13 - description: system clock divided by 256 name: Div256 value: 14 - description: system clock divided by 512 name: Div512 value: 15 enum/HSEBYP: bit_size: 1 variants: - description: HSE oscillator not bypassed name: NotBypassed value: 0 - description: HSE oscillator bypassed name: Bypassed value: 1 enum/HSERDYR: bit_size: 1 variants: - description: Oscillator is not stable name: NotReady value: 0 - description: Oscillator is stable name: Ready value: 1 enum/HSI16RDYFR: bit_size: 1 variants: - description: HSI 16 MHz oscillator not ready name: NotReady value: 0 - description: HSI 16 MHz oscillator ready name: Ready value: 1 enum/HSI48RDYFR: bit_size: 1 variants: - description: No clock ready interrupt name: NotInterrupted value: 0 - description: Clock ready interrupt name: Interrupted value: 1 enum/HSIDIVFR: bit_size: 1 variants: - description: 16 MHz HSI clock not divided name: NotDivided value: 0 - description: 16 MHz HSI clock divided by 4 name: Div4 value: 1 enum/HSIRDYFR: bit_size: 1 variants: - description: HSI 16 MHz oscillator not ready name: NotReady value: 0 - description: HSI 16 MHz oscillator ready name: Ready value: 1 enum/HSIRDYIE: bit_size: 1 variants: - description: Ready interrupt disabled name: Disabled value: 0 - description: Ready interrupt enabled name: Enabled value: 1 enum/ICSEL: bit_size: 2 variants: - description: APB clock selected as peripheral clock name: APB value: 0 - description: System clock selected as peripheral clock name: SYSTEM value: 1 - description: HSI16 clock selected as peripheral clock name: HSI16 value: 2 enum/LPTIMRSTW: bit_size: 1 variants: - description: Reset the module name: Reset value: 1 enum/LPTIMSEL: bit_size: 2 variants: - description: APB clock selected as Timer clock name: APB value: 0 - description: LSI clock selected as Timer clock name: LSI value: 1 - description: HSI16 clock selected as Timer clock name: HSI16 value: 2 - description: LSE clock selected as Timer clock name: LSE value: 3 enum/LPUARTSEL: bit_size: 2 variants: - description: APB clock selected as peripheral clock name: APB value: 0 - description: System clock selected as peripheral clock name: SYSTEM value: 1 - description: HSI16 clock selected as peripheral clock name: HSI16 value: 2 - description: LSE clock selected as peripheral clock name: LSE value: 3 enum/LPWRRSTFR: bit_size: 1 variants: - description: No reset has occured name: NoReset value: 0 - description: A reset has occured name: Reset value: 1 enum/LPWRSTFR: bit_size: 1 variants: - description: No reset has occured name: NoReset value: 0 - description: A reset has occured name: Reset value: 1 enum/LSEBYP: bit_size: 1 variants: - description: LSE oscillator not bypassed name: NotBypassed value: 0 - description: LSE oscillator bypassed name: Bypassed value: 1 enum/LSEDRV: bit_size: 2 variants: - description: Lowest drive name: Low value: 0 - description: Medium low drive name: MediumLow value: 1 - description: Medium high drive name: MediumHigh value: 2 - description: Highest drive name: High value: 3 enum/LSERDY: bit_size: 1 variants: - description: Oscillator not ready name: NotReady value: 0 - description: Oscillator ready name: Ready value: 1 enum/MCOPRE: bit_size: 3 variants: - description: No division name: Div1 value: 0 - description: Division by 2 name: Div2 value: 1 - description: Division by 4 name: Div4 value: 2 - description: Division by 8 name: Div8 value: 3 - description: Division by 16 name: Div16 value: 4 enum/MCOSEL: bit_size: 4 variants: - description: No clock name: NoClock value: 0 - description: SYSCLK clock selected name: SYSCLK value: 1 - description: HSI oscillator clock selected name: HSI16 value: 2 - description: MSI oscillator clock selected name: MSI value: 3 - description: HSE oscillator clock selected name: HSE value: 4 - description: PLL clock selected name: PLL value: 5 - description: LSI oscillator clock selected name: LSI value: 6 - description: LSE oscillator clock selected name: LSE value: 7 enum/MSIRANGE: bit_size: 3 variants: - description: range 0 around 65.536 kHz name: Range0 value: 0 - description: range 1 around 131.072 kHz name: Range1 value: 1 - description: range 2 around 262.144 kHz name: Range2 value: 2 - description: range 3 around 524.288 kHz name: Range3 value: 3 - description: range 4 around 1.048 MHz name: Range4 value: 4 - description: range 5 around 2.097 MHz (reset value) name: Range5 value: 5 - description: range 6 around 4.194 MHz name: Range6 value: 6 - description: not allowed name: Range7 value: 7 enum/MSIRDYFR: bit_size: 1 variants: - description: No clock ready interrupt name: NotInterrupted value: 0 - description: Clock ready interrupt name: Interrupted value: 1 enum/MSIRDYIE: bit_size: 1 variants: - description: Ready interrupt disabled name: Disabled value: 0 - description: Ready interrupt enabled name: Enabled value: 1 enum/PLLDIV: bit_size: 2 variants: - description: PLLVCO / 2 name: Div2 value: 1 - description: PLLVCO / 3 name: Div3 value: 2 - description: PLLVCO / 4 name: Div4 value: 3 enum/PLLMUL: bit_size: 4 variants: - description: PLL clock entry x 3 name: Mul3 value: 0 - description: PLL clock entry x 4 name: Mul4 value: 1 - description: PLL clock entry x 6 name: Mul6 value: 2 - description: PLL clock entry x 8 name: Mul8 value: 3 - description: PLL clock entry x 12 name: Mul12 value: 4 - description: PLL clock entry x 16 name: Mul16 value: 5 - description: PLL clock entry x 24 name: Mul24 value: 6 - description: PLL clock entry x 32 name: Mul32 value: 7 - description: PLL clock entry x 48 name: Mul48 value: 8 enum/PLLRDYR: bit_size: 1 variants: - description: PLL unlocked name: Unlocked value: 0 - description: PLL locked name: Locked value: 1 enum/PLLSRC: bit_size: 1 variants: - description: HSI selected as PLL input clock name: HSI16 value: 0 - description: HSE selected as PLL input clock name: HSE value: 1 enum/PPRE: bit_size: 3 variants: - description: HCLK not divided name: Div1 value: 0 - description: HCLK divided by 2 name: Div2 value: 4 - description: HCLK divided by 4 name: Div4 value: 5 - description: HCLK divided by 8 name: Div8 value: 6 - description: HCLK divided by 16 name: Div16 value: 7 enum/RMVFW: bit_size: 1 variants: - description: Clears the reset flag name: Clear value: 1 enum/RTCPRE: bit_size: 2 variants: - description: HSE divided by 2 name: Div2 value: 0 - description: HSE divided by 4 name: Div4 value: 1 - description: HSE divided by 8 name: Div8 value: 2 - description: HSE divided by 16 name: Div16 value: 3 enum/RTCRSTW: bit_size: 1 variants: - description: Resets the RTC peripheral name: Reset value: 1 enum/RTCSEL: bit_size: 2 variants: - description: No clock name: NoClock value: 0 - description: LSE oscillator clock used as RTC clock name: LSE value: 1 - description: LSI oscillator clock used as RTC clock name: LSI value: 2 - description: HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock name: HSE value: 3 enum/STOPWUCK: bit_size: 1 variants: - description: Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock name: MSI value: 0 - description: Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) name: HSI16 value: 1 enum/SW: bit_size: 2 variants: - description: MSI oscillator used as system clock name: MSI value: 0 - description: HSI oscillator used as system clock name: HSI16 value: 1 - description: HSE oscillator used as system clock name: HSE value: 2 - description: PLL used as system clock name: PLL value: 3 enum/SWS: bit_size: 2 variants: - description: MSI oscillator used as system clock name: MSI value: 0 - description: HSI oscillator used as system clock name: HSI16 value: 1 - description: HSE oscillator used as system clock name: HSE value: 2 - description: PLL used as system clock name: PLL value: 3 fieldset/AHBENR: description: AHB peripheral clock enable register fields: - bit_offset: 0 bit_size: 1 description: DMA clock enable bit name: DMAEN - bit_offset: 8 bit_size: 1 description: NVM interface clock enable bit name: MIFEN - bit_offset: 12 bit_size: 1 description: CRC clock enable bit name: CRCEN - bit_offset: 24 bit_size: 1 description: Crypto clock enable bit name: CRYPEN - bit_offset: 16 bit_size: 1 description: Touch Sensing clock enable bit name: TOUCHEN - bit_offset: 20 bit_size: 1 description: Random Number Generator clock enable bit name: RNGEN fieldset/AHBRSTR: description: AHB peripheral reset register fields: - bit_offset: 0 bit_size: 1 description: DMA reset enum_write: CRYPRSTW name: DMARST - bit_offset: 8 bit_size: 1 description: Memory interface reset enum_write: CRYPRSTW name: MIFRST - bit_offset: 12 bit_size: 1 description: Test integration module reset enum_write: CRYPRSTW name: CRCRST - bit_offset: 24 bit_size: 1 description: Crypto module reset enum_write: CRYPRSTW name: CRYPRST - bit_offset: 16 bit_size: 1 description: Touch Sensing reset enum_write: CRYPRSTW name: TOUCHRST - bit_offset: 20 bit_size: 1 description: Random Number Generator module reset enum_write: CRYPRSTW name: RNGRST fieldset/AHBSMENR: description: AHB peripheral clock enable in sleep mode register fields: - bit_offset: 0 bit_size: 1 description: DMA clock enable during sleep mode bit name: DMASMEN - bit_offset: 8 bit_size: 1 description: NVM interface clock enable during sleep mode bit name: MIFSMEN - bit_offset: 9 bit_size: 1 description: SRAM interface clock enable during sleep mode bit name: SRAMSMEN - bit_offset: 12 bit_size: 1 description: CRC clock enable during sleep mode bit name: CRCSMEN - bit_offset: 24 bit_size: 1 description: Crypto clock enable during sleep mode bit name: CRYPSMEN - bit_offset: 16 bit_size: 1 description: Touch Sensing clock enable during sleep mode bit name: TOUCHSMEN - bit_offset: 20 bit_size: 1 description: Random Number Generator clock enable during sleep mode bit name: RNGSMEN fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - bit_offset: 0 bit_size: 1 description: Timer2 clock enable bit name: TIM2EN - bit_offset: 4 bit_size: 1 description: Timer 6 clock enable bit name: TIM6EN - bit_offset: 5 bit_size: 1 description: Timer 7 clock enable bit name: TIM7EN - bit_offset: 11 bit_size: 1 description: Window watchdog clock enable bit name: WWDGEN - bit_offset: 14 bit_size: 1 description: SPI2 clock enable bit name: SPI2EN - bit_offset: 17 bit_size: 1 description: UART2 clock enable bit name: USART2EN - bit_offset: 18 bit_size: 1 description: LPUART1 clock enable bit name: LPUART1EN - bit_offset: 19 bit_size: 1 description: USART4 clock enable bit name: USART4EN - bit_offset: 20 bit_size: 1 description: USART5 clock enable bit name: USART5EN - bit_offset: 21 bit_size: 1 description: I2C1 clock enable bit name: I2C1EN - bit_offset: 22 bit_size: 1 description: I2C2 clock enable bit name: I2C2EN - bit_offset: 28 bit_size: 1 description: Power interface clock enable bit name: PWREN - bit_offset: 30 bit_size: 1 description: I2C3 clock enable bit name: I2C3EN - bit_offset: 31 bit_size: 1 description: Low power timer clock enable bit name: LPTIM1EN - bit_offset: 1 bit_size: 1 description: Timer 3 clock enbale bit name: TIM3EN - bit_offset: 23 bit_size: 1 description: USB clock enable bit name: USBEN - bit_offset: 27 bit_size: 1 description: Clock recovery system clock enable bit name: CRSEN - bit_offset: 29 bit_size: 1 description: DAC interface clock enable bit name: DACEN fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - bit_offset: 0 bit_size: 1 description: Timer 2 reset enum_write: LPTIMRSTW name: TIM2RST - bit_offset: 1 bit_size: 1 description: Timer 3 reset enum_write: LPTIMRSTW name: TIM3RST - bit_offset: 4 bit_size: 1 description: Timer 6 reset enum_write: LPTIMRSTW name: TIM6RST - bit_offset: 5 bit_size: 1 description: Timer 7 reset enum_write: LPTIMRSTW name: TIM7RST - bit_offset: 11 bit_size: 1 description: Window watchdog reset enum_write: LPTIMRSTW name: WWDGRST - bit_offset: 14 bit_size: 1 description: SPI2 reset enum_write: LPTIMRSTW name: SPI2RST - bit_offset: 17 bit_size: 1 description: USART2 reset enum_write: LPTIMRSTW name: USART2RST - bit_offset: 18 bit_size: 1 description: LPUART1 reset enum_write: LPTIMRSTW name: LPUART1RST - bit_offset: 19 bit_size: 1 description: USART4 reset enum_write: LPTIMRSTW name: USART4RST - bit_offset: 20 bit_size: 1 description: USART5 reset enum_write: LPTIMRSTW name: USART5RST - bit_offset: 21 bit_size: 1 description: I2C1 reset enum_write: LPTIMRSTW name: I2C1RST - bit_offset: 22 bit_size: 1 description: I2C2 reset enum_write: LPTIMRSTW name: I2C2RST - bit_offset: 27 bit_size: 1 description: CRC reset enum_write: LPTIMRSTW name: CRCRST - bit_offset: 28 bit_size: 1 description: Power interface reset enum_write: LPTIMRSTW name: PWRRST - bit_offset: 30 bit_size: 1 description: I2C3 reset name: I2C3 - bit_offset: 31 bit_size: 1 description: Low power timer reset enum_write: LPTIMRSTW name: LPTIM1RST - bit_offset: 30 bit_size: 1 description: I2C3 reset enum_write: LPTIMRSTW name: I2C3RST - bit_offset: 11 bit_size: 1 description: Window watchdog reset enum_write: LPTIMRSTW name: WWDRST - bit_offset: 17 bit_size: 1 description: UART2 reset enum_write: LPTIMRSTW name: LPUART12RST - bit_offset: 23 bit_size: 1 description: USB reset enum_write: LPTIMRSTW name: USBRST - bit_offset: 27 bit_size: 1 description: Clock recovery system reset enum_write: LPTIMRSTW name: CRSRST - bit_offset: 29 bit_size: 1 description: DAC interface reset enum_write: LPTIMRSTW name: DACRST fieldset/APB1SMENR: description: APB1 peripheral clock enable in sleep mode register fields: - bit_offset: 0 bit_size: 1 description: Timer2 clock enable during sleep mode bit name: TIM2SMEN - bit_offset: 1 bit_size: 1 description: Timer 3 clock enable during sleep mode bit name: TIM3SMEN - bit_offset: 4 bit_size: 1 description: Timer 6 clock enable during sleep mode bit name: TIM6SMEN - bit_offset: 5 bit_size: 1 description: Timer 7 clock enable during sleep mode bit name: TIM7SMEN - bit_offset: 11 bit_size: 1 description: Window watchdog clock enable during sleep mode bit name: WWDGSMEN - bit_offset: 14 bit_size: 1 description: SPI2 clock enable during sleep mode bit name: SPI2SMEN - bit_offset: 17 bit_size: 1 description: UART2 clock enable during sleep mode bit name: USART2SMEN - bit_offset: 18 bit_size: 1 description: LPUART1 clock enable during sleep mode bit name: LPUART1SMEN - bit_offset: 19 bit_size: 1 description: USART4 clock enabe during sleep mode bit name: USART4SMEN - bit_offset: 20 bit_size: 1 description: USART5 clock enable during sleep mode bit name: USART5SMEN - bit_offset: 21 bit_size: 1 description: I2C1 clock enable during sleep mode bit name: I2C1SMEN - bit_offset: 22 bit_size: 1 description: I2C2 clock enable during sleep mode bit name: I2C2SMEN - bit_offset: 27 bit_size: 1 description: Clock recovery system clock enable during sleep mode bit name: CRSSMEN - bit_offset: 28 bit_size: 1 description: Power interface clock enable during sleep mode bit name: PWRSMEN - bit_offset: 30 bit_size: 1 description: I2C3 clock enable during sleep mode bit name: I2C3SMEN - bit_offset: 31 bit_size: 1 description: Low power timer clock enable during sleep mode bit name: LPTIM1SMEN - bit_offset: 23 bit_size: 1 description: USB clock enable during sleep mode bit name: USBSMEN - bit_offset: 29 bit_size: 1 description: DAC interface clock enable during sleep mode bit name: DACSMEN fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - bit_offset: 0 bit_size: 1 description: System configuration controller clock enable bit name: SYSCFGEN - bit_offset: 2 bit_size: 1 description: TIM21 timer clock enable bit name: TIM21EN - bit_offset: 5 bit_size: 1 description: TIM22 timer clock enable bit name: TIM22EN - bit_offset: 7 bit_size: 1 description: Firewall clock enable bit name: FWEN - bit_offset: 9 bit_size: 1 description: ADC clock enable bit name: ADCEN - bit_offset: 12 bit_size: 1 description: SPI1 clock enable bit name: SPI1EN - bit_offset: 14 bit_size: 1 description: USART1 clock enable bit name: USART1EN - bit_offset: 22 bit_size: 1 description: DBG clock enable bit name: DBGEN - bit_offset: 7 bit_size: 1 description: MiFaRe Firewall clock enable bit name: MIFIEN fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - bit_offset: 0 bit_size: 1 description: System configuration controller reset enum_write: DBGRSTW name: SYSCFGRST - bit_offset: 2 bit_size: 1 description: TIM21 timer reset enum_write: DBGRSTW name: TIM21RST - bit_offset: 5 bit_size: 1 description: TIM22 timer reset enum_write: DBGRSTW name: TIM22RST - bit_offset: 9 bit_size: 1 description: ADC interface reset enum_write: DBGRSTW name: ADCRST - bit_offset: 12 bit_size: 1 description: SPI 1 reset enum_write: DBGRSTW name: SPI1RST - bit_offset: 14 bit_size: 1 description: USART1 reset enum_write: DBGRSTW name: USART1RST - bit_offset: 22 bit_size: 1 description: DBG reset enum_write: DBGRSTW name: DBGRST fieldset/APB2SMENR: description: APB2 peripheral clock enable in sleep mode register fields: - bit_offset: 0 bit_size: 1 description: System configuration controller clock enable during sleep mode bit name: SYSCFGSMEN - bit_offset: 2 bit_size: 1 description: TIM21 timer clock enable during sleep mode bit name: TIM21SMEN - bit_offset: 5 bit_size: 1 description: TIM22 timer clock enable during sleep mode bit name: TIM22SMEN - bit_offset: 9 bit_size: 1 description: ADC clock enable during sleep mode bit name: ADCSMEN - bit_offset: 12 bit_size: 1 description: SPI1 clock enable during sleep mode bit name: SPI1SMEN - bit_offset: 14 bit_size: 1 description: USART1 clock enable during sleep mode bit name: USART1SMEN - bit_offset: 22 bit_size: 1 description: DBG clock enable during sleep mode bit name: DBGSMEN fieldset/CCIPR: description: Clock configuration register fields: - bit_offset: 0 bit_size: 2 description: USART1 clock source selection bits enum: LPUARTSEL name: USART1SEL - bit_offset: 2 bit_size: 2 description: USART2 clock source selection bits enum: LPUARTSEL name: USART2SEL - bit_offset: 10 bit_size: 2 description: LPUART1 clock source selection bits enum: LPUARTSEL name: LPUART1SEL - bit_offset: 12 bit_size: 2 description: I2C1 clock source selection bits enum: ICSEL name: I2C1SEL - bit_offset: 16 bit_size: 2 description: I2C3 clock source selection bits enum: ICSEL name: I2C3SEL - bit_offset: 18 bit_size: 2 description: Low Power Timer clock source selection bits enum: LPTIMSEL name: LPTIM1SEL - bit_offset: 26 bit_size: 1 description: 48 MHz HSI48 clock source selection bit name: HSI48MSEL fieldset/CFGR: description: Clock configuration register fields: - bit_offset: 0 bit_size: 2 description: System clock switch enum: SW name: SW - bit_offset: 2 bit_size: 2 description: System clock switch status enum: SWS name: SWS - bit_offset: 4 bit_size: 4 description: AHB prescaler enum: HPRE name: HPRE - bit_offset: 8 bit_size: 3 description: APB low-speed prescaler (APB1) enum: PPRE name: PPRE1 - bit_offset: 11 bit_size: 3 description: APB high-speed prescaler (APB2) enum: PPRE name: PPRE2 - bit_offset: 15 bit_size: 1 description: Wake-up from stop clock selection enum: STOPWUCK name: STOPWUCK - bit_offset: 16 bit_size: 1 description: PLL entry clock source enum: PLLSRC name: PLLSRC - bit_offset: 18 bit_size: 4 description: PLL multiplication factor enum: PLLMUL name: PLLMUL - bit_offset: 22 bit_size: 2 description: PLL output division enum: PLLDIV name: PLLDIV - bit_offset: 24 bit_size: 3 description: Microcontroller clock output selection enum: MCOSEL name: MCOSEL - bit_offset: 28 bit_size: 3 description: Microcontroller clock output prescaler enum: MCOPRE name: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - bit_offset: 0 bit_size: 1 description: LSI ready Interrupt clear enum_write: CSSHSECW name: LSIRDYC - bit_offset: 1 bit_size: 1 description: LSE ready Interrupt clear enum_write: CSSHSECW name: LSERDYC - bit_offset: 2 bit_size: 1 description: HSI16 ready Interrupt clear enum_write: CSSHSECW name: HSI16RDYC - bit_offset: 3 bit_size: 1 description: HSE ready Interrupt clear enum_write: CSSHSECW name: HSERDYC - bit_offset: 4 bit_size: 1 description: PLL ready Interrupt clear enum_write: CSSHSECW name: PLLRDYC - bit_offset: 5 bit_size: 1 description: MSI ready Interrupt clear enum_write: CSSHSECW name: MSIRDYC - bit_offset: 7 bit_size: 1 description: LSE Clock Security System Interrupt clear enum_write: CSSHSECW name: CSSLSEC - bit_offset: 8 bit_size: 1 description: Clock Security System Interrupt clear enum_write: CSSHSECW name: CSSHSEC - bit_offset: 6 bit_size: 1 description: HSI48 ready Interrupt clear enum_write: CSSHSECW name: HSI48RDYC fieldset/CIER: description: Clock interrupt enable register fields: - bit_offset: 0 bit_size: 1 description: LSI ready interrupt flag enum: MSIRDYIE name: LSIRDYIE - bit_offset: 1 bit_size: 1 description: LSE ready interrupt flag enum: MSIRDYIE name: LSERDYIE - bit_offset: 2 bit_size: 1 description: HSI16 ready interrupt flag enum: MSIRDYIE name: HSI16RDYIE - bit_offset: 3 bit_size: 1 description: HSE ready interrupt flag enum: MSIRDYIE name: HSERDYIE - bit_offset: 4 bit_size: 1 description: PLL ready interrupt flag enum: MSIRDYIE name: PLLRDYIE - bit_offset: 5 bit_size: 1 description: MSI ready interrupt flag enum: MSIRDYIE name: MSIRDYIE - bit_offset: 7 bit_size: 1 description: LSE CSS interrupt flag enum: CSSLSE name: CSSLSE - bit_offset: 6 bit_size: 1 description: HSI48 ready interrupt flag enum: HSIRDYIE name: HSI48RDYIE fieldset/CIFR: description: Clock interrupt flag register fields: - bit_offset: 0 bit_size: 1 description: LSI ready interrupt flag enum_read: MSIRDYFR name: LSIRDYF - bit_offset: 1 bit_size: 1 description: LSE ready interrupt flag enum_read: MSIRDYFR name: LSERDYF - bit_offset: 2 bit_size: 1 description: HSI16 ready interrupt flag enum_read: MSIRDYFR name: HSI16RDYF - bit_offset: 3 bit_size: 1 description: HSE ready interrupt flag enum_read: MSIRDYFR name: HSERDYF - bit_offset: 4 bit_size: 1 description: PLL ready interrupt flag enum_read: MSIRDYFR name: PLLRDYF - bit_offset: 5 bit_size: 1 description: MSI ready interrupt flag enum_read: MSIRDYFR name: MSIRDYF - bit_offset: 7 bit_size: 1 description: LSE Clock Security System Interrupt flag enum: CSSLSEF name: CSSLSEF - bit_offset: 8 bit_size: 1 description: Clock Security System Interrupt flag enum: CSSHSEF name: CSSHSEF - bit_offset: 6 bit_size: 1 description: HSI48 ready interrupt flag enum_read: HSI48RDYFR name: HSI48RDYF fieldset/CR: description: Clock control register fields: - bit_offset: 0 bit_size: 1 description: 16 MHz high-speed internal clock enable name: HSI16ON - bit_offset: 1 bit_size: 1 description: High-speed internal clock enable bit for some IP kernels name: HSI16KERON - bit_offset: 2 bit_size: 1 description: Internal high-speed clock ready flag enum_read: HSIRDYFR name: HSI16RDYF - bit_offset: 3 bit_size: 1 description: HSI16DIVEN name: HSI16DIVEN - bit_offset: 4 bit_size: 1 description: HSI16DIVF enum_read: HSIDIVFR name: HSI16DIVF - bit_offset: 5 bit_size: 1 description: 16 MHz high-speed internal clock output enable name: HSI16OUTEN - bit_offset: 8 bit_size: 1 description: MSI clock enable bit name: MSION - bit_offset: 9 bit_size: 1 description: MSI clock ready flag enum_read: HSERDYR name: MSIRDY - bit_offset: 16 bit_size: 1 description: HSE clock enable bit name: HSEON - bit_offset: 17 bit_size: 1 description: HSE clock ready flag enum_read: HSERDYR name: HSERDY - bit_offset: 18 bit_size: 1 description: HSE clock bypass bit enum: HSEBYP name: HSEBYP - bit_offset: 19 bit_size: 1 description: Clock security system on HSE enable bit name: CSSHSEON - bit_offset: 20 bit_size: 2 description: TC/LCD prescaler enum: RTCPRE name: RTCPRE - bit_offset: 24 bit_size: 1 description: PLL enable bit name: PLLON - bit_offset: 25 bit_size: 1 description: PLL clock ready flag enum_read: PLLRDYR name: PLLRDY fieldset/CRRCR: description: Clock recovery RC register fields: - bit_offset: 0 bit_size: 1 description: 48MHz HSI clock enable bit name: HSI48ON - bit_offset: 1 bit_size: 1 description: 48MHz HSI clock ready flag name: HSI48RDY - bit_offset: 2 bit_size: 1 description: 48 MHz HSI clock divided by 6 output enable name: HSI48DIV6EN - bit_offset: 8 bit_size: 8 description: 48 MHz HSI clock calibration name: HSI48CAL fieldset/CSR: description: Control and status register fields: - bit_offset: 0 bit_size: 1 description: Internal low-speed oscillator enable name: LSION - bit_offset: 1 bit_size: 1 description: Internal low-speed oscillator ready bit enum: LSERDY name: LSIRDY - bit_offset: 8 bit_size: 1 description: External low-speed oscillator enable bit name: LSEON - bit_offset: 9 bit_size: 1 description: External low-speed oscillator ready bit enum: LSERDY name: LSERDY - bit_offset: 10 bit_size: 1 description: External low-speed oscillator bypass bit enum: LSEBYP name: LSEBYP - bit_offset: 11 bit_size: 2 description: LSEDRV enum: LSEDRV name: LSEDRV - bit_offset: 13 bit_size: 1 description: CSSLSEON name: CSSLSEON - bit_offset: 14 bit_size: 1 description: CSS on LSE failure detection flag enum: CSSLSED name: CSSLSED - bit_offset: 16 bit_size: 2 description: RTC and LCD clock source selection bits enum: RTCSEL name: RTCSEL - bit_offset: 18 bit_size: 1 description: RTC clock enable bit name: RTCEN - bit_offset: 19 bit_size: 1 description: RTC software reset bit enum_write: RTCRSTW name: RTCRST - bit_offset: 23 bit_size: 1 description: Remove reset flag enum_write: RMVFW name: RMVF - bit_offset: 24 bit_size: 1 description: Firewall reset flag enum_read: LPWRRSTFR name: FWRSTF - bit_offset: 25 bit_size: 1 description: OBLRSTF enum_read: LPWRRSTFR name: OBLRSTF - bit_offset: 26 bit_size: 1 description: PIN reset flag enum_read: LPWRRSTFR name: PINRSTF - bit_offset: 27 bit_size: 1 description: POR/PDR reset flag enum_read: LPWRRSTFR name: PORRSTF - bit_offset: 28 bit_size: 1 description: Software reset flag enum_read: LPWRRSTFR name: SFTRSTF - bit_offset: 29 bit_size: 1 description: Independent watchdog reset flag enum_read: LPWRRSTFR name: IWDGRSTF - bit_offset: 30 bit_size: 1 description: Window watchdog reset flag enum_read: LPWRRSTFR name: WWDGRSTF - bit_offset: 31 bit_size: 1 description: Low-power reset flag enum_read: LPWRRSTFR name: LPWRRSTF - bit_offset: 31 bit_size: 1 description: Low-power reset flag enum_read: LPWRSTFR name: LPWRSTF fieldset/ICSCR: description: Internal clock sources calibration register fields: - bit_offset: 0 bit_size: 8 description: nternal high speed clock calibration name: HSI16CAL - bit_offset: 8 bit_size: 5 description: High speed internal clock trimming name: HSI16TRIM - bit_offset: 13 bit_size: 3 description: MSI clock ranges enum: MSIRANGE name: MSIRANGE - bit_offset: 16 bit_size: 8 description: MSI clock calibration name: MSICAL - bit_offset: 24 bit_size: 8 description: MSI clock trimming name: MSITRIM fieldset/IOPENR: description: GPIO clock enable register fields: - bit_offset: 0 bit_size: 1 description: IO port A clock enable bit name: IOPAEN - bit_offset: 1 bit_size: 1 description: IO port B clock enable bit name: IOPBEN - bit_offset: 2 bit_size: 1 description: IO port A clock enable bit name: IOPCEN - bit_offset: 3 bit_size: 1 description: I/O port D clock enable bit name: IOPDEN - bit_offset: 4 bit_size: 1 description: IO port E clock enable bit name: IOPEEN - bit_offset: 7 bit_size: 1 description: I/O port H clock enable bit name: IOPHEN fieldset/IOPRSTR: description: GPIO reset register fields: - bit_offset: 0 bit_size: 1 description: I/O port A reset name: IOPARST - bit_offset: 1 bit_size: 1 description: I/O port B reset name: IOPBRST - bit_offset: 2 bit_size: 1 description: I/O port A reset name: IOPCRST - bit_offset: 3 bit_size: 1 description: I/O port D reset name: IOPDRST - bit_offset: 4 bit_size: 1 description: I/O port E reset name: IOPERST - bit_offset: 7 bit_size: 1 description: I/O port H reset name: IOPHRST fieldset/IOPSMEN: description: GPIO clock enable in sleep mode register fields: - bit_offset: 0 bit_size: 1 description: Port A clock enable during Sleep mode bit name: IOPASMEN - bit_offset: 1 bit_size: 1 description: Port B clock enable during Sleep mode bit name: IOPBSMEN - bit_offset: 2 bit_size: 1 description: Port C clock enable during Sleep mode bit name: IOPCSMEN - bit_offset: 3 bit_size: 1 description: Port D clock enable during Sleep mode bit name: IOPDSMEN - bit_offset: 4 bit_size: 1 description: Port E clock enable during Sleep mode bit name: IOPESMEN - bit_offset: 7 bit_size: 1 description: Port H clock enable during Sleep mode bit name: IOPHSMEN