--- block/SYSCFG: description: System configuration controller items: - name: CFGR1 description: configuration register 1 byte_offset: 0 fieldset: CFGR1 - name: CFGR2 description: configuration register 1 byte_offset: 24 fieldset: CFGR2 - name: VREFBUF_CSR description: VREFBUF control and status register byte_offset: 48 fieldset: VREFBUF_CSR - name: VREFBUF_CCR description: VREFBUF calibration control register byte_offset: 52 fieldset: VREFBUF_CCR - name: ITLINE0 description: interrupt line 0 status register byte_offset: 128 access: Read fieldset: ITLINE0 - name: ITLINE1 description: interrupt line 1 status register byte_offset: 132 access: Read fieldset: ITLINE1 - name: ITLINE2 description: interrupt line 2 status register byte_offset: 136 access: Read fieldset: ITLINE2 - name: ITLINE3 description: interrupt line 3 status register byte_offset: 140 access: Read fieldset: ITLINE3 - name: ITLINE4 description: interrupt line 4 status register byte_offset: 144 access: Read fieldset: ITLINE4 - name: ITLINE5 description: interrupt line 5 status register byte_offset: 148 access: Read fieldset: ITLINE5 - name: ITLINE6 description: interrupt line 6 status register byte_offset: 152 access: Read fieldset: ITLINE6 - name: ITLINE7 description: interrupt line 7 status register byte_offset: 156 access: Read fieldset: ITLINE7 - name: ITLINE8 description: interrupt line 8 status register byte_offset: 160 access: Read fieldset: ITLINE8 - name: ITLINE9 description: interrupt line 9 status register byte_offset: 164 access: Read fieldset: ITLINE9 - name: ITLINE10 description: interrupt line 10 status register byte_offset: 168 access: Read fieldset: ITLINE10 - name: ITLINE11 description: interrupt line 11 status register byte_offset: 172 access: Read fieldset: ITLINE11 - name: ITLINE12 description: interrupt line 12 status register byte_offset: 176 access: Read fieldset: ITLINE12 - name: ITLINE13 description: interrupt line 13 status register byte_offset: 180 access: Read fieldset: ITLINE13 - name: ITLINE14 description: interrupt line 14 status register byte_offset: 184 access: Read fieldset: ITLINE14 - name: ITLINE15 description: interrupt line 15 status register byte_offset: 188 access: Read fieldset: ITLINE15 - name: ITLINE16 description: interrupt line 16 status register byte_offset: 192 access: Read fieldset: ITLINE16 - name: ITLINE17 description: interrupt line 17 status register byte_offset: 196 access: Read fieldset: ITLINE17 - name: ITLINE18 description: interrupt line 18 status register byte_offset: 200 access: Read fieldset: ITLINE18 - name: ITLINE19 description: interrupt line 19 status register byte_offset: 204 access: Read fieldset: ITLINE19 - name: ITLINE20 description: interrupt line 20 status register byte_offset: 208 access: Read fieldset: ITLINE20 - name: ITLINE21 description: interrupt line 21 status register byte_offset: 212 access: Read fieldset: ITLINE21 - name: ITLINE22 description: interrupt line 22 status register byte_offset: 216 access: Read fieldset: ITLINE22 - name: ITLINE23 description: interrupt line 23 status register byte_offset: 220 access: Read fieldset: ITLINE23 - name: ITLINE24 description: interrupt line 24 status register byte_offset: 224 access: Read fieldset: ITLINE24 - name: ITLINE25 description: interrupt line 25 status register byte_offset: 228 access: Read fieldset: ITLINE25 - name: ITLINE26 description: interrupt line 26 status register byte_offset: 232 access: Read fieldset: ITLINE26 - name: ITLINE27 description: interrupt line 27 status register byte_offset: 236 access: Read fieldset: ITLINE27 - name: ITLINE28 description: interrupt line 28 status register byte_offset: 240 access: Read fieldset: ITLINE28 - name: ITLINE29 description: interrupt line 29 status register byte_offset: 244 access: Read fieldset: ITLINE29 - name: ITLINE30 description: interrupt line 30 status register byte_offset: 248 access: Read fieldset: ITLINE30 - name: ITLINE31 description: interrupt line 31 status register byte_offset: 252 access: Read fieldset: ITLINE31 fieldset/CFGR1: description: configuration register 1 fields: - name: MEM_MODE description: "Memory mapping selection bits. This bitfield controlled by software selects the memory internally mapped at the address 0x0000_0000. Its reset value is determined by the boot mode configuration. Refer to Reference Manual section 2.5 for more details." bit_offset: 0 bit_size: 2 enum: MEM_MODE - name: PA11_RMP description: "PA11 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA11 pin to operate as PA9 GPIO port, instead as PA11 GPIO port." bit_offset: 3 bit_size: 1 - name: PA12_RMP description: "PA12 pin remapping\r This bit is set and cleared by software. When set, it remaps the PA12 pin to operate as PA10 GPIO port, instead as PA12 GPIO port." bit_offset: 4 bit_size: 1 - name: IR_POL description: IR output polarity selection bit_offset: 5 bit_size: 1 - name: IR_MOD description: IR Modulation Envelope signal selection. bit_offset: 6 bit_size: 2 - name: BOOSTEN description: I/O analog switch voltage booster enable bit_offset: 8 bit_size: 1 - name: UCPD1_STROBE description: Strobe signal bit for UCPD1 bit_offset: 9 bit_size: 1 - name: UCPD2_STROBE description: Strobe signal bit for UCPD2 bit_offset: 10 bit_size: 1 - name: I2C_PBx_FMP description: Fast Mode Plus (FM+) driving capability activation bits bit_offset: 16 bit_size: 4 - name: I2C1_FMP description: FM+ driving capability activation for I2C1 bit_offset: 20 bit_size: 1 - name: I2C2_FMP description: FM+ driving capability activation for I2C2 bit_offset: 21 bit_size: 1 - name: I2C_PAx_FMP description: Fast Mode Plus (FM+) driving capability activation bits bit_offset: 22 bit_size: 2 fieldset/CFGR2: description: configuration register 1 fields: - name: LOCKUP_LOCK description: Cortex-M0+ LOCKUP bit enable bit bit_offset: 0 bit_size: 1 - name: SRAM_PARITY_LOCK description: SRAM parity lock bit bit_offset: 1 bit_size: 1 - name: PVD_LOCK description: PVD lock enable bit bit_offset: 2 bit_size: 1 - name: ECC_LOCK description: ECC error lock bit bit_offset: 3 bit_size: 1 - name: SRAM_PEF description: SRAM parity error flag bit_offset: 8 bit_size: 1 - name: PA1_CDEN description: PA1_CDEN bit_offset: 16 bit_size: 1 - name: PA3_CDEN description: PA3_CDEN bit_offset: 17 bit_size: 1 - name: PA5_CDEN description: PA5_CDEN bit_offset: 18 bit_size: 1 - name: PA6_CDEN description: PA6_CDEN bit_offset: 19 bit_size: 1 - name: PA13_CDEN description: PA13_CDEN bit_offset: 20 bit_size: 1 - name: PB0_CDEN description: PB0_CDEN bit_offset: 21 bit_size: 1 - name: PB1_CDEN description: PB1_CDEN bit_offset: 22 bit_size: 1 - name: PB2_CDEN description: PB2_CDEN bit_offset: 23 bit_size: 1 fieldset/ITLINE0: description: interrupt line 0 status register fields: - name: WWDG description: Window watchdog interrupt pending flag bit_offset: 0 bit_size: 1 fieldset/ITLINE1: description: interrupt line 1 status register fields: - name: PVDOUT description: PVD supply monitoring interrupt request pending (EXTI line 16). bit_offset: 0 bit_size: 1 fieldset/ITLINE10: description: interrupt line 10 status register fields: - name: DMA1_CH2 description: DMA1_CH1 bit_offset: 0 bit_size: 1 - name: DMA1_CH3 description: DMA1_CH3 bit_offset: 1 bit_size: 1 fieldset/ITLINE11: description: interrupt line 11 status register fields: - name: DMAMUX description: DMAMUX bit_offset: 0 bit_size: 1 - name: DMA1_CH4 description: DMA1_CH4 bit_offset: 1 bit_size: 1 - name: DMA1_CH5 description: DMA1_CH5 bit_offset: 2 bit_size: 1 - name: DMA1_CH6 description: DMA1_CH6 bit_offset: 3 bit_size: 1 - name: DMA1_CH7 description: DMA1_CH7 bit_offset: 4 bit_size: 1 fieldset/ITLINE12: description: interrupt line 12 status register fields: - name: ADC description: ADC bit_offset: 0 bit_size: 1 - name: COMP description: COMP1 bit_offset: 1 bit_size: 1 array: len: 2 stride: 1 fieldset/ITLINE13: description: interrupt line 13 status register fields: - name: TIM1_CCU description: TIM1_CCU bit_offset: 0 bit_size: 1 - name: TIM1_TRG description: TIM1_TRG bit_offset: 1 bit_size: 1 - name: TIM1_UPD description: TIM1_UPD bit_offset: 2 bit_size: 1 - name: TIM1_BRK description: TIM1_BRK bit_offset: 3 bit_size: 1 fieldset/ITLINE14: description: interrupt line 14 status register fields: - name: TIM1_CC description: TIM1_CC bit_offset: 0 bit_size: 1 fieldset/ITLINE15: description: interrupt line 15 status register fields: - name: TIM description: TIM2 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE16: description: interrupt line 16 status register fields: - name: TIM description: TIM3 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE17: description: interrupt line 17 status register fields: - name: TIM description: TIM6 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 - name: DAC description: DAC bit_offset: 1 bit_size: 1 - name: LPTIM description: LPTIM1 bit_offset: 2 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE18: description: interrupt line 18 status register fields: - name: TIM description: TIM7 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 - name: LPTIM description: LPTIM2 bit_offset: 1 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE19: description: interrupt line 19 status register fields: - name: TIM description: TIM14 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE2: description: interrupt line 2 status register fields: - name: TAMP description: TAMP bit_offset: 0 bit_size: 1 - name: RTC description: RTC bit_offset: 1 bit_size: 1 fieldset/ITLINE20: description: interrupt line 20 status register fields: - name: TIM description: TIM15 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE21: description: interrupt line 21 status register fields: - name: TIM description: TIM16 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE22: description: interrupt line 22 status register fields: - name: TIM description: TIM17 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE23: description: interrupt line 23 status register fields: - name: I2C1 description: I2C1 bit_offset: 0 bit_size: 1 fieldset/ITLINE24: description: interrupt line 24 status register fields: - name: I2C2 description: I2C2 bit_offset: 0 bit_size: 1 fieldset/ITLINE25: description: interrupt line 25 status register fields: - name: SPI description: SPI1 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE26: description: interrupt line 26 status register fields: - name: SPI description: SPI2 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE27: description: interrupt line 27 status register fields: - name: USART description: USART1 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE28: description: interrupt line 28 status register fields: - name: USART description: USART2 bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE29: description: interrupt line 29 status register fields: - name: USART description: USART3 bit_offset: 0 bit_size: 1 array: len: 3 stride: 1 fieldset/ITLINE3: description: interrupt line 3 status register fields: - name: FLASH_ITF description: FLASH_ITF bit_offset: 0 bit_size: 1 - name: FLASH_ECC description: FLASH_ECC bit_offset: 1 bit_size: 1 fieldset/ITLINE30: description: interrupt line 30 status register fields: - name: USART description: CEC bit_offset: 0 bit_size: 1 array: len: 1 stride: 0 fieldset/ITLINE31: description: interrupt line 31 status register fields: - name: RNG description: RNG bit_offset: 0 bit_size: 1 - name: AES description: AES bit_offset: 1 bit_size: 1 fieldset/ITLINE4: description: interrupt line 4 status register fields: - name: RCC description: RCC bit_offset: 0 bit_size: 1 fieldset/ITLINE5: description: interrupt line 5 status register fields: - name: EXTI description: EXTI bit_offset: 0 bit_size: 1 array: len: 2 stride: 1 fieldset/ITLINE6: description: interrupt line 6 status register fields: - name: EXTI description: EXTI bit_offset: 0 bit_size: 1 array: len: 2 stride: 1 fieldset/ITLINE7: description: interrupt line 7 status register fields: - name: EXTI description: EXTI bit_offset: 0 bit_size: 1 array: len: 12 stride: 1 fieldset/ITLINE8: description: interrupt line 8 status register fields: - name: UCPD description: UCPD1 bit_offset: 0 bit_size: 1 array: len: 2 stride: 1 fieldset/ITLINE9: description: interrupt line 9 status register fields: - name: DMA1_CH1 description: DMA1_CH1 bit_offset: 0 bit_size: 1 fieldset/VREFBUF_CCR: description: VREFBUF calibration control register fields: - name: TRIM description: Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage. bit_offset: 0 bit_size: 6 fieldset/VREFBUF_CSR: description: VREFBUF control and status register fields: - name: ENVR description: Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode. bit_offset: 0 bit_size: 1 - name: HIZ description: "High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration." bit_offset: 1 bit_size: 1 - name: VRR description: Voltage reference buffer ready bit_offset: 3 bit_size: 1 - name: VRS description: "Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved" bit_offset: 4 bit_size: 3 enum/MEM_MODE: bit_size: 2 variants: - name: MAIN_FLASH description: Main Flash memory mapped at address 0 value: 0 - name: MAIN_FLASH_ALT description: Main Flash memory mapped at address 0 (alternate encoding) value: 2 - name: SYSTEM_FLASH description: System Flash memory mapped at address 0 value: 1 - name: SRAM description: Embedded SRAM mapped at address 0 value: 3