--- block/FDCAN: description: FDCAN items: - name: CREL description: FDCAN Core Release Register byte_offset: 0 access: Read fieldset: CREL - name: ENDN description: FDCAN Core Release Register byte_offset: 4 access: Read fieldset: ENDN - name: DBTP description: "This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point." byte_offset: 12 fieldset: DBTP - name: TEST description: "Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus." byte_offset: 16 fieldset: TEST - name: RWD description: "The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock." byte_offset: 20 fieldset: RWD - name: CCCR description: For details about setting and resetting of single bits see Software initialization. byte_offset: 24 fieldset: CCCR - name: NBTP description: FDCAN_NBTP byte_offset: 28 fieldset: NBTP - name: TSCC description: FDCAN Timestamp Counter Configuration Register byte_offset: 32 fieldset: TSCC - name: TSCV description: FDCAN Timestamp Counter Value Register byte_offset: 36 fieldset: TSCV - name: TOCC description: FDCAN Timeout Counter Configuration Register byte_offset: 40 fieldset: TOCC - name: TOCV description: FDCAN Timeout Counter Value Register byte_offset: 44 fieldset: TOCV - name: ECR description: FDCAN Error Counter Register byte_offset: 64 access: Read fieldset: ECR - name: PSR description: FDCAN Protocol Status Register byte_offset: 68 fieldset: PSR - name: TDCR description: FDCAN Transmitter Delay Compensation Register byte_offset: 72 fieldset: TDCR - name: IR description: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. byte_offset: 80 fieldset: IR - name: IE description: The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. byte_offset: 84 fieldset: IE - name: ILS description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]." byte_offset: 88 fieldset: ILS - name: ILE description: Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. byte_offset: 92 fieldset: ILE - name: RXGFC description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path." byte_offset: 128 fieldset: RXGFC - name: XIDAM description: FDCAN Extended ID and Mask Register byte_offset: 132 fieldset: XIDAM - name: HPMS description: This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. byte_offset: 136 access: Read fieldset: HPMS - name: RXFS description: FDCAN Rx FIFO X Status Register byte_offset: 144 fieldset: RXFS access: Read array: offsets: - 0 - 8 - name: RXFA description: CAN Rx FIFO 0 Acknowledge Register byte_offset: 148 fieldset: RXFA array: offsets: - 0 - 8 - name: TXBC description: FDCAN Tx Buffer Configuration Register byte_offset: 192 fieldset: TXBC - name: TXFQS description: The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). byte_offset: 196 access: Read fieldset: TXFQS - name: TXBRP description: FDCAN Tx Buffer Request Pending Register byte_offset: 200 access: Read fieldset: TXBRP - name: TXBAR description: FDCAN Tx Buffer Add Request Register byte_offset: 204 fieldset: TXBAR - name: TXBCR description: FDCAN Tx Buffer Cancellation Request Register byte_offset: 208 fieldset: TXBCR - name: TXBTO description: FDCAN Tx Buffer Transmission Occurred Register byte_offset: 212 access: Read fieldset: TXBTO - name: TXBCF description: FDCAN Tx Buffer Cancellation Finished Register byte_offset: 216 access: Read fieldset: TXBCF - name: TXBTIE description: FDCAN Tx Buffer Transmission Interrupt Enable Register byte_offset: 220 fieldset: TXBTIE - name: TXBCIE description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register byte_offset: 224 fieldset: TXBCIE - name: TXEFS description: FDCAN Tx Event FIFO Status Register byte_offset: 228 access: Read fieldset: TXEFS - name: TXEFA description: FDCAN Tx Event FIFO Acknowledge Register byte_offset: 232 fieldset: TXEFA - name: CKDIV description: FDCAN CFG clock divider register byte_offset: 256 fieldset: CKDIV fieldset/CCCR: description: For details about setting and resetting of single bits see Software initialization. fields: - name: INIT description: INIT bit_offset: 0 bit_size: 1 - name: CCE description: CCE bit_offset: 1 bit_size: 1 - name: ASM description: ASM bit_offset: 2 bit_size: 1 - name: CSA description: CSA bit_offset: 3 bit_size: 1 - name: CSR description: CSR bit_offset: 4 bit_size: 1 - name: MON description: MON bit_offset: 5 bit_size: 1 - name: DAR description: DAR bit_offset: 6 bit_size: 1 - name: TEST description: TEST bit_offset: 7 bit_size: 1 - name: FDOE description: FDOE bit_offset: 8 bit_size: 1 - name: BRSE description: BRSE bit_offset: 9 bit_size: 1 - name: PXHD description: PXHD bit_offset: 12 bit_size: 1 - name: EFBI description: EFBI bit_offset: 13 bit_size: 1 - name: TXP description: TXP bit_offset: 14 bit_size: 1 - name: NISO description: NISO bit_offset: 15 bit_size: 1 fieldset/CKDIV: description: FDCAN CFG clock divider register fields: - name: PDIV description: input clock divider. the APB clock could be divided prior to be used by the CAN sub bit_offset: 0 bit_size: 4 fieldset/CREL: description: FDCAN Core Release Register fields: - name: DAY description: DAY bit_offset: 0 bit_size: 8 - name: MON description: MON bit_offset: 8 bit_size: 8 - name: YEAR description: YEAR bit_offset: 16 bit_size: 4 - name: SUBSTEP description: SUBSTEP bit_offset: 20 bit_size: 4 - name: STEP description: STEP bit_offset: 24 bit_size: 4 - name: REL description: REL bit_offset: 28 bit_size: 4 fieldset/DBTP: description: "This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point." fields: - name: DSJW description: DSJW bit_offset: 0 bit_size: 4 - name: DTSEG2 description: DTSEG2 bit_offset: 4 bit_size: 4 - name: DTSEG1 description: DTSEG1 bit_offset: 8 bit_size: 5 - name: DBRP description: DBRP bit_offset: 16 bit_size: 5 - name: TDC description: TDC bit_offset: 23 bit_size: 1 fieldset/ECR: description: FDCAN Error Counter Register fields: - name: TEC description: TEC bit_offset: 0 bit_size: 8 - name: REC description: TREC bit_offset: 8 bit_size: 7 - name: RP description: RP bit_offset: 15 bit_size: 1 - name: CEL description: CEL bit_offset: 16 bit_size: 8 fieldset/ENDN: description: FDCAN Core Release Register fields: - name: ETV description: ETV bit_offset: 0 bit_size: 32 fieldset/HPMS: description: This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. fields: - name: BIDX description: BIDX bit_offset: 0 bit_size: 6 - name: MSI description: MSI bit_offset: 6 bit_size: 2 - name: FIDX description: FIDX bit_offset: 8 bit_size: 7 - name: FLST description: FLST bit_offset: 15 bit_size: 1 fieldset/IE: description: The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. fields: - name: RFNE description: Rx FIFO X new message enable bit_offset: 0 bit_size: 1 array: offsets: - 0 - 3 - name: RFFE description: Rx FIFO X full enable bit_offset: 1 bit_size: 1 array: offsets: - 0 - 3 - name: RFLE description: Rx FIFO X message lost enable bit_offset: 2 bit_size: 1 array: offsets: - 0 - 3 - name: HPME description: High-priority message enable bit_offset: 6 bit_size: 1 - name: TCE description: Transmission completed enable bit_offset: 7 bit_size: 1 - name: TCFE description: Transmission cancellation finished enable bit_offset: 8 bit_size: 1 - name: TFEE description: Tx FIFO empty enable bit_offset: 9 bit_size: 1 - name: TEFNE description: Tx even FIFO new entry enable bit_offset: 10 bit_size: 1 - name: TEFFE description: Tx event FIFO full enable bit_offset: 11 bit_size: 1 - name: TEFLE description: Tx event FIFO element lost enable bit_offset: 12 bit_size: 1 - name: TSWE description: Timestamp wraparound enable bit_offset: 13 bit_size: 1 - name: MRAFE description: Message RAM access failure enable bit_offset: 14 bit_size: 1 - name: TOOE description: Timeout occurred enable bit_offset: 15 bit_size: 1 - name: ELOE description: Error logging overflow enable bit_offset: 16 bit_size: 1 - name: EPE description: Error passive enable bit_offset: 17 bit_size: 1 - name: EWE description: Warning status enable bit_offset: 18 bit_size: 1 - name: BOE description: Bus_off status enable bit_offset: 19 bit_size: 1 - name: WDIE description: Watchdog interrupt enable bit_offset: 20 bit_size: 1 - name: PEAE description: Protocol error in arbitration phase enable bit_offset: 21 bit_size: 1 - name: PEDE description: Protocol error in data phase enable bit_offset: 22 bit_size: 1 - name: ARAE description: Access to reserved address enable bit_offset: 23 bit_size: 1 fieldset/ILE: description: Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. fields: - name: EINT0 description: EINT0 bit_offset: 0 bit_size: 1 - name: EINT1 description: EINT1 bit_offset: 1 bit_size: 1 fieldset/ILS: description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]." fields: - name: RXFIFO description: RX FIFO bit grouping the following interruption bit_offset: 0 bit_size: 1 array: len: 2 stride: 1 - name: SMSG description: Status message bit grouping the following interruption bit_offset: 2 bit_size: 1 - name: TFERR description: TX FIFO error grouping the following interruption bit_offset: 3 bit_size: 1 - name: MISC description: Interrupt regrouping the following interruption bit_offset: 4 bit_size: 1 - name: BERR description: Bit and line error grouping the following interruption bit_offset: 5 bit_size: 1 - name: PERR description: Protocol error grouping the following interruption bit_offset: 6 bit_size: 1 fieldset/IR: description: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. fields: - name: RFN description: Rx FIFO X new message bit_offset: 0 bit_size: 1 array: offsets: - 0 - 3 - name: RFF description: Rx FIFO X full bit_offset: 1 bit_size: 1 array: offsets: - 0 - 3 - name: RFL description: Rx FIFO X message lost bit_offset: 2 bit_size: 1 array: offsets: - 0 - 3 - name: HPM description: High-priority message bit_offset: 6 bit_size: 1 - name: TC description: Transmission completed bit_offset: 7 bit_size: 1 - name: TCF description: Transmission cancellation finished bit_offset: 8 bit_size: 1 - name: TFE description: Tx FIFO empty bit_offset: 9 bit_size: 1 - name: TEFN description: Tx even FIFO new entry bit_offset: 10 bit_size: 1 - name: TEFF description: Tx event FIFO full bit_offset: 11 bit_size: 1 - name: TEFL description: Tx event FIFO element lost bit_offset: 12 bit_size: 1 - name: TSW description: Timestamp wraparound bit_offset: 13 bit_size: 1 - name: MRAF description: Message RAM access failure bit_offset: 14 bit_size: 1 - name: TOO description: Timeout occurred bit_offset: 15 bit_size: 1 - name: ELO description: Error logging overflow bit_offset: 16 bit_size: 1 - name: EP description: Error passive bit_offset: 17 bit_size: 1 - name: EW description: Warning status bit_offset: 18 bit_size: 1 - name: BO description: Bus_off status bit_offset: 19 bit_size: 1 - name: WDI description: Watchdog interrupt bit_offset: 20 bit_size: 1 - name: PEA description: Protocol error in arbitration phase bit_offset: 21 bit_size: 1 - name: PED description: Protocol error in data phase bit_offset: 22 bit_size: 1 - name: ARA description: Access to reserved address bit_offset: 23 bit_size: 1 fieldset/NBTP: description: FDCAN_NBTP fields: - name: NTSEG2 description: TSEG2 bit_offset: 0 bit_size: 7 - name: NTSEG1 description: NTSEG1 bit_offset: 8 bit_size: 8 - name: NBRP description: NBRP bit_offset: 16 bit_size: 9 - name: NSJW description: NSJW bit_offset: 25 bit_size: 7 fieldset/PSR: description: FDCAN Protocol Status Register fields: - name: LEC description: LEC bit_offset: 0 bit_size: 3 - name: ACT description: ACT bit_offset: 3 bit_size: 2 - name: EP description: EP bit_offset: 5 bit_size: 1 - name: EW description: EW bit_offset: 6 bit_size: 1 - name: BO description: BO bit_offset: 7 bit_size: 1 - name: DLEC description: DLEC bit_offset: 8 bit_size: 3 - name: RESI description: RESI bit_offset: 11 bit_size: 1 - name: RBRS description: RBRS bit_offset: 12 bit_size: 1 - name: REDL description: REDL bit_offset: 13 bit_size: 1 - name: PXE description: PXE bit_offset: 14 bit_size: 1 - name: TDCV description: TDCV bit_offset: 16 bit_size: 7 fieldset/RWD: description: "The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock." fields: - name: WDC description: WDC bit_offset: 0 bit_size: 8 - name: WDV description: WDV bit_offset: 8 bit_size: 8 fieldset/RXFA: description: CAN Rx FIFO X Acknowledge Register fields: - name: FAI description: FAI bit_offset: 0 bit_size: 6 fieldset/RXFS: description: FDCAN Rx FIFO X Status Register fields: - name: FFL description: FFL bit_offset: 0 bit_size: 7 - name: FGI description: FGI bit_offset: 8 bit_size: 6 - name: FPI description: FPI bit_offset: 16 bit_size: 6 - name: FF description: FF bit_offset: 24 bit_size: 1 - name: RFL description: RFL bit_offset: 25 bit_size: 1 fieldset/RXGFC: description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path." fields: - name: RRFE description: RRFE bit_offset: 0 bit_size: 1 - name: RRFS description: RRFS bit_offset: 1 bit_size: 1 - name: ANFE description: ANFE bit_offset: 2 bit_size: 2 - name: ANFS description: ANFS bit_offset: 4 bit_size: 2 - name: F1OM description: FIFO 1 operation mode bit_offset: 8 bit_size: 1 - name: F0OM description: FIFO 0 operation mode bit_offset: 9 bit_size: 1 - name: LSS description: List size standard bit_offset: 16 bit_size: 5 - name: LSE description: List size extended bit_offset: 24 bit_size: 4 fieldset/TDCR: description: FDCAN Transmitter Delay Compensation Register fields: - name: TDCF description: TDCF bit_offset: 0 bit_size: 7 - name: TDCO description: TDCO bit_offset: 8 bit_size: 7 fieldset/TEST: description: "Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus." fields: - name: LBCK description: LBCK bit_offset: 4 bit_size: 1 - name: TX description: TX bit_offset: 5 bit_size: 2 - name: RX description: RX bit_offset: 7 bit_size: 1 fieldset/TOCC: description: FDCAN Timeout Counter Configuration Register fields: - name: ETOC description: ETOC bit_offset: 0 bit_size: 1 - name: TOS description: TOS bit_offset: 1 bit_size: 2 - name: TOP description: TOP bit_offset: 16 bit_size: 16 fieldset/TOCV: description: FDCAN Timeout Counter Value Register fields: - name: TOC description: TOC bit_offset: 0 bit_size: 16 fieldset/TSCC: description: FDCAN Timestamp Counter Configuration Register fields: - name: TSS description: TSS bit_offset: 0 bit_size: 2 - name: TCP description: TCP bit_offset: 16 bit_size: 4 fieldset/TSCV: description: FDCAN Timestamp Counter Value Register fields: - name: TSC description: TSC bit_offset: 0 bit_size: 16 fieldset/TXBAR: description: FDCAN Tx Buffer Add Request Register fields: - name: AR description: AR bit_offset: 0 bit_size: 3 fieldset/TXBC: description: FDCAN Tx Buffer Configuration Register fields: - name: TBSA description: TBSA bit_offset: 2 bit_size: 14 - name: NDTB description: NDTB bit_offset: 16 bit_size: 6 - name: TFQS description: TFQS bit_offset: 24 bit_size: 6 - name: TFQM description: TFQM bit_offset: 30 bit_size: 1 fieldset/TXBCF: description: FDCAN Tx Buffer Cancellation Finished Register fields: - name: CF description: CF bit_offset: 0 bit_size: 3 fieldset/TXBCIE: description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register fields: - name: CFIE description: CFIE bit_offset: 0 bit_size: 3 fieldset/TXBCR: description: FDCAN Tx Buffer Cancellation Request Register fields: - name: CR description: CR bit_offset: 0 bit_size: 3 fieldset/TXBRP: description: FDCAN Tx Buffer Request Pending Register fields: - name: TRP description: TRP bit_offset: 0 bit_size: 3 fieldset/TXBTIE: description: FDCAN Tx Buffer Transmission Interrupt Enable Register fields: - name: TIE description: TIE bit_offset: 0 bit_size: 3 fieldset/TXBTO: description: FDCAN Tx Buffer Transmission Occurred Register fields: - name: TO description: TO bit_offset: 0 bit_size: 3 fieldset/TXEFA: description: FDCAN Tx Event FIFO Acknowledge Register fields: - name: EFAI description: EFAI bit_offset: 0 bit_size: 5 fieldset/TXEFS: description: FDCAN Tx Event FIFO Status Register fields: - name: EFFL description: EFFL bit_offset: 0 bit_size: 3 - name: EFGI description: EFGI bit_offset: 8 bit_size: 2 - name: EFPI description: EFPI bit_offset: 16 bit_size: 2 - name: EFF description: EFF bit_offset: 24 bit_size: 1 - name: TEFL description: TEFL bit_offset: 25 bit_size: 1 fieldset/TXFQS: description: The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). fields: - name: TFFL description: TFFL bit_offset: 0 bit_size: 3 - name: TFGI description: TFGI bit_offset: 8 bit_size: 2 - name: TFQPI description: TFQPI bit_offset: 16 bit_size: 2 - name: TFQF description: TFQF bit_offset: 21 bit_size: 1 fieldset/XIDAM: description: FDCAN Extended ID and Mask Register fields: - name: EIDM description: EIDM bit_offset: 0 bit_size: 29