block/RCC: description: Reset and clock control items: - name: CR description: Clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register byte_offset: 8 fieldset: CFGR - name: PLLCFGR description: PLL configuration register byte_offset: 12 fieldset: PLLCFGR - name: CIER description: Clock interrupt enable register byte_offset: 24 fieldset: CIER - name: CIFR description: Clock interrupt flag register byte_offset: 28 access: Read fieldset: CIFR - name: CICR description: Clock interrupt clear register byte_offset: 32 access: Write fieldset: CICR - name: AHB1RSTR description: AHB1 peripheral reset register byte_offset: 40 fieldset: AHB1RSTR - name: AHB2RSTR description: AHB2 peripheral reset register byte_offset: 44 fieldset: AHB2RSTR - name: AHB3RSTR description: AHB3 peripheral reset register byte_offset: 48 fieldset: AHB3RSTR - name: APB1RSTR1 description: APB1 peripheral reset register 1 byte_offset: 56 fieldset: APB1RSTR1 - name: APB1RSTR2 description: APB1 peripheral reset register 2 byte_offset: 60 fieldset: APB1RSTR2 - name: APB2RSTR description: APB2 peripheral reset register byte_offset: 64 fieldset: APB2RSTR - name: AHB1ENR description: AHB1 peripheral clock enable register byte_offset: 72 fieldset: AHB1ENR - name: AHB2ENR description: AHB2 peripheral clock enable register byte_offset: 76 fieldset: AHB2ENR - name: AHB3ENR description: AHB3 peripheral clock enable register byte_offset: 80 fieldset: AHB3ENR - name: APB1ENR1 description: APB1ENR1 byte_offset: 88 fieldset: APB1ENR1 - name: APB1ENR2 description: APB1 peripheral clock enable register 2 byte_offset: 92 fieldset: APB1ENR2 - name: APB2ENR description: APB2ENR byte_offset: 96 fieldset: APB2ENR - name: AHB1SMENR description: AHB1 peripheral clocks enable in Sleep and Stop modes register byte_offset: 104 fieldset: AHB1SMENR - name: AHB2SMENR description: AHB2 peripheral clocks enable in Sleep and Stop modes register byte_offset: 108 fieldset: AHB2SMENR - name: AHB3SMENR description: AHB3 peripheral clocks enable in Sleep and Stop modes register byte_offset: 112 fieldset: AHB3SMENR - name: APB1SMENR1 description: APB1SMENR1 byte_offset: 120 fieldset: APB1SMENR1 - name: APB1SMENR2 description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 byte_offset: 124 fieldset: APB1SMENR2 - name: APB2SMENR description: APB2SMENR byte_offset: 128 fieldset: APB2SMENR - name: CCIPR description: CCIPR byte_offset: 136 fieldset: CCIPR - name: BDCR description: BDCR byte_offset: 144 fieldset: BDCR - name: CSR description: CSR byte_offset: 148 fieldset: CSR - name: CRRCR description: Clock recovery RC register byte_offset: 152 fieldset: CRRCR - name: CCIPR2 description: Peripherals independent clock configuration register byte_offset: 156 fieldset: CCIPR2 fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - name: DMA1EN description: DMA1 clock enable bit_offset: 0 bit_size: 1 - name: DMA2EN description: DMA2 clock enable bit_offset: 1 bit_size: 1 - name: DMAMUX1EN description: DMAMUX clock enable bit_offset: 2 bit_size: 1 - name: CORDICEN description: CORDIC clock enable bit_offset: 3 bit_size: 1 - name: FMACEN description: FMAC clock enable bit_offset: 4 bit_size: 1 - name: FLASHEN description: Flash memory interface clock enable bit_offset: 8 bit_size: 1 - name: CRCEN description: CRC clock enable bit_offset: 12 bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - name: DMA1RST description: DMA1 reset bit_offset: 0 bit_size: 1 - name: DMA2RST description: DMA2 reset bit_offset: 1 bit_size: 1 - name: DMAMUX1RST description: DMAMUX1RST bit_offset: 2 bit_size: 1 - name: CORDICRST description: CORDIC reset bit_offset: 3 bit_size: 1 - name: FMACRST description: FMAC reset bit_offset: 4 bit_size: 1 - name: FLASHRST description: Flash memory interface reset bit_offset: 8 bit_size: 1 - name: CRCRST description: CRC reset bit_offset: 12 bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep and Stop modes register fields: - name: DMA1SMEN description: DMA1 clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: DMA2 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: DMAMUX1SMEN description: DMAMUX clock enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: CORDICSMEN description: CORDIC clock enable during sleep mode bit_offset: 3 bit_size: 1 - name: FMACSMEN description: FMACSM clock enable bit_offset: 4 bit_size: 1 - name: FLASHSMEN description: Flash memory interface clocks enable during Sleep and Stop modes bit_offset: 8 bit_size: 1 - name: SRAM1SMEN description: SRAM1 interface clocks enable during Sleep and Stop modes bit_offset: 9 bit_size: 1 - name: CRCSMEN description: CRCSMEN bit_offset: 12 bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - name: GPIOAEN description: IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: IO port C clock enable bit_offset: 2 bit_size: 1 - name: GPIODEN description: IO port D clock enable bit_offset: 3 bit_size: 1 - name: GPIOEEN description: IO port E clock enable bit_offset: 4 bit_size: 1 - name: GPIOFEN description: IO port F clock enable bit_offset: 5 bit_size: 1 - name: GPIOGEN description: IO port G clock enable bit_offset: 6 bit_size: 1 - name: ADC12EN description: ADC clock enable bit_offset: 13 bit_size: 1 - name: ADC345EN description: DCMI clock enable bit_offset: 14 bit_size: 1 - name: DAC1EN description: AES accelerator clock enable bit_offset: 16 bit_size: 1 - name: DAC2EN description: HASH clock enable bit_offset: 17 bit_size: 1 - name: DAC3EN description: Random Number Generator clock enable bit_offset: 18 bit_size: 1 - name: DAC4EN description: DAC4 clock enable bit_offset: 19 bit_size: 1 - name: AESEN description: AES clock enable bit_offset: 24 bit_size: 1 - name: RNGEN description: Random Number Generator clock enable bit_offset: 26 bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - name: GPIOARST description: IO port A reset bit_offset: 0 bit_size: 1 - name: GPIOBRST description: IO port B reset bit_offset: 1 bit_size: 1 - name: GPIOCRST description: IO port C reset bit_offset: 2 bit_size: 1 - name: GPIODRST description: IO port D reset bit_offset: 3 bit_size: 1 - name: GPIOERST description: IO port E reset bit_offset: 4 bit_size: 1 - name: GPIOFRST description: IO port F reset bit_offset: 5 bit_size: 1 - name: GPIOGRST description: IO port G reset bit_offset: 6 bit_size: 1 - name: ADC12RST description: ADC reset bit_offset: 13 bit_size: 1 - name: ADC345RST description: SAR ADC345 interface reset bit_offset: 14 bit_size: 1 - name: DAC1RST description: DAC1 interface reset bit_offset: 16 bit_size: 1 - name: DAC2RST description: DAC2 interface reset bit_offset: 17 bit_size: 1 - name: DAC3RST description: DAC3 interface reset bit_offset: 18 bit_size: 1 - name: DAC4RST description: DAC4 interface reset bit_offset: 19 bit_size: 1 - name: AESRST description: Cryptography module reset bit_offset: 24 bit_size: 1 - name: RNGRST description: Random Number Generator module reset bit_offset: 26 bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep and Stop modes register fields: - name: GPIOASMEN description: IO port A clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: IO port B clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: IO port C clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: IO port D clocks enable during Sleep and Stop modes bit_offset: 3 bit_size: 1 - name: GPIOESMEN description: IO port E clocks enable during Sleep and Stop modes bit_offset: 4 bit_size: 1 - name: GPIOFSMEN description: IO port F clocks enable during Sleep and Stop modes bit_offset: 5 bit_size: 1 - name: GPIOGSMEN description: IO port G clocks enable during Sleep and Stop modes bit_offset: 6 bit_size: 1 - name: CCMSRAMSMEN description: CCM SRAM interface clocks enable during Sleep and Stop modes bit_offset: 9 bit_size: 1 - name: SRAM2SMEN description: SRAM2 interface clocks enable during Sleep and Stop modes bit_offset: 10 bit_size: 1 - name: ADC12SMEN description: ADC clocks enable during Sleep and Stop modes bit_offset: 13 bit_size: 1 - name: ADC345SMEN description: DCMI clock enable during Sleep and Stop modes bit_offset: 14 bit_size: 1 - name: DAC1SMEN description: AES accelerator clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: DAC2SMEN description: HASH clock enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: DAC3SMEN description: DAC3 clock enable during sleep mode bit_offset: 18 bit_size: 1 - name: DAC4SMEN description: DAC4 clock enable during sleep mode bit_offset: 19 bit_size: 1 - name: AESMEN description: Cryptography clock enable during sleep mode bit_offset: 24 bit_size: 1 - name: RNGEN description: Random Number Generator clock enable during sleep mode bit_offset: 26 bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - name: FMCEN description: Flexible memory controller clock enable bit_offset: 0 bit_size: 1 - name: QUADSPIEN description: QUADSPI memory interface clock enable bit_offset: 8 bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - name: FMCRST description: Flexible memory controller reset bit_offset: 0 bit_size: 1 - name: QSPIRST description: Quad SPI 1 module reset bit_offset: 8 bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - name: FMCSMEN description: Flexible memory controller clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: QSPISMEN description: QUADSPI memory interface clock enable during Sleep and Stop modes bit_offset: 8 bit_size: 1 fieldset/APB1ENR1: description: APB1ENR1 fields: - name: TIM2EN description: TIM2 timer clock enable bit_offset: 0 bit_size: 1 - name: TIM3EN description: TIM3 timer clock enable bit_offset: 1 bit_size: 1 - name: TIM4EN description: TIM4 timer clock enable bit_offset: 2 bit_size: 1 - name: TIM5EN description: TIM5 timer clock enable bit_offset: 3 bit_size: 1 - name: TIM6EN description: TIM6 timer clock enable bit_offset: 4 bit_size: 1 - name: TIM7EN description: TIM7 timer clock enable bit_offset: 5 bit_size: 1 - name: CRSEN description: CRSclock enable bit_offset: 8 bit_size: 1 - name: RTCAPBEN description: RTC APB clock enable bit_offset: 10 bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN description: SPI2 clock enable bit_offset: 14 bit_size: 1 - name: SPI3EN description: SPI3 clock enable bit_offset: 15 bit_size: 1 - name: USART2EN description: USART2 clock enable bit_offset: 17 bit_size: 1 - name: USART3EN description: USART3 clock enable bit_offset: 18 bit_size: 1 - name: UART4EN description: UART4 clock enable bit_offset: 19 bit_size: 1 - name: UART5EN description: UART5 clock enable bit_offset: 20 bit_size: 1 - name: I2C1EN description: I2C1 clock enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: I2C2 clock enable bit_offset: 22 bit_size: 1 - name: USBEN description: USB device clock enable bit_offset: 23 bit_size: 1 - name: FDCANEN description: FDCAN clock enable bit_offset: 25 bit_size: 1 - name: PWREN description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: I2C3EN description: I2C3 clock enable bit_offset: 30 bit_size: 1 - name: LPTIM1EN description: Low power timer 1 clock enable bit_offset: 31 bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - name: LPUART1EN description: Low power UART 1 clock enable bit_offset: 0 bit_size: 1 - name: I2C4EN description: I2C4 clock enable bit_offset: 1 bit_size: 1 - name: UCPD1EN description: UCPD1 clock enable bit_offset: 8 bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - name: TIM2RST description: TIM2 timer reset bit_offset: 0 bit_size: 1 - name: TIM3RST description: TIM3 timer reset bit_offset: 1 bit_size: 1 - name: TIM4RST description: TIM3 timer reset bit_offset: 2 bit_size: 1 - name: TIM5RST description: TIM5 timer reset bit_offset: 3 bit_size: 1 - name: TIM6RST description: TIM6 timer reset bit_offset: 4 bit_size: 1 - name: TIM7RST description: TIM7 timer reset bit_offset: 5 bit_size: 1 - name: CRSRST description: Clock recovery system reset bit_offset: 8 bit_size: 1 - name: SPI2RST description: SPI2 reset bit_offset: 14 bit_size: 1 - name: SPI3RST description: SPI3 reset bit_offset: 15 bit_size: 1 - name: USART2RST description: USART2 reset bit_offset: 17 bit_size: 1 - name: USART3RST description: USART3 reset bit_offset: 18 bit_size: 1 - name: UART4RST description: UART4 reset bit_offset: 19 bit_size: 1 - name: UART5RST description: UART5 reset bit_offset: 20 bit_size: 1 - name: I2C1RST description: I2C1 reset bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C2 reset bit_offset: 22 bit_size: 1 - name: USBRST description: USBD reset bit_offset: 23 bit_size: 1 - name: FDCANRST description: FDCAN reset bit_offset: 25 bit_size: 1 - name: PWRRST description: Power interface reset bit_offset: 28 bit_size: 1 - name: I2C3RST description: I2C3 interface reset bit_offset: 30 bit_size: 1 - name: LPTIM1RST description: Low Power Timer 1 reset bit_offset: 31 bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - name: LPUART1RST description: Low-power UART 1 reset bit_offset: 0 bit_size: 1 - name: I2C4RST description: I2C4 reset bit_offset: 1 bit_size: 1 - name: UCPD1RST description: UCPD1 reset bit_offset: 8 bit_size: 1 fieldset/APB1SMENR1: description: APB1SMENR1 fields: - name: TIM2SMEN description: TIM2 timer clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: TIM3SMEN description: TIM3 timer clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: TIM4SMEN description: TIM4 timer clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 - name: TIM5SMEN description: TIM5 timer clocks enable during Sleep and Stop modes bit_offset: 3 bit_size: 1 - name: TIM6SMEN description: TIM6 timer clocks enable during Sleep and Stop modes bit_offset: 4 bit_size: 1 - name: TIM7SMEN description: TIM7 timer clocks enable during Sleep and Stop modes bit_offset: 5 bit_size: 1 - name: CRSSMEN description: CRS clock enable during sleep mode bit_offset: 8 bit_size: 1 - name: RTCAPBSMEN description: RTC APB clock enable during Sleep and Stop modes bit_offset: 10 bit_size: 1 - name: WWDGSMEN description: Window watchdog clocks enable during Sleep and Stop modes bit_offset: 11 bit_size: 1 - name: SPI2SMEN description: SPI2 clocks enable during Sleep and Stop modes bit_offset: 14 bit_size: 1 - name: SP3SMEN description: SPI3 clocks enable during Sleep and Stop modes bit_offset: 15 bit_size: 1 - name: USART2SMEN description: USART2 clocks enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: USART3SMEN description: USART3 clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: UART4SMEN description: UART4 clocks enable during Sleep and Stop modes bit_offset: 19 bit_size: 1 - name: UART5SMEN description: UART5 clocks enable during Sleep and Stop modes bit_offset: 20 bit_size: 1 - name: I2C1SMEN description: I2C1 clocks enable during Sleep and Stop modes bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clocks enable during Sleep and Stop modes bit_offset: 22 bit_size: 1 - name: USBSMEN description: USB device clocks enable during Sleep and Stop modes bit_offset: 23 bit_size: 1 - name: FDCANSMEN description: FDCAN clock enable during sleep mode bit_offset: 25 bit_size: 1 - name: PWRSMEN description: Power interface clocks enable during Sleep and Stop modes bit_offset: 28 bit_size: 1 - name: I2C3SMEN description: I2C3 clocks enable during Sleep and Stop modes bit_offset: 30 bit_size: 1 - name: LPTIM1SMEN description: Low Power Timer1 clock enable during sleep mode bit_offset: 31 bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep and Stop modes register 2 fields: - name: LPUART1SMEN description: Low power UART 1 clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: I2C4SMEN description: I2C4 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - name: UCPD1SMEN description: UCPD1 clocks enable during Sleep and Stop modes bit_offset: 8 bit_size: 1 fieldset/APB2ENR: description: APB2ENR fields: - name: SYSCFGEN description: SYSCFG clock enable bit_offset: 0 bit_size: 1 - name: TIM1EN description: TIM1 timer clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: SPI1 clock enable bit_offset: 12 bit_size: 1 - name: TIM8EN description: TIM8 timer clock enable bit_offset: 13 bit_size: 1 - name: USART1EN description: USART1clock enable bit_offset: 14 bit_size: 1 - name: SPI4EN description: SPI 4 clock enable bit_offset: 15 bit_size: 1 - name: TIM15EN description: TIM15 timer clock enable bit_offset: 16 bit_size: 1 - name: TIM16EN description: TIM16 timer clock enable bit_offset: 17 bit_size: 1 - name: TIM17EN description: TIM17 timer clock enable bit_offset: 18 bit_size: 1 - name: TIM20EN description: Timer 20 clock enable bit_offset: 20 bit_size: 1 - name: SAI1EN description: SAI1 clock enable bit_offset: 21 bit_size: 1 - name: HRTIM1EN description: HRTIMER clock enable bit_offset: 26 bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: SYSCFGRST description: System configuration (SYSCFG) reset bit_offset: 0 bit_size: 1 - name: TIM1RST description: TIM1 timer reset bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI1 reset bit_offset: 12 bit_size: 1 - name: TIM8RST description: TIM8 timer reset bit_offset: 13 bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - name: SPI4RST description: SPI 4 reset bit_offset: 15 bit_size: 1 - name: TIM15RST description: TIM15 timer reset bit_offset: 16 bit_size: 1 - name: TIM16RST description: TIM16 timer reset bit_offset: 17 bit_size: 1 - name: TIM17RST description: TIM17 timer reset bit_offset: 18 bit_size: 1 - name: TIM20RST description: Timer 20 reset bit_offset: 20 bit_size: 1 - name: SAI1RST description: Serial audio interface 1 (SAI1) reset bit_offset: 21 bit_size: 1 - name: HRTIM1RST description: HRTIMER reset bit_offset: 26 bit_size: 1 fieldset/APB2SMENR: description: APB2SMENR fields: - name: SYSCFGSMEN description: SYSCFG clocks enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 - name: TIM1SMEN description: TIM1 timer clocks enable during Sleep and Stop modes bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clocks enable during Sleep and Stop modes bit_offset: 12 bit_size: 1 - name: TIM8SMEN description: TIM8 timer clocks enable during Sleep and Stop modes bit_offset: 13 bit_size: 1 - name: USART1SMEN description: USART1clocks enable during Sleep and Stop modes bit_offset: 14 bit_size: 1 - name: SPI4SMEN description: SPI4 timer clocks enable during Sleep and Stop modes bit_offset: 15 bit_size: 1 - name: TIM15SMEN description: TIM15 timer clocks enable during Sleep and Stop modes bit_offset: 16 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clocks enable during Sleep and Stop modes bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: TIM17 timer clocks enable during Sleep and Stop modes bit_offset: 18 bit_size: 1 - name: TIM20SMEN description: Timer 20clock enable during sleep mode bit_offset: 20 bit_size: 1 - name: SAI1SMEN description: SAI1 clock enable during sleep mode bit_offset: 21 bit_size: 1 - name: HRTIM1SMEN description: HRTIMER clock enable during sleep mode bit_offset: 26 bit_size: 1 fieldset/BDCR: description: BDCR fields: - name: LSEON description: LSE oscillator enable bit_offset: 0 bit_size: 1 - name: LSERDY description: LSE oscillator ready bit_offset: 1 bit_size: 1 - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - name: LSEDRV description: SE oscillator drive capability bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: LSECSSON bit_offset: 5 bit_size: 1 - name: LSECSSD description: LSECSSD bit_offset: 6 bit_size: 1 - name: RTCSEL description: RTC clock source selection bit_offset: 8 bit_size: 2 enum: RTCSEL - name: RTCEN description: RTC clock enable bit_offset: 15 bit_size: 1 - name: BDRST description: RTC domain software reset bit_offset: 16 bit_size: 1 - name: LSCOEN description: Low speed clock output enable bit_offset: 24 bit_size: 1 - name: LSCOSEL description: Low speed clock output selection bit_offset: 25 bit_size: 1 fieldset/CCIPR: description: CCIPR fields: - name: USART1SEL description: USART1 clock source selection bit_offset: 0 bit_size: 2 - name: USART2SEL description: USART2 clock source selection bit_offset: 2 bit_size: 2 - name: USART3SEL description: USART3 clock source selection bit_offset: 4 bit_size: 2 - name: UART4SEL description: UART4 clock source selection bit_offset: 6 bit_size: 2 - name: UART5SEL description: UART5 clock source selection bit_offset: 8 bit_size: 2 - name: LPUART1SEL description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 - name: I2C1SEL description: I2C1 clock source selection bit_offset: 12 bit_size: 2 - name: I2C2SEL description: I2C2 clock source selection bit_offset: 14 bit_size: 2 - name: I2C3SEL description: I2C3 clock source selection bit_offset: 16 bit_size: 2 - name: LPTIM1SEL description: Low power timer 1 clock source selection bit_offset: 18 bit_size: 2 - name: SAI1SEL description: SAI1 clock source selection bit_offset: 20 bit_size: 2 - name: I2S23SEL description: I2S23 clock source selection bit_offset: 22 bit_size: 2 - name: FDCANSEL description: FDCAN clock source selection bit_offset: 24 bit_size: 2 enum: FDCANSEL - name: CLK48SEL description: 48 MHz clock source selection bit_offset: 26 bit_size: 2 enum: CLK48SEL - name: ADC12SEL description: ADCs clock source selection bit_offset: 28 bit_size: 2 enum: ADCSEL - name: ADC345SEL description: ADC3/4/5 clock source selection bit_offset: 30 bit_size: 2 enum: ADCSEL fieldset/CCIPR2: description: Peripherals independent clock configuration register fields: - name: I2C4SEL description: I2C4 clock source selection bit_offset: 0 bit_size: 2 - name: QSPISEL description: Octospi clock source selection bit_offset: 20 bit_size: 2 fieldset/CFGR: description: Clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 enum: SW - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 description: PB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE2 description: APB high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 enum: PPRE - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 0 bit_size: 1 - name: LSERDYC description: LSE ready interrupt clear bit_offset: 1 bit_size: 1 - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 3 bit_size: 1 - name: HSERDYC description: HSE ready interrupt clear bit_offset: 4 bit_size: 1 - name: PLLRDYC description: PLL ready interrupt clear bit_offset: 5 bit_size: 1 - name: CSSC description: Clock security system interrupt clear bit_offset: 8 bit_size: 1 - name: LSECSSC description: LSE Clock security system interrupt clear bit_offset: 9 bit_size: 1 - name: HSI48RDYC description: HSI48 oscillator ready interrupt clear bit_offset: 10 bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 0 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 1 bit_size: 1 - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 3 bit_size: 1 - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 4 bit_size: 1 - name: PLLRDYIE description: PLL ready interrupt enable bit_offset: 5 bit_size: 1 - name: LSECSSIE description: LSE clock security system interrupt enable bit_offset: 9 bit_size: 1 - name: HSI48RDYIE description: HSI48 ready interrupt enable bit_offset: 10 bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 3 bit_size: 1 - name: HSERDYF description: HSE ready interrupt flag bit_offset: 4 bit_size: 1 - name: PLLRDYF description: PLL ready interrupt flag bit_offset: 5 bit_size: 1 - name: CSSF description: Clock security system interrupt flag bit_offset: 8 bit_size: 1 - name: LSECSSF description: LSE Clock security system interrupt flag bit_offset: 9 bit_size: 1 - name: HSI48RDYF description: HSI48 ready interrupt flag bit_offset: 10 bit_size: 1 fieldset/CR: description: Clock control register fields: - name: HSION description: HSI clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON description: HSI always enable for peripheral kernels bit_offset: 9 bit_size: 1 - name: HSIRDY description: HSI clock ready flag bit_offset: 10 bit_size: 1 - name: HSEON description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 - name: HSEBYP description: HSE crystal oscillator bypass bit_offset: 18 bit_size: 1 - name: CSSON description: Clock security system enable bit_offset: 19 bit_size: 1 - name: PLLON description: Main PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: Main PLL clock ready flag bit_offset: 25 bit_size: 1 fieldset/CRRCR: description: Clock recovery RC register fields: - name: HSI48ON description: HSI48 clock enable bit_offset: 0 bit_size: 1 - name: HSI48RDY description: HSI48 clock ready flag bit_offset: 1 bit_size: 1 - name: HSI48CAL description: HSI48 clock calibration bit_offset: 7 bit_size: 9 fieldset/CSR: description: CSR fields: - name: LSION description: LSI oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: LSI oscillator ready bit_offset: 1 bit_size: 1 - name: RMVF description: Remove reset flag bit_offset: 23 bit_size: 1 - name: OBLRSTF description: Option byte loader reset flag bit_offset: 25 bit_size: 1 - name: PINRSTF description: Pad reset flag bit_offset: 26 bit_size: 1 - name: BORRSTF description: BOR flag bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: Independent window watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: HSICAL0 description: Internal High Speed clock Calibration bit_offset: 16 bit_size: 8 - name: HSITRIM description: Internal High Speed clock trimming bit_offset: 24 bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - name: PLLSRC description: Main PLL, PLLSAI1 and PLLSAI2 entry clock source bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLM description: Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock bit_offset: 4 bit_size: 4 enum: PLLM - name: PLLN description: Main PLL multiplication factor for VCO bit_offset: 8 bit_size: 7 enum: PLLN - name: PLLPEN description: Main PLL PLLSAI3CLK output enable bit_offset: 16 bit_size: 1 - name: PLLPBIT description: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) bit_offset: 17 bit_size: 1 enum: PLLPBIT - name: PLLQEN description: Main PLL PLLUSB1CLK output enable bit_offset: 20 bit_size: 1 - name: PLLQ description: Main PLL division factor for PLLUSB1CLK(48 MHz clock) bit_offset: 21 bit_size: 2 enum: PLLQ - name: PLLREN description: Main PLL PLLCLK output enable bit_offset: 24 bit_size: 1 - name: PLLR description: Main PLL division factor for PLLCLK (system clock) bit_offset: 25 bit_size: 2 enum: PLLR - name: PLLP description: Main PLL division factor for PLLSAI2CLK bit_offset: 27 bit_size: 5 enum: PLLP enum/ADCSEL: bit_size: 2 variants: - name: DISABLE description: No clock selected value: 0 - name: PLL1_P description: PLL 'P' clock selected as ADC clock value: 1 - name: SYS description: System clock selected as ADC clock value: 2 enum/FDCANSEL: bit_size: 2 variants: - name: HSE description: HSE used as FDCAN clock source value: 0 - name: PLL1_Q description: PLLQCLK used as FDCAN clock source value: 1 - name: PCLK1 description: PCLK used as FDCAN clock source value: 2 enum/CLK48SEL: bit_size: 2 variants: - name: HSI48 description: HSI48 oscillator clock selected as 48 MHz clock value: 0 - name: PLL1_Q description: PLLQCLK selected as 48 MHz clock value: 2 enum/HPRE: bit_size: 4 variants: - name: Div1 description: SYSCLK not divided value: 0 - name: Div2 description: SYSCLK is divided by 2 value: 8 - name: Div4 description: SYSCLK is divided by 4 value: 9 - name: Div8 description: SYSCLK is divided by 8 value: 10 - name: Div16 description: SYSCLK is divided by 16 value: 11 - name: Div64 description: SYSCLK is divided by 64 value: 12 - name: Div128 description: SYSCLK is divided by 128 value: 13 - name: Div256 description: SYSCLK is divided by 256 value: 14 - name: Div512 description: SYSCLK is divided by 512 value: 15 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: MCO1 not divided value: 0 - name: Div2 description: MCO clock is divided by 2 value: 1 - name: Div4 description: MCO clock is divided by 4 value: 2 - name: Div8 description: MCO clock is divided by 8 value: 3 - name: Div16 description: MCO clock is divided divided by 16 value: 4 enum/MCOSEL: bit_size: 4 variants: - name: DISABLE description: No clock, MCO output disabled value: 0 - name: SYS description: SYSCLK selected as MCO source value: 1 - name: HSI description: HSI selected as MCO source value: 3 - name: HSE description: HSE selected as MCO source value: 4 - name: PLLCLK description: Main PLLCLK selected as MCO source value: 5 - name: LSI description: LSI selected as MCO source value: 6 - name: LSE description: LSE selected as MCO source value: 7 - name: HSI48 description: HSI48 selected as MCO source value: 8 enum/PLLM: bit_size: 4 variants: - name: Div1 value: 0 - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 - name: Div9 value: 8 - name: Div10 value: 9 - name: Div11 value: 10 - name: Div12 value: 11 - name: Div13 value: 12 - name: Div14 value: 13 - name: Div15 value: 14 - name: Div16 value: 15 enum/PLLN: bit_size: 7 variants: - name: Mul8 value: 8 - name: Mul9 value: 9 - name: Mul10 value: 10 - name: Mul11 value: 11 - name: Mul12 value: 12 - name: Mul13 value: 13 - name: Mul14 value: 14 - name: Mul15 value: 15 - name: Mul16 value: 16 - name: Mul17 value: 17 - name: Mul18 value: 18 - name: Mul19 value: 19 - name: Mul20 value: 20 - name: Mul21 value: 21 - name: Mul22 value: 22 - name: Mul23 value: 23 - name: Mul24 value: 24 - name: Mul25 value: 25 - name: Mul26 value: 26 - name: Mul27 value: 27 - name: Mul28 value: 28 - name: Mul29 value: 29 - name: Mul30 value: 30 - name: Mul31 value: 31 - name: Mul32 value: 32 - name: Mul33 value: 33 - name: Mul34 value: 34 - name: Mul35 value: 35 - name: Mul36 value: 36 - name: Mul37 value: 37 - name: Mul38 value: 38 - name: Mul39 value: 39 - name: Mul40 value: 40 - name: Mul41 value: 41 - name: Mul42 value: 42 - name: Mul43 value: 43 - name: Mul44 value: 44 - name: Mul45 value: 45 - name: Mul46 value: 46 - name: Mul47 value: 47 - name: Mul48 value: 48 - name: Mul49 value: 49 - name: Mul50 value: 50 - name: Mul51 value: 51 - name: Mul52 value: 52 - name: Mul53 value: 53 - name: Mul54 value: 54 - name: Mul55 value: 55 - name: Mul56 value: 56 - name: Mul57 value: 57 - name: Mul58 value: 58 - name: Mul59 value: 59 - name: Mul60 value: 60 - name: Mul61 value: 61 - name: Mul62 value: 62 - name: Mul63 value: 63 - name: Mul64 value: 64 - name: Mul65 value: 65 - name: Mul66 value: 66 - name: Mul67 value: 67 - name: Mul68 value: 68 - name: Mul69 value: 69 - name: Mul70 value: 70 - name: Mul71 value: 71 - name: Mul72 value: 72 - name: Mul73 value: 73 - name: Mul74 value: 74 - name: Mul75 value: 75 - name: Mul76 value: 76 - name: Mul77 value: 77 - name: Mul78 value: 78 - name: Mul79 value: 79 - name: Mul80 value: 80 - name: Mul81 value: 81 - name: Mul82 value: 82 - name: Mul83 value: 83 - name: Mul84 value: 84 - name: Mul85 value: 85 - name: Mul86 value: 86 - name: Mul87 value: 87 - name: Mul88 value: 88 - name: Mul89 value: 89 - name: Mul90 value: 90 - name: Mul91 value: 91 - name: Mul92 value: 92 - name: Mul93 value: 93 - name: Mul94 value: 94 - name: Mul95 value: 95 - name: Mul96 value: 96 - name: Mul97 value: 97 - name: Mul98 value: 98 - name: Mul99 value: 99 - name: Mul100 value: 100 - name: Mul101 value: 101 - name: Mul102 value: 102 - name: Mul103 value: 103 - name: Mul104 value: 104 - name: Mul105 value: 105 - name: Mul106 value: 106 - name: Mul107 value: 107 - name: Mul108 value: 108 - name: Mul109 value: 109 - name: Mul110 value: 110 - name: Mul111 value: 111 - name: Mul112 value: 112 - name: Mul113 value: 113 - name: Mul114 value: 114 - name: Mul115 value: 115 - name: Mul116 value: 116 - name: Mul117 value: 117 - name: Mul118 value: 118 - name: Mul119 value: 119 - name: Mul120 value: 120 - name: Mul121 value: 121 - name: Mul122 value: 122 - name: Mul123 value: 123 - name: Mul124 value: 124 - name: Mul125 value: 125 - name: Mul126 value: 126 - name: Mul127 value: 127 enum/PLLP: bit_size: 7 variants: - name: Div2 value: 2 - name: Div3 value: 3 - name: Div4 value: 4 - name: Div5 value: 5 - name: Div6 value: 6 - name: Div7 value: 7 - name: Div8 value: 8 - name: Div9 value: 9 - name: Div10 value: 10 - name: Div11 value: 11 - name: Div12 value: 12 - name: Div13 value: 13 - name: Div14 value: 14 - name: Div15 value: 15 - name: Div16 value: 16 - name: Div17 value: 17 - name: Div18 value: 18 - name: Div19 value: 19 - name: Div20 value: 20 - name: Div21 value: 21 - name: Div22 value: 22 - name: Div23 value: 23 - name: Div24 value: 24 - name: Div25 value: 25 - name: Div26 value: 26 - name: Div27 value: 27 - name: Div28 value: 28 - name: Div29 value: 29 - name: Div30 value: 30 - name: Div31 value: 31 enum/PLLPBIT: bit_size: 1 variants: - name: Div7 value: 0 - name: Div17 value: 1 enum/PLLQ: bit_size: 2 variants: - name: Div2 value: 0 - name: Div4 value: 1 - name: Div6 value: 2 - name: Div8 value: 3 enum/PLLR: bit_size: 2 variants: - name: Div2 value: 0 - name: Div4 value: 1 - name: Div6 value: 2 - name: Div8 value: 3 enum/PLLSRC: bit_size: 2 variants: - name: DISABLE description: No clock selected as PLL entry clock source value: 0 - name: HSI description: HSI selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source value: 3 enum/PPRE: bit_size: 4 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK is divided by 2 value: 4 - name: Div4 description: HCLK is divided by 4 value: 5 - name: Div8 description: HCLK is divided by 8 value: 6 - name: Div16 description: HCLK is divided by 16 value: 7 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE description: No clock used as RTC clock value: 0 - name: LSE description: LSE used as RTC clock value: 1 - name: LSI description: LSI used as RTC clock value: 2 - name: HSE_Div32 description: HSE divided by 32 used as RTC clock value: 3 enum/SW: bit_size: 2 variants: - name: HSI description: HSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock value: 2 - name: PLL1_R description: PLLRCLK selected as system clock value: 3