block/RCC: description: Reset and clock controller items: - name: CR description: RCC clock control register byte_offset: 0 fieldset: CR - name: HSICFGR description: RCC HSI calibration register byte_offset: 16 fieldset: HSICFGR - name: CRRCR description: RCC clock recovery RC register byte_offset: 20 fieldset: CRRCR - name: CSICFGR description: RCC CSI calibration register byte_offset: 24 fieldset: CSICFGR - name: CFGR description: RCC clock configuration register byte_offset: 28 fieldset: CFGR - name: CFGR2 description: RCC CPU domain clock configuration register 2 byte_offset: 32 fieldset: CFGR2 - name: PLLCFGR description: RCC PLL clock source selection register array: len: 3 stride: 4 byte_offset: 40 fieldset: PLLCFGR - name: PLLDIVR description: RCC PLL1 dividers register array: len: 3 stride: 8 byte_offset: 52 fieldset: PLLDIVR - name: PLLFRACR description: RCC PLL1 fractional divider register array: len: 3 stride: 8 byte_offset: 56 fieldset: PLLFRACR - name: CIER description: RCC clock source interrupt enable register byte_offset: 80 fieldset: CIER - name: CIFR description: RCC clock source interrupt flag register byte_offset: 84 fieldset: CIFR - name: CICR description: RCC clock source interrupt clear register byte_offset: 88 fieldset: CICR - name: AHB1RSTR description: RCC AHB1 reset register byte_offset: 96 fieldset: AHB1RSTR - name: AHB2RSTR description: RCC AHB2 peripheral reset register byte_offset: 100 fieldset: AHB2RSTR - name: AHB4RSTR description: RCC AHB4 peripheral reset register byte_offset: 108 fieldset: AHB4RSTR - name: APB1LRSTR description: RCC APB1 peripheral low reset register byte_offset: 116 fieldset: APB1LRSTR - name: APB1HRSTR description: RCC APB1 peripheral high reset register byte_offset: 120 fieldset: APB1HRSTR - name: APB2RSTR description: RCC APB2 peripheral reset register byte_offset: 124 fieldset: APB2RSTR - name: APB3RSTR description: RCC APB3 peripheral reset register byte_offset: 128 fieldset: APB3RSTR - name: AHB1ENR description: RCC AHB1 peripherals clock register byte_offset: 136 fieldset: AHB1ENR - name: AHB2ENR description: RCC AHB2 peripheral clock register byte_offset: 140 fieldset: AHB2ENR - name: AHB4ENR description: RCC AHB4 peripheral clock register byte_offset: 148 fieldset: AHB4ENR - name: APB1LENR description: RCC APB1 peripheral clock register byte_offset: 156 fieldset: APB1LENR - name: APB1HENR description: RCC APB1 peripheral clock register byte_offset: 160 fieldset: APB1HENR - name: APB2ENR description: RCC APB2 peripheral clock register byte_offset: 164 fieldset: APB2ENR - name: APB3ENR description: RCC APB3 peripheral clock register byte_offset: 168 fieldset: APB3ENR - name: AHB1LPENR description: RCC AHB1 sleep clock register byte_offset: 176 fieldset: AHB1LPENR - name: AHB2LPENR description: RCC AHB2 sleep clock register byte_offset: 180 fieldset: AHB2LPENR - name: AHB4LPENR description: RCC AHB4 sleep clock register byte_offset: 188 fieldset: AHB4LPENR - name: APB1LLPENR description: RCC APB1 sleep clock register byte_offset: 196 fieldset: APB1LLPENR - name: APB1HLPENR description: RCC APB1 sleep clock register byte_offset: 200 fieldset: APB1HLPENR - name: APB2LPENR description: RCC APB2 sleep clock register byte_offset: 204 fieldset: APB2LPENR - name: APB3LPENR description: RCC APB3 sleep clock register byte_offset: 208 fieldset: APB3LPENR - name: CCIPR1 description: RCC kernel clock configuration register byte_offset: 216 fieldset: CCIPR1 - name: CCIPR2 description: RCC kernel clock configuration register byte_offset: 220 fieldset: CCIPR2 - name: CCIPR3 description: RCC kernel clock configuration register byte_offset: 224 fieldset: CCIPR3 - name: CCIPR4 description: RCC kernel clock configuration register byte_offset: 228 fieldset: CCIPR4 - name: CCIPR5 description: RCC kernel clock configuration register byte_offset: 232 fieldset: CCIPR5 - name: BDCR description: RCC Backup domain control register byte_offset: 240 fieldset: BDCR - name: RSR description: RCC reset status register byte_offset: 244 fieldset: RSR - name: SECCFGR description: RCC secure configuration register byte_offset: 272 fieldset: SECCFGR - name: PRIVCFGR description: RCC privilege configuration register byte_offset: 276 fieldset: PRIVCFGR fieldset/AHB1ENR: description: RCC AHB1 peripherals clock register fields: - name: GPDMA1EN description: "GPDMA1 clock enable\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPDMA2EN description: "GPDMA2 clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: FLITFEN description: "Flash interface clock enable\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: CRCEN description: "CRC clock enable\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: CORDICEN description: "CORDIC clock enable\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: FMACEN description: "FMAC clock enable\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: RAMCFGEN description: "RAMCFG clock enable\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: ETHEN description: "ETH clock enable\r Set and reset by software" bit_offset: 19 bit_size: 1 - name: ETHTXEN description: "ETHTX clock enable\r Set and reset by software" bit_offset: 20 bit_size: 1 - name: ETHRXEN description: "ETHRX clock enable\r Set and reset by software" bit_offset: 21 bit_size: 1 - name: TZSC1EN description: "TZSC1 clock enable\r Set and reset by software" bit_offset: 24 bit_size: 1 - name: BKPRAMEN description: "BKPRAM clock enable\r Set and reset by software" bit_offset: 28 bit_size: 1 - name: DCACHEEN description: "DCACHE clock enable\r Set and reset by software" bit_offset: 30 bit_size: 1 - name: SRAM1EN description: "SRAM1 clock enable\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/AHB1LPENR: description: RCC AHB1 sleep clock register fields: - name: GPDMA1LPEN description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPDMA2LPEN description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: FLITFLPEN description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: CRCLPEN description: "CRC clock enable during sleep mode\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: CORDICLPEN description: "CORDIC clock enable during sleep mode\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: FMACLPEN description: "FMAC clock enable during sleep mode\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: RAMCFGLPEN description: "RAMCFG clock enable during sleep mode\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: ETHLPEN description: "ETH clock enable during Sleep mode\r Set and reset by software" bit_offset: 19 bit_size: 1 - name: ETHTXLPEN description: "ETHTX clock enable during sleep mode\r Set and reset by software" bit_offset: 20 bit_size: 1 - name: ETHRXLPEN description: "ETHRX clock enable during sleep mode\r Set and reset by software" bit_offset: 21 bit_size: 1 - name: TZSC1LPEN description: "TZSC1 clock enable during sleep mode\r Set and reset by software" bit_offset: 24 bit_size: 1 - name: BKPRAMLPEN description: "BKPRAM clock enable during sleep mode\r Set and reset by software" bit_offset: 28 bit_size: 1 - name: ICACHELPEN description: "ICACHE clock enable during sleep mode\r Set and reset by software" bit_offset: 29 bit_size: 1 - name: DCACHELPEN description: "DCACHE clock enable during sleep mode\r Set and reset by software" bit_offset: 30 bit_size: 1 - name: SRAM1LPEN description: "SRAM1 clock enable during sleep mode\r Set and reset by software" bit_offset: 31 bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 reset register fields: - name: GPDMA1RST description: "GPDMA1 block reset\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPDMA2RST description: "GPDMA2 block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: CRCRST description: CRC block reset Set and reset by software. bit_offset: 12 bit_size: 1 - name: CORDICRST description: "CORDIC block reset\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: FMACRST description: "FMAC block reset\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: RAMCFGRST description: "RAMCFG block reset\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: ETHRST description: "ETH1 block reset\r Set and reset by software" bit_offset: 19 bit_size: 1 - name: TZSC1RST description: "TZSC1 reset\r Set and reset by software" bit_offset: 24 bit_size: 1 fieldset/AHB2ENR: description: RCC AHB2 peripheral clock register fields: - name: GPIOAEN description: "GPIOA clock enable\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPIOBEN description: "GPIOB clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: GPIOCEN description: "GPIOC clock enable\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: GPIODEN description: "GPIOD clock enable\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: GPIOEEN description: "GPIOE clock enable\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: GPIOFEN description: "GPIOF clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: GPIOGEN description: "GPIOG clock enable\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: GPIOHEN description: "GPIOH clock enable\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: GPIOIEN description: "GPIOI clock enable\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: ADC12EN description: "ADC1 and 2 peripherals clock enabled\r Set and reset by software." bit_offset: 10 bit_size: 1 - name: DAC1EN description: "DAC clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: DCMI_PSSIEN description: "digital camera interface clock enable (DCMI or PSSI depending which interface is active)\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: AESEN description: "AES clock enable\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: HASHEN description: "HASH clock enable\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: RNGEN description: "RNG clock enable\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: PKAEN description: "PKA clock enable\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: SAESEN description: "SAES clock enable\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: SRAM3EN description: "SRAM3 clock enable\r Set and reset by software." bit_offset: 30 bit_size: 1 - name: SRAM2EN description: "SRAM2 clock enable\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/AHB2LPENR: description: RCC AHB2 sleep clock register fields: - name: GPIOALPEN description: "GPIOA clock enable during sleep mode\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPIOBLPEN description: "GPIOB clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: GPIOCLPEN description: "GPIOC clock enable during sleep mode\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: GPIODLPEN description: "GPIOD clock enable during sleep mode\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: GPIOELPEN description: "GPIOE clock enable during sleep mode\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: GPIOFLPEN description: "GPIOF clock enable during sleep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: GPIOGLPEN description: "GPIOG clock enable during sleep mode\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: GPIOHLPEN description: "GPIOH clock enable during sleep mode\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: GPIOILPEN description: "GPIOI clock enable during sleep mode\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: ADC12LPEN description: "ADC1 and 2 peripherals clock enable during sleep mode\r Set and reset by software." bit_offset: 10 bit_size: 1 - name: DAC1LPEN description: "DAC clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: DCMI_PSSILPEN description: "digital camera interface clock enable during sleep mode (DCMI or PSSI depending which interface is active)\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: AESLPEN description: "AES clock enable during sleep mode\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: HASHLPEN description: "HASH clock enable during sleep mode\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: RNGLPEN description: "RNG clock enable during sleep mode\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: PKALPEN description: "PKA clock enable during sleep mode\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: SAESLPEN description: "SAES clock enable during sleep mode\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: SRAM2LPEN description: "SRAM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 30 bit_size: 1 - name: SRAM3LPEN description: "SRAM3 clock enable during sleep mode\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/AHB2RSTR: description: RCC AHB2 peripheral reset register fields: - name: GPIOARST description: "GPIOA block reset\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPIOBRST description: "GPIOB block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: GPIOCRST description: "GPIOC block reset\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: GPIODRST description: "GPIOD block reset\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: GPIOERST description: "GPIOE block reset\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: GPIOFRST description: "GPIOF block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: GPIOGRST description: "GPIOG block reset\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: GPIOHRST description: "GPIOH block reset\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: GPIOIRST description: "GPIOI block reset\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: ADC12RST description: "ADC1 and 2 blocks reset\r Set and reset by software." bit_offset: 10 bit_size: 1 - name: DAC1RST description: "DAC block reset\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: DCMI_PSSIRST description: "digital camera interface block reset (DCMI or PSSI depending which interface is active)\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: AESRST description: "AES block reset\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: HASHRST description: "HASH block reset\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: RNGRST description: "RNG block reset\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: PKARST description: "PKA block reset\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: SAESRST description: "SAES block reset\r Set and reset by software." bit_offset: 20 bit_size: 1 fieldset/AHB4ENR: description: RCC AHB4 peripheral clock register fields: - name: OTFDEC1EN description: "OTFDEC1 clock enable\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: SDMMC1EN description: SDMMC1 and SDMMC1 delay peripheral clock enable reset bit_offset: 11 bit_size: 1 - name: SDMMC2EN description: "SDMMC2 and SDMMC2 delay peripheral clock enabled\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: FMCEN description: "FMC clock enable\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: OCTOSPI1EN description: "OCTOSPI1 clock enable\r Set and reset by software." bit_offset: 20 bit_size: 1 fieldset/AHB4LPENR: description: RCC AHB4 sleep clock register fields: - name: OTFDEC1LPEN description: "OTFDEC1 clock enable during sleep mode\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: SDMMC1LPEN description: "SDMMC1 and SDMMC1 delay peripheral clock enable during sleep mode\r Set and reset by software" bit_offset: 11 bit_size: 1 - name: SDMMC2LPEN description: "SDMMC2 and SDMMC2 delay peripheral clock enable during sleep mode\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: FMCLPEN description: "FMC clock enable during sleep mode\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: OCTOSPI1LPEN description: "OCTOSPI1 clock enable during sleep mode\r Set and reset by software." bit_offset: 20 bit_size: 1 fieldset/AHB4RSTR: description: RCC AHB4 peripheral reset register fields: - name: OTFDEC1RST description: "OTFDEC1 block reset\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: SDMMC1RST description: "SDMMC1 and SDMMC1 delay blocks reset\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SDMMC2RST description: "SDMMC2 and SDMMC2 delay blocks reset\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: FMCRST description: "FMC block reset\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: OCTOSPI1RST description: "OCTOSPI1 block reset\r Set and reset by software." bit_offset: 20 bit_size: 1 fieldset/APB1HENR: description: RCC APB1 peripheral clock register fields: - name: UART9EN description: "UART9 clock enable\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: UART12EN description: "UART12 clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: DTSEN description: "DTS clock enable\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: LPTIM2EN description: "LPTIM2 clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: FDCAN12EN description: "FDCAN1 and FDCAN2 peripheral clock enable\r Set and reset by software." bit_offset: 9 bit_size: 1 - name: UCPDEN description: "UCPD clock enable\r Set and reset by software." bit_offset: 23 bit_size: 1 fieldset/APB1HLPENR: description: RCC APB1 sleep clock register fields: - name: UART9LPEN description: "UART9 clock enable during sleep mode\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: UART12LPEN description: "UART12 clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: DTSLPEN description: "DTS clock enable during sleep mode\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: LPTIM2LPEN description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: FDCAN12LPEN description: "FDCAN1 and FDCAN2 peripheral clock enable during sleep mode\r Set and reset by software." bit_offset: 9 bit_size: 1 - name: UCPDLPEN description: "UCPD clock enable during sleep mode\r Set and reset by software." bit_offset: 23 bit_size: 1 fieldset/APB1HRSTR: description: RCC APB1 peripheral high reset register fields: - name: UART9RST description: "UART9 block reset\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: UART12RST description: "UART12 block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: DTSRST description: "DTS block reset\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: LPTIM2RST description: "LPTIM2 block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: FDCAN12RST description: "FDCAN1 and FDCAN2 blocks reset\r Set and reset by software." bit_offset: 9 bit_size: 1 - name: UCPDRST description: "UCPD block reset\r Set and reset by software." bit_offset: 23 bit_size: 1 fieldset/APB1LENR: description: RCC APB1 peripheral clock register fields: - name: TIM2EN description: "TIM2 clock enable\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: TIM3EN description: "TIM3 clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: TIM4EN description: "TIM4 clock enable\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: TIM5EN description: "TIM5 clock enable\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: TIM6EN description: "TIM6 clock enable\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: TIM7EN description: "TIM7 clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: TIM12EN description: "TIM12 clock enable\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: TIM13EN description: "TIM13 clock enable\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: TIM14EN description: "TIM14 clock enable\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: WWDGEN description: "WWDG clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI2EN description: "SPI2 clock enable\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: SPI3EN description: "SPI3 clock enable\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: USART2EN description: "USART2 clock enable\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: USART3EN description: "USART3 clock enable\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: UART4EN description: "UART4 clock enable\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: UART5EN description: "UART5 clock enable\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: I2C1EN description: "I2C1 clock enable\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: I2C2EN description: "I2C2 clock enable\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: I3C1EN description: "I3C1 clock enable\r Set and reset by software." bit_offset: 23 bit_size: 1 - name: CRSEN description: "CRS clock enable\r Set and reset by software." bit_offset: 24 bit_size: 1 - name: USART6EN description: "USART6 clock enable\r Set and reset by software." bit_offset: 25 bit_size: 1 - name: USART10EN description: "USART10 clock enable\r Set and reset by software." bit_offset: 26 bit_size: 1 - name: USART11EN description: USART11 clock enable bit_offset: 27 bit_size: 1 - name: CECEN description: "HDMI-CEC clock enable\r Set and reset by software." bit_offset: 28 bit_size: 1 - name: UART7EN description: "UART7 clock enable\r Set and reset by software." bit_offset: 30 bit_size: 1 - name: UART8EN description: "UART8 clock enable\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/APB1LLPENR: description: RCC APB1 sleep clock register fields: - name: TIM2LPEN description: "TIM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: TIM3LPEN description: "TIM3 clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: TIM4LPEN description: "TIM4 clock enable during sleep mode\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: TIM5LPEN description: "TIM5 clock enable during sleep mode\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: TIM6LPEN description: "TIM6 clock enable during sleep mode\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: TIM7LPEN description: "TIM7 clock enable during sleep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: TIM12LPEN description: "TIM12 clock enable during sleep mode\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: TIM13LPEN description: "TIM13 clock enable during sleep mode\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: TIM14LPEN description: "TIM14 clock enable during sleep mode\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: WWDGLPEN description: "WWDG clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI2LPEN description: "SPI2 clock enable during sleep mode\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: SPI3LPEN description: "SPI3 clock enable during sleep mode\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: USART2LPEN description: "USART2 clock enable during sleep mode\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: USART3LPEN description: "USART3 clock enable during sleep mode\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: UART4LPEN description: "UART4 clock enable during sleep mode\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: UART5LPEN description: "UART5 clock enable during sleep mode\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: I2C1LPEN description: "I2C1 clock enable during sleep mode\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: I2C2LPEN description: "I2C2 clock enable during sleep mode\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: I3C1LPEN description: "I3C1 clock enable during sleep mode\r Set and reset by software." bit_offset: 23 bit_size: 1 - name: CRSLPEN description: "CRS clock enable during sleep mode\r Set and reset by software." bit_offset: 24 bit_size: 1 - name: USART6LPEN description: "USART6 clock enable during sleep mode\r Set and reset by software." bit_offset: 25 bit_size: 1 - name: USART10LPEN description: "USART10 clock enable during sleep mode\r Set and reset by software." bit_offset: 26 bit_size: 1 - name: USART11LPEN description: "USART11 clock enable during sleep mode\r Set and reset by software." bit_offset: 27 bit_size: 1 - name: CECLPEN description: "HDMI-CEC clock enable during sleep mode\r Set and reset by software." bit_offset: 28 bit_size: 1 - name: UART7LPEN description: "UART7 clock enable during sleep mode\r Set and reset by software." bit_offset: 30 bit_size: 1 - name: UART8LPEN description: "UART8 clock enable during sleep mode\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/APB1LRSTR: description: RCC APB1 peripheral low reset register fields: - name: TIM2RST description: "TIM2 block reset\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: TIM3RST description: "TIM3 block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: TIM4RST description: "TIM4 block reset\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: TIM5RST description: "TIM5 block reset\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: TIM6RST description: "TIM6 block reset\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: TIM7RST description: "TIM7 block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: TIM12RST description: "TIM12 block reset\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: TIM13RST description: "TIM13 block reset t\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: TIM14RST description: "TIM14 block reset\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: SPI2RST description: "SPI2 block reset\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: SPI3RST description: "SPI3 block reset\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: USART2RST description: "USART2 block reset\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: USART3RST description: "USART3 block reset\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: UART4RST description: "UART4 block reset\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: UART5RST description: "UART5 block reset\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: I2C1RST description: "I2C1 block reset\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: I2C2RST description: "I2C2 block reset\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: I3C1RST description: "I3C1 block reset\r Set and reset by software." bit_offset: 23 bit_size: 1 - name: CRSRST description: "CRS block reset\r Set and reset by software." bit_offset: 24 bit_size: 1 - name: USART6RST description: "USART6 block reset\r Set and reset by software." bit_offset: 25 bit_size: 1 - name: USART10RST description: "USART10 block reset\r Set and reset by software." bit_offset: 26 bit_size: 1 - name: USART11RST description: "USART11 block reset\r Set and reset by software." bit_offset: 27 bit_size: 1 - name: CECRST description: "HDMI-CEC block reset\r Set and reset by software." bit_offset: 28 bit_size: 1 - name: UART7RST description: "UART7 block reset\r Set and reset by software." bit_offset: 30 bit_size: 1 - name: UART8RST description: "UART8 block reset\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/APB2ENR: description: RCC APB2 peripheral clock register fields: - name: TIM1EN description: "TIM1 clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI1EN description: "SPI1 clock enable\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: TIM8EN description: "TIM8 clock enable\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: USART1EN description: "USART1 clock enable\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: TIM15EN description: "TIM15 clock enable\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: TIM16EN description: "TIM16 clock enable\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: TIM17EN description: "TIM17 clock enable\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: SPI4EN description: "SPI4 clock enable\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: SPI6EN description: "SPI6 clock enable\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: SAI1EN description: "SAI1 clock enable\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: SAI2EN description: "SAI2 clock enable\r Set and cleared by software." bit_offset: 22 bit_size: 1 - name: USBEN description: "USB clock enable\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB2LPENR: description: RCC APB2 sleep clock register fields: - name: TIM1LPEN description: "TIM1 clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI1LPEN description: "SPI1 clock enable during sleep mode\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: TIM8LPEN description: "TIM8 clock enable during sleep mode\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: USART1LPEN description: "USART1 clock enable during sleep mode\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: TIM15LPEN description: "TIM15 clock enable during sleep mode\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: TIM16LPEN description: "TIM16 clock enable during sleep mode\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: TIM17LPEN description: "TIM17 clock enable during sleep mode\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: SPI4LPEN description: "SPI4 clock enable during sleep mode\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: SPI6LPEN description: "SPI6 clock enable during sleep mode\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: SAI1LPEN description: "SAI1 clock enable during sleep mode\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: SAI2LPEN description: "SAI2 clock enable during sleep mode\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: USBLPEN description: "USB clock enable during sleep mode\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 peripheral reset register fields: - name: TIM1RST description: "TIM1 block reset\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI1RST description: "SPI1 block reset\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: TIM8RST description: "TIM8 block reset\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: USART1RST description: "USART1 block reset\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: TIM15RST description: "TIM15 block reset\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: TIM16RST description: "TIM16 block reset\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: TIM17RST description: "TIM17 block reset\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: SPI4RST description: "SPI4 block reset\r Set and reset by software." bit_offset: 19 bit_size: 1 - name: SPI6RST description: "SPI6 block reset\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: SAI1RST description: "SAI1 block reset\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: SAI2RST description: "SAI2 block reset\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: USBRST description: "USB block reset\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB3ENR: description: RCC APB3 peripheral clock register fields: - name: SYSCFGEN description: "SBS clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: SPI5EN description: "SPI5 clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: LPUART1EN description: "LPUART1 clock enable\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: I2C3EN description: "I2C3 clock enable\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: I2C4EN description: "I2C4 clock enable\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: LPTIM1EN description: "LPTIM1 clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: LPTIM3EN description: "LPTIM3 clock enable\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: LPTIM4EN description: "LPTIM4 clock enable\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: LPTIM5EN description: "LPTIM5 clock enable\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: LPTIM6EN description: "LPTIM6 clock enable\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: VREFEN description: "VREF clock enable\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: RTCAPBEN description: "RTC APB interface clock enable\r Set and reset by software." bit_offset: 21 bit_size: 1 fieldset/APB3LPENR: description: RCC APB3 sleep clock register fields: - name: SYSCFGLPEN description: "SBS clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: SPI5LPEN description: "SPI5 clock enable during Slsleepeep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: LPUART1LPEN description: "LPUART1 clock enable during sleep mode\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: I2C3LPEN description: "I2C3 clock enable during sleep mode\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: I2C4LPEN description: "I2C4 clock enable during sleep mode\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: LPTIM1LPEN description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: LPTIM3LPEN description: "LPTIM3 clock enable during sleep mode\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: LPTIM4LPEN description: "LPTIM4 clock enable during sleep mode\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: LPTIM5LPEN description: "LPTIM5 clock enable during sleep mode\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: LPTIM6LPEN description: "LPTIM6 clock enable during sleep mode\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: VREFLPEN description: "VREF clock enable during sleep mode\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: RTCAPBLPEN description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." bit_offset: 21 bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - name: SYSCFGRST description: "SBS block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: SPI5RST description: "SPI5 block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: LPUART1RST description: "LPUART1 block reset\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: I2C3RST description: "I2C3 block reset\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: I2C4RST description: "I2C4 block reset\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: LPTIM1RST description: "LPTIM1 block reset\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: LPTIM3RST description: "LPTIM3 block reset\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: LPTIM4RST description: "LPTIM4 block reset\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: LPTIM5RST description: "LPTIM5 block reset\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: LPTIM6RST description: "LPTIM6 block reset\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: VREFRST description: "VREF block reset\r Set and reset by software." bit_offset: 20 bit_size: 1 fieldset/BDCR: description: RCC Backup domain control register fields: - name: LSEON description: "LSE oscillator enabled\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: LSERDY description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." bit_offset: 1 bit_size: 1 - name: LSEBYP description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" bit_offset: 2 bit_size: 1 - name: LSEDRV description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." bit_offset: 5 bit_size: 1 - name: LSECSSD description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." bit_offset: 6 bit_size: 1 - name: LSEEXT description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." bit_offset: 7 bit_size: 1 enum: LSEEXT - name: RTCSEL description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." bit_offset: 8 bit_size: 2 enum: RTCSEL - name: RTCEN description: "RTC clock enable\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: VSWRST description: "VSwitch domain software reset\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: LSCOEN description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: LSCOSEL description: "Low-speed clock output selection\r Set and cleared by software." bit_offset: 25 bit_size: 1 enum: LSCOSEL - name: LSION description: "LSI oscillator enable\r Set and cleared by software." bit_offset: 26 bit_size: 1 - name: LSIRDY description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." bit_offset: 27 bit_size: 1 fieldset/CCIPR1: description: RCC kernel clock configuration register fields: - name: USART1SEL description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 0 bit_size: 3 enum: USART1SEL - name: USART2SEL description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 3 bit_size: 3 enum: USARTSEL - name: USART3SEL description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 6 bit_size: 3 enum: USARTSEL - name: UART4SEL description: "UART4 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 9 bit_size: 3 enum: USARTSEL - name: UART5SEL description: "UART5 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 12 bit_size: 3 enum: USARTSEL - name: USART6SEL description: "USART6 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 15 bit_size: 3 enum: USARTSEL - name: UART7SEL description: "UART7 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 18 bit_size: 3 enum: USARTSEL - name: UART8SEL description: "UART8 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 21 bit_size: 3 enum: USARTSEL - name: UART9SEL description: "UART9 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 24 bit_size: 3 enum: USARTSEL - name: USART10SEL description: "USART10 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 27 bit_size: 3 enum: USARTSEL - name: TIMICSEL description: "TIM12, TIM15 and LPTIM2 input capture source selection\r Set and reset by software." bit_offset: 31 bit_size: 1 enum: TIMICSEL fieldset/CCIPR2: description: RCC kernel clock configuration register fields: - name: USART11SEL description: "USART11 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 0 bit_size: 3 enum: USARTSEL - name: USART12SEL description: "USART12 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 4 bit_size: 3 enum: USARTSEL - name: LPTIM1SEL description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 8 bit_size: 3 enum: LPTIMSEL - name: LPTIM2SEL description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 12 bit_size: 3 enum: LPTIM2SEL - name: LPTIM3SEL description: "LPTIM3 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 16 bit_size: 3 enum: LPTIMSEL - name: LPTIM4SEL description: "LPTIM4 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 20 bit_size: 3 enum: LPTIMSEL - name: LPTIM5SEL description: "LPTIM5 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 24 bit_size: 3 enum: LPTIMSEL - name: LPTIM6SEL description: "LPTIM6 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 28 bit_size: 3 enum: LPTIMSEL fieldset/CCIPR3: description: RCC kernel clock configuration register fields: - name: SPI1SEL description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 0 bit_size: 3 enum: SPI1SEL - name: SPI2SEL description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 3 bit_size: 3 enum: SPI2SEL - name: SPI3SEL description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 6 bit_size: 3 enum: SPI3SEL - name: SPI4SEL description: "SPI4 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 9 bit_size: 3 enum: SPI4SEL - name: SPI5SEL description: "SPI5 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 12 bit_size: 3 enum: SPI5SEL - name: SPI6SEL description: "SPI6 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 15 bit_size: 3 enum: SPI6SEL - name: LPUART1SEL description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 24 bit_size: 3 enum: LPUSARTSEL fieldset/CCIPR4: description: RCC kernel clock configuration register fields: - name: OCTOSPI1SEL description: "OCTOSPI1 kernel clock source selection\r Set and reset by software." bit_offset: 0 bit_size: 2 enum: OCTOSPISEL - name: SYSTICKSEL description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." bit_offset: 2 bit_size: 2 enum: SYSTICKSEL - name: USBSEL description: USB kernel clock source selection bit_offset: 4 bit_size: 2 enum: USBSEL - name: SDMMC1SEL description: SDMMC1 kernel clock source selection bit_offset: 6 bit_size: 1 enum: SDMMCSEL - name: SDMMC2SEL description: SDMMC2 kernel clock source selection bit_offset: 7 bit_size: 1 enum: SDMMCSEL - name: I2C1SEL description: I2C1 kernel clock source selection bit_offset: 16 bit_size: 2 enum: I2CSEL - name: I2C2SEL description: I2C2 kernel clock source selection bit_offset: 18 bit_size: 2 enum: I2CSEL - name: I2C3SEL description: I2C3 kernel clock source selection bit_offset: 20 bit_size: 2 enum: I2C34SEL - name: I2C4SEL description: I2C4 kernel clock source selection bit_offset: 22 bit_size: 2 enum: I2C34SEL - name: I3C1SEL description: I3C1 kernel clock source selection bit_offset: 24 bit_size: 2 enum: I2CSEL fieldset/CCIPR5: description: RCC kernel clock configuration register fields: - name: ADCDACSEL description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 0 bit_size: 3 enum: ADCDACSEL - name: DACHOLDSEL description: DAC hold clock bit_offset: 3 bit_size: 1 enum: DACHOLDSEL - name: RNGSEL description: RNG kernel clock source selection bit_offset: 4 bit_size: 2 enum: RNGSEL - name: CECSEL description: HSMI-CEC kernel clock source selection bit_offset: 6 bit_size: 2 enum: CECSEL - name: FDCAN12SEL description: FDCAN1 and FDCAN2 kernel clock source selection bit_offset: 8 bit_size: 2 enum: FDCANSEL - name: SAI1SEL description: "SAI1 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 16 bit_size: 3 enum: SAISEL - name: SAI2SEL description: "SAI2 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 19 bit_size: 3 enum: SAISEL - name: PERSEL description: per_ck clock source selection bit_offset: 30 bit_size: 2 enum: PERSEL fieldset/CFGR: description: RCC clock configuration register fields: - name: SW description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" bit_offset: 0 bit_size: 3 enum: SW - name: SWS description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" bit_offset: 3 bit_size: 3 enum: SW - name: STOPWUCK description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." bit_offset: 6 bit_size: 1 enum: STOPWUCK - name: STOPKERWUCK description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." bit_offset: 7 bit_size: 1 enum: STOPKERWUCK - name: RTCPRE description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." bit_offset: 8 bit_size: 6 - name: TIMPRE description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." bit_offset: 15 bit_size: 1 enum: TIMPRE - name: MCO1PRE description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." bit_offset: 18 bit_size: 4 enum: MCOPRE - name: MCO1SEL description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 22 bit_size: 3 enum: MCO1SEL - name: MCO2PRE description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." bit_offset: 25 bit_size: 4 enum: MCOPRE - name: MCO2SEL description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 29 bit_size: 3 enum: MCO2SEL fieldset/CFGR2: description: RCC CPU domain clock configuration register 2 fields: - name: HPRE description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" bit_offset: 0 bit_size: 4 enum: HPRE - name: PPRE1 description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" bit_offset: 4 bit_size: 3 enum: PPRE - name: PPRE2 description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE3 description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" bit_offset: 12 bit_size: 3 enum: PPRE - name: AHB1DIS description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" bit_offset: 16 bit_size: 1 - name: AHB2DIS description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" bit_offset: 17 bit_size: 1 - name: AHB4DIS description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" bit_offset: 19 bit_size: 1 - name: APB1DIS description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" bit_offset: 20 bit_size: 1 - name: APB2DIS description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" bit_offset: 21 bit_size: 1 - name: APB3DIS description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" bit_offset: 22 bit_size: 1 fieldset/CICR: description: RCC clock source interrupt clear register fields: - name: LSIRDYC description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." bit_offset: 0 bit_size: 1 - name: LSERDYC description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." bit_offset: 1 bit_size: 1 - name: CSIRDYC description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." bit_offset: 2 bit_size: 1 - name: HSIRDYC description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." bit_offset: 3 bit_size: 1 - name: HSERDYC description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." bit_offset: 4 bit_size: 1 - name: HSI48RDYC description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." bit_offset: 5 bit_size: 1 - name: PLLRDYC description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." bit_offset: 6 bit_size: 1 array: len: 3 stride: 1 - name: HSECSSC description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." bit_offset: 10 bit_size: 1 fieldset/CIER: description: RCC clock source interrupt enable register fields: - name: LSIRDYIE description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." bit_offset: 0 bit_size: 1 - name: LSERDYIE description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." bit_offset: 1 bit_size: 1 - name: CSIRDYIE description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." bit_offset: 2 bit_size: 1 - name: HSIRDYIE description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." bit_offset: 3 bit_size: 1 - name: HSERDYIE description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." bit_offset: 4 bit_size: 1 - name: HSI48RDYIE description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." bit_offset: 5 bit_size: 1 - name: PLLRDYIE description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." bit_offset: 6 bit_size: 1 array: len: 3 stride: 1 fieldset/CIFR: description: RCC clock source interrupt flag register fields: - name: LSIRDYF description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." bit_offset: 0 bit_size: 1 - name: LSERDYF description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." bit_offset: 1 bit_size: 1 - name: CSIRDYF description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." bit_offset: 2 bit_size: 1 - name: HSIRDYF description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." bit_offset: 3 bit_size: 1 - name: HSERDYF description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." bit_offset: 4 bit_size: 1 - name: HSI48RDYF description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." bit_offset: 5 bit_size: 1 - name: PLLRDYF description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." bit_offset: 6 bit_size: 1 array: len: 3 stride: 1 - name: HSECSSF description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." bit_offset: 10 bit_size: 1 fieldset/CR: description: RCC clock control register fields: - name: HSION description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." bit_offset: 0 bit_size: 1 - name: HSIRDY description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." bit_offset: 1 bit_size: 1 - name: HSIKERON description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." bit_offset: 2 bit_size: 1 - name: HSIDIV description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." bit_offset: 3 bit_size: 2 enum: HSIDIV - name: HSIDIVF description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." bit_offset: 5 bit_size: 1 - name: CSION description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." bit_offset: 8 bit_size: 1 - name: CSIRDY description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." bit_offset: 9 bit_size: 1 - name: CSIKERON description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." bit_offset: 10 bit_size: 1 - name: HSI48ON description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." bit_offset: 12 bit_size: 1 - name: HSI48RDY description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." bit_offset: 13 bit_size: 1 - name: HSEON description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." bit_offset: 16 bit_size: 1 - name: HSERDY description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." bit_offset: 17 bit_size: 1 - name: HSEBYP description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." bit_offset: 18 bit_size: 1 - name: HSECSSON description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." bit_offset: 19 bit_size: 1 - name: HSEEXT description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." bit_offset: 20 bit_size: 1 enum: HSEEXT - name: PLLON description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." bit_offset: 24 bit_size: 1 array: len: 3 stride: 2 - name: PLLRDY description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." bit_offset: 25 bit_size: 1 array: len: 3 stride: 2 fieldset/CRRCR: description: RCC clock recovery RC register fields: - name: HSI48CAL description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." bit_offset: 0 bit_size: 10 fieldset/CSICFGR: description: RCC CSI calibration register fields: - name: CSICAL description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." bit_offset: 0 bit_size: 8 - name: CSITRIM description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." bit_offset: 16 bit_size: 6 fieldset/HSICFGR: description: RCC HSI calibration register fields: - name: HSICAL description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." bit_offset: 0 bit_size: 12 - name: HSITRIM description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." bit_offset: 16 bit_size: 7 fieldset/PLLCFGR: description: RCC PLL clock source selection register fields: - name: PLLSRC description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLRGE description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." bit_offset: 2 bit_size: 2 enum: PLLRGE - name: PLLFRACEN description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." bit_offset: 4 bit_size: 1 - name: PLLVCOSEL description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." bit_offset: 5 bit_size: 1 enum: PLLVCOSEL - name: DIVM description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." bit_offset: 8 bit_size: 6 enum: PLLM - name: PLLPEN description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." bit_offset: 16 bit_size: 1 - name: PLLQEN description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 17 bit_size: 1 - name: PLLREN description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 18 bit_size: 1 fieldset/PLLDIVR: description: RCC PLL1 dividers register fields: - name: PLLN description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" bit_offset: 0 bit_size: 9 enum: PLLN - name: PLLP description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." bit_offset: 9 bit_size: 7 enum: PLLDIV - name: PLLQ description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 16 bit_size: 7 enum: PLLDIV - name: PLLR description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 24 bit_size: 7 enum: PLLDIV fieldset/PLLFRACR: description: RCC PLL1 fractional divider register fields: - name: PLLFRACN description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" bit_offset: 3 bit_size: 13 fieldset/PRIVCFGR: description: RCC privilege configuration register fields: - name: SPRIV description: "RCC secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." bit_offset: 0 bit_size: 1 enum: SPRIV - name: NSPRIV description: "RCC non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." bit_offset: 1 bit_size: 1 enum: NSPRIV fieldset/RSR: description: RCC reset status register fields: - name: RMVF description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." bit_offset: 23 bit_size: 1 - name: PINRSTF description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." bit_offset: 26 bit_size: 1 - name: BORRSTF description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." bit_offset: 27 bit_size: 1 - name: SFTRSTF description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." bit_offset: 31 bit_size: 1 fieldset/SECCFGR: description: RCC secure configuration register fields: - name: HSISEC description: "HSI clock configuration and status bits security\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: HSESEC description: "HSE clock configuration bits, status bits and HSE_CSS security\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: CSISEC description: "CSI clock configuration and status bits security\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: LSISEC description: "LSI clock configuration and status bits security\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: LSESEC description: "LSE clock configuration and status bits security\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: SYSCLKSEC description: "SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration security\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: PRESCSEC description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: PLLSEC description: "PLL1 clock configuration and status bits security\r Set and reset by software." bit_offset: 7 bit_size: 1 array: len: 3 stride: 1 - name: HSI48SEC description: "HSI48 clock configuration and status bits security\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: RMVFSEC description: "Remove reset flag security\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: PERSELSEC description: "per_ck selection security\r Set and reset by software." bit_offset: 13 bit_size: 1 enum/ADCDACSEL: bit_size: 3 variants: - name: HCLK2 description: rcc_hclk selected as kernel clock (default after reset) value: 0 - name: SYS description: sys_ck selected as kernel clock value: 1 - name: PLL2_R description: pll2_r_ck selected as kernel clock value: 2 - name: HSE description: hse_ck selected as kernel clock value: 3 - name: HSI description: hsi_ker_ck selected as kernel clock value: 4 - name: CSI description: csi_ker_ck selected as kernel clock value: 5 enum/CECSEL: bit_size: 2 variants: - name: LSE description: lse_ck selected as kernel clock (default after reset) value: 0 - name: LSI description: lsi_ker_ck selected as kernel clock value: 1 - name: CSI_DIV_122 description: csi_ker_ck/122 selected as kernel clock value: 2 enum/DACHOLDSEL: bit_size: 1 variants: - name: DAC_HOLD description: dac_hold_ck selected as kernel clock (default after reset) value: 0 - name: DAC_HOLD_2 description: dac_hold_ck selected as kernel clock value: 1 enum/FDCANSEL: bit_size: 2 variants: - name: HSE description: hse_ck selected as kernel clock (default after reset) value: 0 - name: PLL1_Q description: pll1_q_ck selected as kernel clock value: 1 - name: PLL2_Q description: pll2_q_ck selected as kernel clock value: 2 enum/HPRE: bit_size: 4 variants: - name: Div1 description: sys_ck not divided value: 0 - name: Div2 description: sys_ck divided by 2 value: 8 - name: Div4 description: sys_ck divided by 4 value: 9 - name: Div8 description: sys_ck divided by 8 value: 10 - name: Div16 description: sys_ck divided by 16 value: 11 - name: Div64 description: sys_ck divided by 64 value: 12 - name: Div128 description: sys_ck divided by 128 value: 13 - name: Div256 description: sys_ck divided by 256 value: 14 - name: Div512 description: sys_ck divided by 512 value: 15 enum/HSEEXT: bit_size: 1 variants: - name: Analog description: HSE in analog mode (default after reset) value: 0 - name: Digital description: HSE in digital mode value: 1 enum/HSIDIV: bit_size: 2 variants: - name: Div1 description: No division value: 0 - name: Div2 description: Division by 2 value: 1 - name: Div4 description: Division by 4 value: 2 - name: Div8 description: Division by 8 value: 3 enum/I2C34SEL: bit_size: 2 variants: - name: PCLK3 description: rcc_pclk3 selected as peripheral clock value: 0 - name: PLL3_R description: pll3_r selected as peripheral clock value: 1 - name: HSI description: hsi_ker selected as peripheral clock value: 2 - name: CSI description: csi_ker selected as peripheral clock value: 3 enum/I2CSEL: bit_size: 2 variants: - name: PCLK1 description: rcc_pclk1 selected as peripheral clock value: 0 - name: PLL3_R description: pll3_r selected as peripheral clock value: 1 - name: HSI description: hsi_ker selected as peripheral clock value: 2 - name: CSI description: csi_ker selected as peripheral clock value: 3 enum/LPTIM2SEL: bit_size: 3 variants: - name: PCLK1 description: rcc_pclk1 selected as peripheral clock value: 0 - name: PLL2_P description: pll2_p selected as peripheral clock value: 1 - name: LSE description: LSE selected as peripheral clock value: 3 - name: LSI description: LSI selected as peripheral clock value: 4 - name: PER description: PER selected as peripheral clock value: 5 enum/LPTIMSEL: bit_size: 3 variants: - name: PCLK3 description: rcc_pclk3 selected as peripheral clock value: 0 - name: PLL2_P description: pll2_p selected as peripheral clock value: 1 - name: PLL3_R description: pll3_r selected as peripheral clock value: 2 - name: LSE description: LSE selected as peripheral clock value: 3 - name: LSI description: LSI selected as peripheral clock value: 4 - name: PER description: PER selected as peripheral clock value: 5 enum/LPUSARTSEL: bit_size: 3 variants: - name: PCLK3 description: rcc_pclk3 selected as kernel clock (default after reset) value: 0 - name: PLL2_Q description: pll2_q_ck selected as kernel clock value: 1 - name: PLL3_Q description: pll3_q_ck selected as kernel clock value: 2 - name: HSI description: hsi_ker_ck selected as kernel clock value: 3 - name: CSI description: csi_ker_ck selected as kernel clock value: 4 - name: LSE description: lse_ck selected as kernel clock value: 5 enum/LSCOSEL: bit_size: 1 variants: - name: LSI description: LSI clock selected value: 0 - name: LSE description: LSE clock selected value: 1 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/LSEEXT: bit_size: 1 variants: - name: Analog description: LSE in analog mode (default after Backup domain reset) value: 0 - name: Digital description: LSE in digital mode (do not use if RTC is active). value: 1 enum/MCO1SEL: bit_size: 3 variants: - name: HSI description: HSI selected for micro-controller clock output value: 0 - name: LSE description: LSE selected for micro-controller clock output value: 1 - name: HSE description: HSE selected for micro-controller clock output value: 2 - name: PLL1_Q description: pll1_q selected for micro-controller clock output value: 3 - name: HSI48 description: HSI48 selected for micro-controller clock output value: 4 enum/MCO2SEL: bit_size: 3 variants: - name: SYS description: System clock selected for micro-controller clock output value: 0 - name: PLL2_P description: pll2_p selected for micro-controller clock output value: 1 - name: HSE description: HSE selected for micro-controller clock output value: 2 - name: PLL1_P description: pll1_p selected for micro-controller clock output value: 3 - name: CSI description: CSI selected for micro-controller clock output value: 4 - name: LSI description: LSI selected for micro-controller clock output value: 5 enum/MCOPRE: bit_size: 4 variants: - name: Div1 description: Divide by 1 value: 1 - name: Div2 description: Divide by 2 value: 2 - name: Div3 description: Divide by 3 value: 3 - name: Div4 description: Divide by 4 value: 4 - name: Div5 description: Divide by 5 value: 5 - name: Div6 description: Divide by 6 value: 6 - name: Div7 description: Divide by 7 value: 7 - name: Div8 description: Divide by 8 value: 8 - name: Div9 description: Divide by 9 value: 9 - name: Div10 description: Divide by 10 value: 10 - name: Div11 description: Divide by 11 value: 11 - name: Div12 description: Divide by 12 value: 12 - name: Div13 description: Divide by 13 value: 13 - name: Div14 description: Divide by 14 value: 14 - name: Div15 description: Divide by 15 value: 15 enum/NSPRIV: bit_size: 1 variants: - name: B_0x0 description: Read and write to RCC non-secure functions can be done by privileged or unprivileged access. value: 0 - name: B_0x1 description: Read and write to RCC non-secure functions can be done by privileged access only value: 1 enum/OCTOSPISEL: bit_size: 2 variants: - name: HCLK4 description: rcc_hclk selected as kernel clock (default after reset) value: 0 - name: PLL1_Q description: pll1_q_ck selected as kernel clock value: 1 - name: PLL2_R description: pll2_r_ck selected as kernel clock value: 2 - name: PER description: per_ck selected as kernel clock value: 3 enum/PERSEL: bit_size: 2 variants: - name: HSI description: hsi_ker_ck selected as kernel clock (default after reset) value: 0 - name: CSI description: csi_ker_ck selected as kernel clock value: 1 - name: HSE description: hse_ck selected as kernel clock value: 2 enum/PLLDIV: bit_size: 7 variants: - name: Div1 value: 0 - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 - name: Div9 value: 8 - name: Div10 value: 9 - name: Div11 value: 10 - name: Div12 value: 11 - name: Div13 value: 12 - name: Div14 value: 13 - name: Div15 value: 14 - name: Div16 value: 15 - name: Div17 value: 16 - name: Div18 value: 17 - name: Div19 value: 18 - name: Div20 value: 19 - name: Div21 value: 20 - name: Div22 value: 21 - name: Div23 value: 22 - name: Div24 value: 23 - name: Div25 value: 24 - name: Div26 value: 25 - name: Div27 value: 26 - name: Div28 value: 27 - name: Div29 value: 28 - name: Div30 value: 29 - name: Div31 value: 30 - name: Div32 value: 31 - name: Div33 value: 32 - name: Div34 value: 33 - name: Div35 value: 34 - name: Div36 value: 35 - name: Div37 value: 36 - name: Div38 value: 37 - name: Div39 value: 38 - name: Div40 value: 39 - name: Div41 value: 40 - name: Div42 value: 41 - name: Div43 value: 42 - name: Div44 value: 43 - name: Div45 value: 44 - name: Div46 value: 45 - name: Div47 value: 46 - name: Div48 value: 47 - name: Div49 value: 48 - name: Div50 value: 49 - name: Div51 value: 50 - name: Div52 value: 51 - name: Div53 value: 52 - name: Div54 value: 53 - name: Div55 value: 54 - name: Div56 value: 55 - name: Div57 value: 56 - name: Div58 value: 57 - name: Div59 value: 58 - name: Div60 value: 59 - name: Div61 value: 60 - name: Div62 value: 61 - name: Div63 value: 62 - name: Div64 value: 63 - name: Div65 value: 64 - name: Div66 value: 65 - name: Div67 value: 66 - name: Div68 value: 67 - name: Div69 value: 68 - name: Div70 value: 69 - name: Div71 value: 70 - name: Div72 value: 71 - name: Div73 value: 72 - name: Div74 value: 73 - name: Div75 value: 74 - name: Div76 value: 75 - name: Div77 value: 76 - name: Div78 value: 77 - name: Div79 value: 78 - name: Div80 value: 79 - name: Div81 value: 80 - name: Div82 value: 81 - name: Div83 value: 82 - name: Div84 value: 83 - name: Div85 value: 84 - name: Div86 value: 85 - name: Div87 value: 86 - name: Div88 value: 87 - name: Div89 value: 88 - name: Div90 value: 89 - name: Div91 value: 90 - name: Div92 value: 91 - name: Div93 value: 92 - name: Div94 value: 93 - name: Div95 value: 94 - name: Div96 value: 95 - name: Div97 value: 96 - name: Div98 value: 97 - name: Div99 value: 98 - name: Div100 value: 99 - name: Div101 value: 100 - name: Div102 value: 101 - name: Div103 value: 102 - name: Div104 value: 103 - name: Div105 value: 104 - name: Div106 value: 105 - name: Div107 value: 106 - name: Div108 value: 107 - name: Div109 value: 108 - name: Div110 value: 109 - name: Div111 value: 110 - name: Div112 value: 111 - name: Div113 value: 112 - name: Div114 value: 113 - name: Div115 value: 114 - name: Div116 value: 115 - name: Div117 value: 116 - name: Div118 value: 117 - name: Div119 value: 118 - name: Div120 value: 119 - name: Div121 value: 120 - name: Div122 value: 121 - name: Div123 value: 122 - name: Div124 value: 123 - name: Div125 value: 124 - name: Div126 value: 125 - name: Div127 value: 126 - name: Div128 value: 127 enum/PLLM: bit_size: 6 variants: - name: Div1 value: 1 - name: Div2 value: 2 - name: Div3 value: 3 - name: Div4 value: 4 - name: Div5 value: 5 - name: Div6 value: 6 - name: Div7 value: 7 - name: Div8 value: 8 - name: Div9 value: 9 - name: Div10 value: 10 - name: Div11 value: 11 - name: Div12 value: 12 - name: Div13 value: 13 - name: Div14 value: 14 - name: Div15 value: 15 - name: Div16 value: 16 - name: Div17 value: 17 - name: Div18 value: 18 - name: Div19 value: 19 - name: Div20 value: 20 - name: Div21 value: 21 - name: Div22 value: 22 - name: Div23 value: 23 - name: Div24 value: 24 - name: Div25 value: 25 - name: Div26 value: 26 - name: Div27 value: 27 - name: Div28 value: 28 - name: Div29 value: 29 - name: Div30 value: 30 - name: Div31 value: 31 - name: Div32 value: 32 - name: Div33 value: 33 - name: Div34 value: 34 - name: Div35 value: 35 - name: Div36 value: 36 - name: Div37 value: 37 - name: Div38 value: 38 - name: Div39 value: 39 - name: Div40 value: 40 - name: Div41 value: 41 - name: Div42 value: 42 - name: Div43 value: 43 - name: Div44 value: 44 - name: Div45 value: 45 - name: Div46 value: 46 - name: Div47 value: 47 - name: Div48 value: 48 - name: Div49 value: 49 - name: Div50 value: 50 - name: Div51 value: 51 - name: Div52 value: 52 - name: Div53 value: 53 - name: Div54 value: 54 - name: Div55 value: 55 - name: Div56 value: 56 - name: Div57 value: 57 - name: Div58 value: 58 - name: Div59 value: 59 - name: Div60 value: 60 - name: Div61 value: 61 - name: Div62 value: 62 enum/PLLN: bit_size: 9 variants: - name: Mul4 value: 3 - name: Mul5 value: 4 - name: Mul6 value: 5 - name: Mul7 value: 6 - name: Mul8 value: 7 - name: Mul9 value: 8 - name: Mul10 value: 9 - name: Mul11 value: 10 - name: Mul12 value: 11 - name: Mul13 value: 12 - name: Mul14 value: 13 - name: Mul15 value: 14 - name: Mul16 value: 15 - name: Mul17 value: 16 - name: Mul18 value: 17 - name: Mul19 value: 18 - name: Mul20 value: 19 - name: Mul21 value: 20 - name: Mul22 value: 21 - name: Mul23 value: 22 - name: Mul24 value: 23 - name: Mul25 value: 24 - name: Mul26 value: 25 - name: Mul27 value: 26 - name: Mul28 value: 27 - name: Mul29 value: 28 - name: Mul30 value: 29 - name: Mul31 value: 30 - name: Mul32 value: 31 - name: Mul33 value: 32 - name: Mul34 value: 33 - name: Mul35 value: 34 - name: Mul36 value: 35 - name: Mul37 value: 36 - name: Mul38 value: 37 - name: Mul39 value: 38 - name: Mul40 value: 39 - name: Mul41 value: 40 - name: Mul42 value: 41 - name: Mul43 value: 42 - name: Mul44 value: 43 - name: Mul45 value: 44 - name: Mul46 value: 45 - name: Mul47 value: 46 - name: Mul48 value: 47 - name: Mul49 value: 48 - name: Mul50 value: 49 - name: Mul51 value: 50 - name: Mul52 value: 51 - name: Mul53 value: 52 - name: Mul54 value: 53 - name: Mul55 value: 54 - name: Mul56 value: 55 - name: Mul57 value: 56 - name: Mul58 value: 57 - name: Mul59 value: 58 - name: Mul60 value: 59 - name: Mul61 value: 60 - name: Mul62 value: 61 - name: Mul63 value: 62 - name: Mul64 value: 63 - name: Mul65 value: 64 - name: Mul66 value: 65 - name: Mul67 value: 66 - name: Mul68 value: 67 - name: Mul69 value: 68 - name: Mul70 value: 69 - name: Mul71 value: 70 - name: Mul72 value: 71 - name: Mul73 value: 72 - name: Mul74 value: 73 - name: Mul75 value: 74 - name: Mul76 value: 75 - name: Mul77 value: 76 - name: Mul78 value: 77 - name: Mul79 value: 78 - name: Mul80 value: 79 - name: Mul81 value: 80 - name: Mul82 value: 81 - name: Mul83 value: 82 - name: Mul84 value: 83 - name: Mul85 value: 84 - name: Mul86 value: 85 - name: Mul87 value: 86 - name: Mul88 value: 87 - name: Mul89 value: 88 - name: Mul90 value: 89 - name: Mul91 value: 90 - name: Mul92 value: 91 - name: Mul93 value: 92 - name: Mul94 value: 93 - name: Mul95 value: 94 - name: Mul96 value: 95 - name: Mul97 value: 96 - name: Mul98 value: 97 - name: Mul99 value: 98 - name: Mul100 value: 99 - name: Mul101 value: 100 - name: Mul102 value: 101 - name: Mul103 value: 102 - name: Mul104 value: 103 - name: Mul105 value: 104 - name: Mul106 value: 105 - name: Mul107 value: 106 - name: Mul108 value: 107 - name: Mul109 value: 108 - name: Mul110 value: 109 - name: Mul111 value: 110 - name: Mul112 value: 111 - name: Mul113 value: 112 - name: Mul114 value: 113 - name: Mul115 value: 114 - name: Mul116 value: 115 - name: Mul117 value: 116 - name: Mul118 value: 117 - name: Mul119 value: 118 - name: Mul120 value: 119 - name: Mul121 value: 120 - name: Mul122 value: 121 - name: Mul123 value: 122 - name: Mul124 value: 123 - name: Mul125 value: 124 - name: Mul126 value: 125 - name: Mul127 value: 126 - name: Mul128 value: 127 - name: Mul129 value: 128 - name: Mul130 value: 129 - name: Mul131 value: 130 - name: Mul132 value: 131 - name: Mul133 value: 132 - name: Mul134 value: 133 - name: Mul135 value: 134 - name: Mul136 value: 135 - name: Mul137 value: 136 - name: Mul138 value: 137 - name: Mul139 value: 138 - name: Mul140 value: 139 - name: Mul141 value: 140 - name: Mul142 value: 141 - name: Mul143 value: 142 - name: Mul144 value: 143 - name: Mul145 value: 144 - name: Mul146 value: 145 - name: Mul147 value: 146 - name: Mul148 value: 147 - name: Mul149 value: 148 - name: Mul150 value: 149 - name: Mul151 value: 150 - name: Mul152 value: 151 - name: Mul153 value: 152 - name: Mul154 value: 153 - name: Mul155 value: 154 - name: Mul156 value: 155 - name: Mul157 value: 156 - name: Mul158 value: 157 - name: Mul159 value: 158 - name: Mul160 value: 159 - name: Mul161 value: 160 - name: Mul162 value: 161 - name: Mul163 value: 162 - name: Mul164 value: 163 - name: Mul165 value: 164 - name: Mul166 value: 165 - name: Mul167 value: 166 - name: Mul168 value: 167 - name: Mul169 value: 168 - name: Mul170 value: 169 - name: Mul171 value: 170 - name: Mul172 value: 171 - name: Mul173 value: 172 - name: Mul174 value: 173 - name: Mul175 value: 174 - name: Mul176 value: 175 - name: Mul177 value: 176 - name: Mul178 value: 177 - name: Mul179 value: 178 - name: Mul180 value: 179 - name: Mul181 value: 180 - name: Mul182 value: 181 - name: Mul183 value: 182 - name: Mul184 value: 183 - name: Mul185 value: 184 - name: Mul186 value: 185 - name: Mul187 value: 186 - name: Mul188 value: 187 - name: Mul189 value: 188 - name: Mul190 value: 189 - name: Mul191 value: 190 - name: Mul192 value: 191 - name: Mul193 value: 192 - name: Mul194 value: 193 - name: Mul195 value: 194 - name: Mul196 value: 195 - name: Mul197 value: 196 - name: Mul198 value: 197 - name: Mul199 value: 198 - name: Mul200 value: 199 - name: Mul201 value: 200 - name: Mul202 value: 201 - name: Mul203 value: 202 - name: Mul204 value: 203 - name: Mul205 value: 204 - name: Mul206 value: 205 - name: Mul207 value: 206 - name: Mul208 value: 207 - name: Mul209 value: 208 - name: Mul210 value: 209 - name: Mul211 value: 210 - name: Mul212 value: 211 - name: Mul213 value: 212 - name: Mul214 value: 213 - name: Mul215 value: 214 - name: Mul216 value: 215 - name: Mul217 value: 216 - name: Mul218 value: 217 - name: Mul219 value: 218 - name: Mul220 value: 219 - name: Mul221 value: 220 - name: Mul222 value: 221 - name: Mul223 value: 222 - name: Mul224 value: 223 - name: Mul225 value: 224 - name: Mul226 value: 225 - name: Mul227 value: 226 - name: Mul228 value: 227 - name: Mul229 value: 228 - name: Mul230 value: 229 - name: Mul231 value: 230 - name: Mul232 value: 231 - name: Mul233 value: 232 - name: Mul234 value: 233 - name: Mul235 value: 234 - name: Mul236 value: 235 - name: Mul237 value: 236 - name: Mul238 value: 237 - name: Mul239 value: 238 - name: Mul240 value: 239 - name: Mul241 value: 240 - name: Mul242 value: 241 - name: Mul243 value: 242 - name: Mul244 value: 243 - name: Mul245 value: 244 - name: Mul246 value: 245 - name: Mul247 value: 246 - name: Mul248 value: 247 - name: Mul249 value: 248 - name: Mul250 value: 249 - name: Mul251 value: 250 - name: Mul252 value: 251 - name: Mul253 value: 252 - name: Mul254 value: 253 - name: Mul255 value: 254 - name: Mul256 value: 255 - name: Mul257 value: 256 - name: Mul258 value: 257 - name: Mul259 value: 258 - name: Mul260 value: 259 - name: Mul261 value: 260 - name: Mul262 value: 261 - name: Mul263 value: 262 - name: Mul264 value: 263 - name: Mul265 value: 264 - name: Mul266 value: 265 - name: Mul267 value: 266 - name: Mul268 value: 267 - name: Mul269 value: 268 - name: Mul270 value: 269 - name: Mul271 value: 270 - name: Mul272 value: 271 - name: Mul273 value: 272 - name: Mul274 value: 273 - name: Mul275 value: 274 - name: Mul276 value: 275 - name: Mul277 value: 276 - name: Mul278 value: 277 - name: Mul279 value: 278 - name: Mul280 value: 279 - name: Mul281 value: 280 - name: Mul282 value: 281 - name: Mul283 value: 282 - name: Mul284 value: 283 - name: Mul285 value: 284 - name: Mul286 value: 285 - name: Mul287 value: 286 - name: Mul288 value: 287 - name: Mul289 value: 288 - name: Mul290 value: 289 - name: Mul291 value: 290 - name: Mul292 value: 291 - name: Mul293 value: 292 - name: Mul294 value: 293 - name: Mul295 value: 294 - name: Mul296 value: 295 - name: Mul297 value: 296 - name: Mul298 value: 297 - name: Mul299 value: 298 - name: Mul300 value: 299 - name: Mul301 value: 300 - name: Mul302 value: 301 - name: Mul303 value: 302 - name: Mul304 value: 303 - name: Mul305 value: 304 - name: Mul306 value: 305 - name: Mul307 value: 306 - name: Mul308 value: 307 - name: Mul309 value: 308 - name: Mul310 value: 309 - name: Mul311 value: 310 - name: Mul312 value: 311 - name: Mul313 value: 312 - name: Mul314 value: 313 - name: Mul315 value: 314 - name: Mul316 value: 315 - name: Mul317 value: 316 - name: Mul318 value: 317 - name: Mul319 value: 318 - name: Mul320 value: 319 - name: Mul321 value: 320 - name: Mul322 value: 321 - name: Mul323 value: 322 - name: Mul324 value: 323 - name: Mul325 value: 324 - name: Mul326 value: 325 - name: Mul327 value: 326 - name: Mul328 value: 327 - name: Mul329 value: 328 - name: Mul330 value: 329 - name: Mul331 value: 330 - name: Mul332 value: 331 - name: Mul333 value: 332 - name: Mul334 value: 333 - name: Mul335 value: 334 - name: Mul336 value: 335 - name: Mul337 value: 336 - name: Mul338 value: 337 - name: Mul339 value: 338 - name: Mul340 value: 339 - name: Mul341 value: 340 - name: Mul342 value: 341 - name: Mul343 value: 342 - name: Mul344 value: 343 - name: Mul345 value: 344 - name: Mul346 value: 345 - name: Mul347 value: 346 - name: Mul348 value: 347 - name: Mul349 value: 348 - name: Mul350 value: 349 - name: Mul351 value: 350 - name: Mul352 value: 351 - name: Mul353 value: 352 - name: Mul354 value: 353 - name: Mul355 value: 354 - name: Mul356 value: 355 - name: Mul357 value: 356 - name: Mul358 value: 357 - name: Mul359 value: 358 - name: Mul360 value: 359 - name: Mul361 value: 360 - name: Mul362 value: 361 - name: Mul363 value: 362 - name: Mul364 value: 363 - name: Mul365 value: 364 - name: Mul366 value: 365 - name: Mul367 value: 366 - name: Mul368 value: 367 - name: Mul369 value: 368 - name: Mul370 value: 369 - name: Mul371 value: 370 - name: Mul372 value: 371 - name: Mul373 value: 372 - name: Mul374 value: 373 - name: Mul375 value: 374 - name: Mul376 value: 375 - name: Mul377 value: 376 - name: Mul378 value: 377 - name: Mul379 value: 378 - name: Mul380 value: 379 - name: Mul381 value: 380 - name: Mul382 value: 381 - name: Mul383 value: 382 - name: Mul384 value: 383 - name: Mul385 value: 384 - name: Mul386 value: 385 - name: Mul387 value: 386 - name: Mul388 value: 387 - name: Mul389 value: 388 - name: Mul390 value: 389 - name: Mul391 value: 390 - name: Mul392 value: 391 - name: Mul393 value: 392 - name: Mul394 value: 393 - name: Mul395 value: 394 - name: Mul396 value: 395 - name: Mul397 value: 396 - name: Mul398 value: 397 - name: Mul399 value: 398 - name: Mul400 value: 399 - name: Mul401 value: 400 - name: Mul402 value: 401 - name: Mul403 value: 402 - name: Mul404 value: 403 - name: Mul405 value: 404 - name: Mul406 value: 405 - name: Mul407 value: 406 - name: Mul408 value: 407 - name: Mul409 value: 408 - name: Mul410 value: 409 - name: Mul411 value: 410 - name: Mul412 value: 411 - name: Mul413 value: 412 - name: Mul414 value: 413 - name: Mul415 value: 414 - name: Mul416 value: 415 - name: Mul417 value: 416 - name: Mul418 value: 417 - name: Mul419 value: 418 - name: Mul420 value: 419 - name: Mul421 value: 420 - name: Mul422 value: 421 - name: Mul423 value: 422 - name: Mul424 value: 423 - name: Mul425 value: 424 - name: Mul426 value: 425 - name: Mul427 value: 426 - name: Mul428 value: 427 - name: Mul429 value: 428 - name: Mul430 value: 429 - name: Mul431 value: 430 - name: Mul432 value: 431 - name: Mul433 value: 432 - name: Mul434 value: 433 - name: Mul435 value: 434 - name: Mul436 value: 435 - name: Mul437 value: 436 - name: Mul438 value: 437 - name: Mul439 value: 438 - name: Mul440 value: 439 - name: Mul441 value: 440 - name: Mul442 value: 441 - name: Mul443 value: 442 - name: Mul444 value: 443 - name: Mul445 value: 444 - name: Mul446 value: 445 - name: Mul447 value: 446 - name: Mul448 value: 447 - name: Mul449 value: 448 - name: Mul450 value: 449 - name: Mul451 value: 450 - name: Mul452 value: 451 - name: Mul453 value: 452 - name: Mul454 value: 453 - name: Mul455 value: 454 - name: Mul456 value: 455 - name: Mul457 value: 456 - name: Mul458 value: 457 - name: Mul459 value: 458 - name: Mul460 value: 459 - name: Mul461 value: 460 - name: Mul462 value: 461 - name: Mul463 value: 462 - name: Mul464 value: 463 - name: Mul465 value: 464 - name: Mul466 value: 465 - name: Mul467 value: 466 - name: Mul468 value: 467 - name: Mul469 value: 468 - name: Mul470 value: 469 - name: Mul471 value: 470 - name: Mul472 value: 471 - name: Mul473 value: 472 - name: Mul474 value: 473 - name: Mul475 value: 474 - name: Mul476 value: 475 - name: Mul477 value: 476 - name: Mul478 value: 477 - name: Mul479 value: 478 - name: Mul480 value: 479 - name: Mul481 value: 480 - name: Mul482 value: 481 - name: Mul483 value: 482 - name: Mul484 value: 483 - name: Mul485 value: 484 - name: Mul486 value: 485 - name: Mul487 value: 486 - name: Mul488 value: 487 - name: Mul489 value: 488 - name: Mul490 value: 489 - name: Mul491 value: 490 - name: Mul492 value: 491 - name: Mul493 value: 492 - name: Mul494 value: 493 - name: Mul495 value: 494 - name: Mul496 value: 495 - name: Mul497 value: 496 - name: Mul498 value: 497 - name: Mul499 value: 498 - name: Mul500 value: 499 - name: Mul501 value: 500 - name: Mul502 value: 501 - name: Mul503 value: 502 - name: Mul504 value: 503 - name: Mul505 value: 504 - name: Mul506 value: 505 - name: Mul507 value: 506 - name: Mul508 value: 507 - name: Mul509 value: 508 - name: Mul510 value: 509 - name: Mul511 value: 510 - name: Mul512 value: 511 enum/PLLRGE: bit_size: 2 variants: - name: Range1 description: Frequency is between 1 and 2 MHz value: 0 - name: Range2 description: Frequency is between 2 and 4 MHz value: 1 - name: Range4 description: Frequency is between 4 and 8 MHz value: 2 - name: Range8 description: Frequency is between 8 and 16 MHz value: 3 enum/PLLSRC: bit_size: 2 variants: - name: DISABLE description: no clock send to DIVMx divider and PLLs (default after reset) value: 0 - name: HSI description: HSI selected as PLL clock (hsi_ck) value: 1 - name: CSI description: CSI selected as PLL clock (csi_ck) value: 2 - name: HSE description: HSE selected as PLL clock (hse_ck) value: 3 enum/PLLVCOSEL: bit_size: 1 variants: - name: WideVCO description: VCO frequency range 192 to 836 MHz value: 0 - name: MediumVCO description: VCO frequency range 150 to 420 MHz value: 1 enum/PPRE: bit_size: 3 variants: - name: Div1 description: rcc_pclk3 = rcc_hclk1 / 1 value: 0 - name: Div2 description: rcc_pclk3 = rcc_hclk1 / 2 value: 4 - name: Div4 description: rcc_pclk3 = rcc_hclk1 / 4 value: 5 - name: Div8 description: rcc_pclk3 = rcc_hclk1 / 8 value: 6 - name: Div16 description: rcc_pclk3 = rcc_hclk1 / 16 value: 7 enum/RNGSEL: bit_size: 2 variants: - name: HSI48 description: hsi48_ker_ck selected as kernel clock (default after reset) value: 0 - name: PLL1_Q description: pll1_q_ck selected as kernel clock value: 1 - name: LSE description: lse_ck selected as kernel clock value: 2 - name: LSI description: lsi_ker_ck selected as kernel clock value: 3 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE description: no clock (default after Backup domain reset) value: 0 - name: LSE description: LSE selected as RTC clock value: 1 - name: LSI description: LSI selected as RTC clock value: 2 - name: HSE_DIV_RTCPRE description: HSE divided by RTCPRE value selected as RTC clock value: 3 enum/SAISEL: bit_size: 3 variants: - name: PLL1_Q description: pll1_q_ck selected as kernel clock (default after reset) value: 0 - name: PLL2_P description: pll2_p_ck selected as kernel clock value: 1 - name: PLL3_P description: pll3_p_ck selected as kernel clock value: 2 - name: AUDIOCLK description: AUDIOCLK selected as kernel clock value: 3 - name: PER description: per_ck selected as kernel clock value: 4 enum/SDMMCSEL: bit_size: 1 variants: - name: PLL1_Q description: pll1_q_ck selected as kernel clock (default after reset) value: 0 - name: PLL2_R description: pll2_r_ck selected as kernel clock value: 1 enum/SPI1SEL: bit_size: 3 variants: - name: PLL1_Q description: pll1_q_ck selected as kernel clock (default after reset) value: 0 - name: PLL2_P description: pll2_p_ck selected as kernel clock value: 1 - name: PLL3_P description: pll3_p_ck selected as kernel clock value: 2 - name: AUDIOCLK description: AUDIOCLK selected as kernel clock value: 3 - name: PER description: per_ck selected as kernel clock value: 4 enum/SPI2SEL: bit_size: 3 variants: - name: PLL1_Q description: pll1_q_ck selected as kernel clock (default after reset) value: 0 - name: PLL2_P description: pll2_p_ck selected as kernel clock value: 1 - name: PLL3_P description: pll3_p_ck selected as kernel clock value: 2 - name: AUDIOCLK description: AUDIOCLK selected as kernel clock value: 3 - name: PER description: per_ck selected as kernel clock value: 4 enum/SPI3SEL: bit_size: 3 variants: - name: PLL1_Q description: pll1_q_ck selected as kernel clock (default after reset) value: 0 - name: PLL2_P description: pll2_p_ck selected as kernel clock value: 1 - name: PLL3_P description: pll3_p_ck selected as kernel clock value: 2 - name: AUDIOCLK description: AUDIOCLK selected as kernel clock value: 3 - name: PER description: per_ck selected as kernel clock value: 4 enum/SPI4SEL: bit_size: 3 variants: - name: PCLK2 description: rcc_pclk2 selected as kernel clock (default after reset) value: 0 - name: PLL2_Q description: pll2_q selected as peripheral clock value: 1 - name: PLL3_Q description: pll3_q selected as peripheral clock value: 2 - name: HSI description: hsi_ker selected as peripheral clock value: 3 - name: CSI description: csi_ker selected as peripheral clock value: 4 - name: HSE description: HSE selected as peripheral clock value: 5 enum/SPI5SEL: bit_size: 3 variants: - name: PCLK3 description: rcc_pclk3 selected as kernel clock (default after reset) value: 0 - name: PLL2_Q description: pll2_q selected as peripheral clock value: 1 - name: PLL3_Q description: pll3_q selected as peripheral clock value: 2 - name: HSI description: hsi_ker selected as peripheral clock value: 3 - name: CSI description: csi_ker selected as peripheral clock value: 4 - name: HSE description: HSE selected as peripheral clock value: 5 enum/SPI6SEL: bit_size: 3 variants: - name: PCLK2 description: rcc_pclk2 selected as peripheral clock value: 0 - name: PLL2_Q description: pll2_q selected as peripheral clock value: 1 - name: PLL3_Q description: pll3_q selected as peripheral clock value: 2 - name: HSI description: hsi_ker selected as peripheral clock value: 3 - name: CSI description: csi_ker selected as peripheral clock value: 4 - name: HSE description: HSE selected as peripheral clock value: 5 enum/SPRIV: bit_size: 1 variants: - name: Any description: Read and write to RCC secure functions can be done by privileged or unprivileged access. value: 0 - name: Privileged description: Read and write to RCC secure functions can be done by privileged access only value: 1 enum/STOPKERWUCK: bit_size: 1 variants: - name: HSI description: HSI selected as wakeup clock from system Stop (default after reset) value: 0 - name: CSI description: CSI selected as wakeup clock from system Stop value: 1 enum/STOPWUCK: bit_size: 1 variants: - name: CSI description: CSI selected as wakeup clock from system Stop value: 1 enum/SW: bit_size: 3 variants: - name: HSI description: HSI selected as system clock value: 0 - name: CSI description: CSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock value: 2 - name: PLL1_P description: PLL1 selected as system clock value: 3 enum/SYSTICKSEL: bit_size: 2 variants: - name: HCLK1_DIV_8 description: rcc_hclk/8 selected as clock source (default after reset) value: 0 - name: LSI description: lsi_ker_ck[1] selected as clock source value: 1 - name: LSE description: lse_ck[1] selected as clock source value: 2 enum/TIMICSEL: bit_size: 1 variants: - name: B_0x0 description: No internal clock available for timers input capture (default after reset) value: 0 - name: B_0x1 description: hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture value: 1 enum/TIMPRE: bit_size: 1 variants: - name: DefaultX2 description: The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) value: 0 - name: DefaultX4 description: The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 value: 1 enum/USART1SEL: bit_size: 3 variants: - name: PCLK2 description: rcc_pclk2 selected as peripheral clock value: 0 - name: PLL2_Q description: pll2_q selected as peripheral clock value: 1 - name: PLL3_Q description: pll3_q selected as peripheral clock value: 2 - name: HSI description: hsi_ker selected as peripheral clock value: 3 - name: CSI description: csi_ker selected as peripheral clock value: 4 - name: LSE description: LSE selected as peripheral clock value: 5 enum/USARTSEL: bit_size: 3 variants: - name: PCLK1 description: rcc_pclk1 selected as peripheral clock value: 0 - name: PLL2_Q description: pll2_q selected as peripheral clock value: 1 - name: PLL3_Q description: pll3_q selected as peripheral clock value: 2 - name: HSI description: hsi_ker selected as peripheral clock value: 3 - name: CSI description: csi_ker selected as peripheral clock value: 4 - name: LSE description: LSE selected as peripheral clock value: 5 enum/USBSEL: bit_size: 2 variants: - name: DISABLE description: Disable the kernel clock value: 0 - name: PLL1_Q description: pll1_q selected as peripheral clock value: 1 - name: PLL3_Q description: pll3_q selected as peripheral clock value: 2 - name: HSI48 description: HSI48 selected as peripheral clock value: 3