PA0: TIM2_CH1: 2 TIM2_ETR: 2 TSC_G1_IO1: 3 USART2_CTS: 1 PA1: EVENTOUT: 0 TIM2_CH2: 2 TSC_G1_IO2: 3 USART2_DE: 1 USART2_RTS: 1 PA10: I2C1_SDA: 4 TIM17_BKIN: 0 TIM1_CH3: 2 TSC_G4_IO2: 3 USART1_RX: 1 PA11: CAN_RX: 4 EVENTOUT: 0 I2C1_SCL: 5 TIM1_CH4: 2 TSC_G4_IO3: 3 USART1_CTS: 1 PA12: CAN_TX: 4 EVENTOUT: 0 I2C1_SDA: 5 TIM1_ETR: 2 TSC_G4_IO4: 3 USART1_DE: 1 USART1_RTS: 1 PA13: IR_OUT: 1 SYS_SWDIO: 0 USB_NOE: 2 PA14: SYS_SWCLK: 0 USART2_TX: 1 PA15: EVENTOUT: 3 I2S1_WS: 0 SPI1_NSS: 0 TIM2_CH1: 2 TIM2_ETR: 2 USART2_RX: 1 USB_NOE: 5 PA2: TIM2_CH3: 2 TSC_G1_IO3: 3 USART2_TX: 1 PA3: TIM2_CH4: 2 TSC_G1_IO4: 3 USART2_RX: 1 PA4: I2S1_WS: 0 SPI1_NSS: 0 TIM14_CH1: 4 TSC_G2_IO1: 3 USART2_CK: 1 USB_NOE: 2 PA5: CEC: 1 I2S1_CK: 0 SPI1_SCK: 0 TIM2_CH1: 2 TIM2_ETR: 2 TSC_G2_IO2: 3 PA6: EVENTOUT: 6 I2S1_MCK: 0 SPI1_MISO: 0 TIM16_CH1: 5 TIM1_BKIN: 2 TIM3_CH1: 1 TSC_G2_IO3: 3 PA7: EVENTOUT: 6 I2S1_SD: 0 SPI1_MOSI: 0 TIM14_CH1: 4 TIM17_CH1: 5 TIM1_CH1N: 2 TIM3_CH2: 1 TSC_G2_IO4: 3 PA8: CRS_SYNC: 4 EVENTOUT: 3 RCC_MCO: 0 TIM1_CH1: 2 USART1_CK: 1 PA9: I2C1_SCL: 4 RCC_MCO: 5 TIM1_CH2: 2 TSC_G4_IO1: 3 USART1_TX: 1 PB0: EVENTOUT: 0 TIM1_CH2N: 2 TIM3_CH3: 1 TSC_G3_IO2: 3 PB1: TIM14_CH1: 0 TIM1_CH3N: 2 TIM3_CH4: 1 TSC_G3_IO3: 3 PB10: CEC: 0 I2C1_SCL: 1 SPI2_SCK: 5 TIM2_CH3: 2 TSC_SYNC: 3 PB11: EVENTOUT: 0 I2C1_SDA: 1 TIM2_CH4: 2 PB12: EVENTOUT: 1 SPI2_NSS: 0 TIM1_BKIN: 2 PB13: I2C2_SCL: 5 SPI2_SCK: 0 TIM1_CH1N: 2 PB14: I2C2_SDA: 5 SPI2_MISO: 0 TIM1_CH2N: 2 PB15: SPI2_MOSI: 0 TIM1_CH3N: 2 PB2: TSC_G3_IO4: 3 PB3: EVENTOUT: 1 I2S1_CK: 0 SPI1_SCK: 0 TIM2_CH2: 2 TSC_G5_IO1: 3 PB4: EVENTOUT: 2 I2S1_MCK: 0 SPI1_MISO: 0 TIM17_BKIN: 5 TIM3_CH1: 1 TSC_G5_IO2: 3 PB5: I2C1_SMBA: 3 I2S1_SD: 0 SPI1_MOSI: 0 TIM16_BKIN: 2 TIM3_CH2: 1 PB6: I2C1_SCL: 1 TIM16_CH1N: 2 TSC_G5_IO3: 3 USART1_TX: 0 PB7: I2C1_SDA: 1 TIM17_CH1N: 2 TSC_G5_IO4: 3 USART1_RX: 0 PB8: CAN_RX: 4 CEC: 0 I2C1_SCL: 1 TIM16_CH1: 2 TSC_SYNC: 3 PB9: CAN_TX: 4 EVENTOUT: 3 I2C1_SDA: 1 IR_OUT: 0 SPI2_NSS: 5 TIM17_CH1: 2 PC13: {} PC14: {} PC15: {} PF0: CRS_SYNC: 0 I2C1_SDA: 1 PF1: I2C1_SCL: 1 PF11: {}