--- block/RCC: description: Reset and clock control items: - name: CR description: clock control register byte_offset: 0 fieldset: CR - name: PLLCFGR description: PLL configuration register byte_offset: 4 fieldset: PLLCFGR - name: CFGR description: clock configuration register byte_offset: 8 fieldset: CFGR - name: CIR description: clock interrupt register byte_offset: 12 fieldset: CIR - name: AHB1RSTR description: AHB1 peripheral reset register byte_offset: 16 fieldset: AHB1RSTR - name: AHB2RSTR description: AHB2 peripheral reset register byte_offset: 20 fieldset: AHB2RSTR - name: AHB3RSTR description: AHB3 peripheral reset register byte_offset: 24 fieldset: AHB3RSTR - name: APB1RSTR description: APB1 peripheral reset register byte_offset: 32 fieldset: APB1RSTR - name: APB2RSTR description: APB2 peripheral reset register byte_offset: 36 fieldset: APB2RSTR - name: AHB1ENR description: AHB1 peripheral clock register byte_offset: 48 fieldset: AHB1ENR - name: AHB2ENR description: AHB2 peripheral clock enable register byte_offset: 52 fieldset: AHB2ENR - name: AHB3ENR description: AHB3 peripheral clock enable register byte_offset: 56 fieldset: AHB3ENR - name: APB1ENR description: APB1 peripheral clock enable register byte_offset: 64 fieldset: APB1ENR - name: APB2ENR description: APB2 peripheral clock enable register byte_offset: 68 fieldset: APB2ENR - name: AHB1LPENR description: AHB1 peripheral clock enable in low power mode register byte_offset: 80 fieldset: AHB1LPENR - name: AHB2LPENR description: AHB2 peripheral clock enable in low power mode register byte_offset: 84 fieldset: AHB2LPENR - name: AHB3LPENR description: AHB3 peripheral clock enable in low power mode register byte_offset: 88 fieldset: AHB3LPENR - name: APB1LPENR description: APB1 peripheral clock enable in low power mode register byte_offset: 96 fieldset: APB1LPENR - name: APB2LPENR description: APB2 peripheral clock enabled in low power mode register byte_offset: 100 fieldset: APB2LPENR - name: BDCR description: Backup domain control register byte_offset: 112 fieldset: BDCR - name: CSR description: clock control & status register byte_offset: 116 fieldset: CSR - name: SSCGR description: spread spectrum clock generation register byte_offset: 128 fieldset: SSCGR - name: PLLI2SCFGR description: PLLI2S configuration register byte_offset: 132 fieldset: PLLI2SCFGR - name: PLLSAICFGR description: RCC PLL configuration register byte_offset: 136 fieldset: PLLSAICFGR - name: DCKCFGR description: RCC Dedicated Clock Configuration Register byte_offset: 140 fieldset: DCKCFGR - name: CKGATENR description: Clocks gated enable register byte_offset: 144 fieldset: CKGATENR - name: DCKCFGR2 description: DCKCFGR2 register byte_offset: 148 fieldset: DCKCFGR2 fieldset/AHB1ENR: description: AHB1 peripheral clock register fields: - name: GPIOAEN description: IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: IO port C clock enable bit_offset: 2 bit_size: 1 - name: GPIODEN description: IO port D clock enable bit_offset: 3 bit_size: 1 - name: GPIOEEN description: IO port E clock enable bit_offset: 4 bit_size: 1 - name: GPIOFEN description: IO port F clock enable bit_offset: 5 bit_size: 1 - name: GPIOGEN description: IO port G clock enable bit_offset: 6 bit_size: 1 - name: GPIOHEN description: IO port H clock enable bit_offset: 7 bit_size: 1 - name: GPIOIEN description: IO port I clock enable bit_offset: 8 bit_size: 1 - name: GPIOJEN description: IO port J clock enable bit_offset: 9 bit_size: 1 - name: GPIOKEN description: IO port K clock enable bit_offset: 10 bit_size: 1 - name: CRCEN description: CRC clock enable bit_offset: 12 bit_size: 1 - name: BKPSRAMEN description: Backup SRAM interface clock enable bit_offset: 18 bit_size: 1 - name: CCMDATARAMEN description: CCM data RAM clock enable bit_offset: 20 bit_size: 1 - name: DMA1EN description: DMA1 clock enable bit_offset: 21 bit_size: 1 - name: DMA2EN description: DMA2 clock enable bit_offset: 22 bit_size: 1 - name: DMA2DEN description: DMA2D clock enable bit_offset: 23 bit_size: 1 - name: ETHEN description: Ethernet MAC clock enable bit_offset: 25 bit_size: 1 - name: ETHTXEN description: Ethernet Transmission clock enable bit_offset: 26 bit_size: 1 - name: ETHRXEN description: Ethernet Reception clock enable bit_offset: 27 bit_size: 1 - name: ETHPTPEN description: Ethernet PTP clock enable bit_offset: 28 bit_size: 1 - name: USB_OTG_HSEN description: USB OTG HS clock enable bit_offset: 29 bit_size: 1 - name: USB_OTG_HSULPIEN description: USB OTG HSULPI clock enable bit_offset: 30 bit_size: 1 fieldset/AHB1LPENR: description: AHB1 peripheral clock enable in low power mode register fields: - name: GPIOALPEN description: IO port A clock enable during sleep mode bit_offset: 0 bit_size: 1 - name: GPIOBLPEN description: IO port B clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: GPIOCLPEN description: IO port C clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: GPIODLPEN description: IO port D clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: GPIOELPEN description: IO port E clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: GPIOFLPEN description: IO port F clock enable during Sleep mode bit_offset: 5 bit_size: 1 - name: GPIOGLPEN description: IO port G clock enable during Sleep mode bit_offset: 6 bit_size: 1 - name: GPIOHLPEN description: IO port H clock enable during Sleep mode bit_offset: 7 bit_size: 1 - name: GPIOILPEN description: IO port I clock enable during Sleep mode bit_offset: 8 bit_size: 1 - name: GPIOJLPEN description: IO port J clock enable during Sleep mode bit_offset: 9 bit_size: 1 - name: GPIOKLPEN description: IO port K clock enable during Sleep mode bit_offset: 10 bit_size: 1 - name: CRCLPEN description: CRC clock enable during Sleep mode bit_offset: 12 bit_size: 1 - name: FLASHLPEN description: Flash interface clock enable during Sleep mode bit_offset: 15 bit_size: 1 - name: SRAM1LPEN description: SRAM 1interface clock enable during Sleep mode bit_offset: 16 bit_size: 1 - name: SRAM2LPEN description: SRAM 2 interface clock enable during Sleep mode bit_offset: 17 bit_size: 1 - name: BKPSRAMLPEN description: Backup SRAM interface clock enable during Sleep mode bit_offset: 18 bit_size: 1 - name: SRAM3LPEN description: SRAM 3 interface clock enable during Sleep mode bit_offset: 19 bit_size: 1 - name: DMA1LPEN description: DMA1 clock enable during Sleep mode bit_offset: 21 bit_size: 1 - name: DMA2LPEN description: DMA2 clock enable during Sleep mode bit_offset: 22 bit_size: 1 - name: DMA2DLPEN description: DMA2D clock enable during Sleep mode bit_offset: 23 bit_size: 1 - name: ETHLPEN description: Ethernet MAC clock enable during Sleep mode bit_offset: 25 bit_size: 1 - name: ETHTXLPEN description: Ethernet transmission clock enable during Sleep mode bit_offset: 26 bit_size: 1 - name: ETHRXLPEN description: Ethernet reception clock enable during Sleep mode bit_offset: 27 bit_size: 1 - name: ETHPTPLPEN description: Ethernet PTP clock enable during Sleep mode bit_offset: 28 bit_size: 1 - name: USB_OTG_HSLPEN description: USB OTG HS clock enable during Sleep mode bit_offset: 29 bit_size: 1 - name: USB_OTG_HSULPILPEN description: USB OTG HS ULPI clock enable during Sleep mode bit_offset: 30 bit_size: 1 - name: RNGLPEN description: RNG clock enable during sleep mode bit_offset: 31 bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - name: GPIOARST description: IO port A reset bit_offset: 0 bit_size: 1 - name: GPIOBRST description: IO port B reset bit_offset: 1 bit_size: 1 - name: GPIOCRST description: IO port C reset bit_offset: 2 bit_size: 1 - name: GPIODRST description: IO port D reset bit_offset: 3 bit_size: 1 - name: GPIOERST description: IO port E reset bit_offset: 4 bit_size: 1 - name: GPIOFRST description: IO port F reset bit_offset: 5 bit_size: 1 - name: GPIOGRST description: IO port G reset bit_offset: 6 bit_size: 1 - name: GPIOHRST description: IO port H reset bit_offset: 7 bit_size: 1 - name: GPIOIRST description: IO port I reset bit_offset: 8 bit_size: 1 - name: GPIOJRST description: IO port J reset bit_offset: 9 bit_size: 1 - name: GPIOKRST description: IO port K reset bit_offset: 10 bit_size: 1 - name: CRCRST description: CRC reset bit_offset: 12 bit_size: 1 - name: DMA1RST description: DMA2 reset bit_offset: 21 bit_size: 1 - name: DMA2RST description: DMA2 reset bit_offset: 22 bit_size: 1 - name: DMA2DRST description: DMA2D reset bit_offset: 23 bit_size: 1 - name: ETHRST description: Ethernet MAC reset bit_offset: 25 bit_size: 1 - name: USB_OTG_HSRST description: USB OTG HS module reset bit_offset: 29 bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - name: DCMIEN description: Camera interface enable bit_offset: 0 bit_size: 1 - name: CRYPEN description: CRYP clock enable bit_offset: 4 bit_size: 1 - name: HASHEN description: Hash modules clock enable bit_offset: 5 bit_size: 1 - name: RNGEN description: Random number generator clock enable bit_offset: 6 bit_size: 1 - name: USB_OTG_FSEN description: USB OTG FS clock enable bit_offset: 7 bit_size: 1 fieldset/AHB2LPENR: description: AHB2 peripheral clock enable in low power mode register fields: - name: DCMILPEN description: Camera interface enable during Sleep mode bit_offset: 0 bit_size: 1 - name: FSMCLPEN description: Flexible memory controller module clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: QSPILPEN description: QUADSPI memory controller module clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: CRYPLPEN description: Cryptography modules clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: HASHLPEN description: Hash modules clock enable during Sleep mode bit_offset: 5 bit_size: 1 - name: RNGLPEN description: Random number generator clock enable during Sleep mode bit_offset: 6 bit_size: 1 - name: USB_OTG_FSLPEN description: USB OTG FS clock enable during Sleep mode bit_offset: 7 bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - name: DCMIRST description: Camera interface reset bit_offset: 0 bit_size: 1 - name: CRYPRST description: CRYP module reset bit_offset: 4 bit_size: 1 - name: HSAHRST description: Hash module reset bit_offset: 5 bit_size: 1 - name: RNGRST description: Random number generator module reset bit_offset: 6 bit_size: 1 - name: USB_OTG_FSRST description: USB OTG FS module reset bit_offset: 7 bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - name: FMCEN description: Flexible static memory controller module clock enable bit_offset: 0 bit_size: 1 - name: FSMCEN description: Flexible static memory controller module clock enable bit_offset: 0 bit_size: 1 - name: QUADSPIEN description: QUADSPI memory controller module clock enable bit_offset: 1 bit_size: 1 fieldset/AHB3LPENR: description: AHB3 peripheral clock enable in low power mode register fields: - name: FMCLPEN description: Flexible static memory controller module clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: FSMCLPEN description: Flexible static memory controller module clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: QSPILPEN description: QUADSPI memory controller module clock enable during Sleep mode bit_offset: 1 bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - name: FMCRST description: Flexible static memory controller module reset bit_offset: 0 bit_size: 1 - name: FSMCRST description: Flexible static memory controller module reset bit_offset: 0 bit_size: 1 - name: QSPIRST description: QUADSPI module reset bit_offset: 1 bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - name: TIM2EN description: TIM2 clock enable bit_offset: 0 bit_size: 1 - name: TIM3EN description: TIM3 clock enable bit_offset: 1 bit_size: 1 - name: TIM4EN description: TIM4 clock enable bit_offset: 2 bit_size: 1 - name: TIM5EN description: TIM5 clock enable bit_offset: 3 bit_size: 1 - name: TIM6EN description: TIM6 clock enable bit_offset: 4 bit_size: 1 - name: TIM7EN description: TIM7 clock enable bit_offset: 5 bit_size: 1 - name: TIM12EN description: TIM12 clock enable bit_offset: 6 bit_size: 1 - name: TIM13EN description: TIM13 clock enable bit_offset: 7 bit_size: 1 - name: TIM14EN description: TIM14 clock enable bit_offset: 8 bit_size: 1 - name: LPTIM1EN description: LPTIM1 clock enable bit_offset: 9 bit_size: 1 - name: RTCAPBEN description: RTC APB clock enable bit_offset: 10 bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN description: SPI2 clock enable bit_offset: 14 bit_size: 1 - name: SPI3EN description: SPI3 clock enable bit_offset: 15 bit_size: 1 - name: SPDIFEN description: SPDIF-IN clock enable bit_offset: 16 bit_size: 1 - name: USART2EN description: USART 2 clock enable bit_offset: 17 bit_size: 1 - name: USART3EN description: USART3 clock enable bit_offset: 18 bit_size: 1 - name: UART4EN description: UART4 clock enable bit_offset: 19 bit_size: 1 - name: UART5EN description: UART5 clock enable bit_offset: 20 bit_size: 1 - name: I2C1EN description: I2C1 clock enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: I2C2 clock enable bit_offset: 22 bit_size: 1 - name: I2C3EN description: I2C3 clock enable bit_offset: 23 bit_size: 1 - name: FMPI2C1EN description: FMPI2C1 clock enable bit_offset: 24 bit_size: 1 - name: CAN1EN description: CAN 1 clock enable bit_offset: 25 bit_size: 1 - name: CAN2EN description: CAN 2 clock enable bit_offset: 26 bit_size: 1 - name: CAN3EN description: CAN 3 clock enable bit_offset: 27 bit_size: 1 - name: CECEN description: CEC interface clock enable bit_offset: 27 bit_size: 1 - name: PWREN description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: DACEN description: DAC interface clock enable bit_offset: 29 bit_size: 1 - name: UART7EN description: UART7 clock enable bit_offset: 30 bit_size: 1 - name: UART8EN description: UART8 clock enable bit_offset: 31 bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - name: TIM2LPEN description: TIM2 clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: TIM3LPEN description: TIM3 clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: TIM4LPEN description: TIM4 clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: TIM5LPEN description: TIM5 clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: TIM6LPEN description: TIM6 clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: TIM7LPEN description: TIM7 clock enable during Sleep mode bit_offset: 5 bit_size: 1 - name: TIM12LPEN description: TIM12 clock enable during Sleep mode bit_offset: 6 bit_size: 1 - name: TIM13LPEN description: TIM13 clock enable during Sleep mode bit_offset: 7 bit_size: 1 - name: TIM14LPEN description: TIM14 clock enable during Sleep mode bit_offset: 8 bit_size: 1 - name: LPTIM1LPEN description: LPTIM1 clock enable during sleep mode bit_offset: 9 bit_size: 1 - name: RTCAPBLPEN description: RTC APB clock enable during sleep mode bit_offset: 10 bit_size: 1 - name: WWDGLPEN description: Window watchdog clock enable during Sleep mode bit_offset: 11 bit_size: 1 - name: SPI2LPEN description: SPI2 clock enable during Sleep mode bit_offset: 14 bit_size: 1 - name: SPI3LPEN description: SPI3 clock enable during Sleep mode bit_offset: 15 bit_size: 1 - name: SPDIFLPEN description: SPDIF clock enable during Sleep mode bit_offset: 16 bit_size: 1 - name: USART2LPEN description: USART2 clock enable during Sleep mode bit_offset: 17 bit_size: 1 - name: USART3LPEN description: USART3 clock enable during Sleep mode bit_offset: 18 bit_size: 1 - name: UART4LPEN description: UART4 clock enable during Sleep mode bit_offset: 19 bit_size: 1 - name: UART5LPEN description: UART5 clock enable during Sleep mode bit_offset: 20 bit_size: 1 - name: I2C1LPEN description: I2C1 clock enable during Sleep mode bit_offset: 21 bit_size: 1 - name: I2C2LPEN description: I2C2 clock enable during Sleep mode bit_offset: 22 bit_size: 1 - name: I2C3LPEN description: I2C3 clock enable during Sleep mode bit_offset: 23 bit_size: 1 - name: FMPI2C1LPEN description: FMPI2C1 clock enable during Sleep bit_offset: 24 bit_size: 1 - name: CAN1LPEN description: CAN 1 clock enable during Sleep mode bit_offset: 25 bit_size: 1 - name: CAN2LPEN description: CAN 2 clock enable during Sleep mode bit_offset: 26 bit_size: 1 - name: CAN3LPEN description: CAN3 clock enable during Sleep mode bit_offset: 27 bit_size: 1 - name: CECLPEN description: CEC clock enable during Sleep mode bit_offset: 27 bit_size: 1 - name: PWRLPEN description: Power interface clock enable during Sleep mode bit_offset: 28 bit_size: 1 - name: DACLPEN description: DAC interface clock enable during Sleep mode bit_offset: 29 bit_size: 1 - name: UART7LPEN description: UART7 clock enable during Sleep mode bit_offset: 30 bit_size: 1 - name: UART8LPEN description: UART8 clock enable during Sleep mode bit_offset: 31 bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - name: TIM2RST description: TIM2 reset bit_offset: 0 bit_size: 1 - name: TIM3RST description: TIM3 reset bit_offset: 1 bit_size: 1 - name: TIM4RST description: TIM4 reset bit_offset: 2 bit_size: 1 - name: TIM5RST description: TIM5 reset bit_offset: 3 bit_size: 1 - name: TIM6RST description: TIM6 reset bit_offset: 4 bit_size: 1 - name: TIM7RST description: TIM7 reset bit_offset: 5 bit_size: 1 - name: TIM12RST description: TIM12 reset bit_offset: 6 bit_size: 1 - name: TIM13RST description: TIM13 reset bit_offset: 7 bit_size: 1 - name: TIM14RST description: TIM14 reset bit_offset: 8 bit_size: 1 - name: LPTIM1RST description: LPTIM1 reset bit_offset: 9 bit_size: 1 - name: WWDGRST description: Window watchdog reset bit_offset: 11 bit_size: 1 - name: SPI2RST description: SPI 2 reset bit_offset: 14 bit_size: 1 - name: SPI3RST description: SPI 3 reset bit_offset: 15 bit_size: 1 - name: SPDIFRST description: SPDIF-IN reset bit_offset: 16 bit_size: 1 - name: USART2RST description: USART 2 reset bit_offset: 17 bit_size: 1 - name: USART3RST description: USART 3 reset bit_offset: 18 bit_size: 1 - name: UART4RST description: UART 4 reset bit_offset: 19 bit_size: 1 - name: UART5RST description: UART 5 reset bit_offset: 20 bit_size: 1 - name: I2C1RST description: I2C 1 reset bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C 2 reset bit_offset: 22 bit_size: 1 - name: I2C3RST description: I2C3 reset bit_offset: 23 bit_size: 1 - name: FMPI2C1RST description: FMPI2C1 reset bit_offset: 24 bit_size: 1 - name: CAN1RST description: CAN1 reset bit_offset: 25 bit_size: 1 - name: CAN2RST description: CAN2 reset bit_offset: 26 bit_size: 1 - name: CAN3RST description: CAN 3 reset bit_offset: 27 bit_size: 1 - name: PWRRST description: Power interface reset bit_offset: 28 bit_size: 1 - name: DACRST description: DAC reset bit_offset: 29 bit_size: 1 - name: UART7RST description: UART 7 reset bit_offset: 30 bit_size: 1 - name: UART8RST description: UART 8 reset bit_offset: 31 bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - name: TIM1EN description: TIM1 clock enable bit_offset: 0 bit_size: 1 - name: TIM8EN description: TIM8 clock enable bit_offset: 1 bit_size: 1 - name: USART1EN description: USART1 clock enable bit_offset: 4 bit_size: 1 - name: USART6EN description: USART6 clock enable bit_offset: 5 bit_size: 1 - name: UART9EN description: UART9 clock enable bit_offset: 6 bit_size: 1 - name: UART10EN description: UART10 clock enable bit_offset: 7 bit_size: 1 - name: ADC1EN description: ADC1 clock enable bit_offset: 8 bit_size: 1 - name: ADC2EN description: ADC2 clock enable bit_offset: 9 bit_size: 1 - name: ADC3EN description: ADC3 clock enable bit_offset: 10 bit_size: 1 - name: SDIOEN description: SDIO clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: SPI1 clock enable bit_offset: 12 bit_size: 1 - name: SPI4EN description: SPI4 clock enable bit_offset: 13 bit_size: 1 - name: SYSCFGEN description: System configuration controller clock enable bit_offset: 14 bit_size: 1 - name: EXTITEN description: EXTI ans external IT clock enable bit_offset: 15 bit_size: 1 - name: TIM9EN description: TIM9 clock enable bit_offset: 16 bit_size: 1 - name: TIM10EN description: TIM10 clock enable bit_offset: 17 bit_size: 1 - name: TIM11EN description: TIM11 clock enable bit_offset: 18 bit_size: 1 - name: SPI5EN description: SPI5 clock enable bit_offset: 20 bit_size: 1 - name: SPI6EN description: SPI6 clock enable bit_offset: 21 bit_size: 1 - name: SAI1EN description: SAI 1 clock enable bit_offset: 22 bit_size: 1 - name: SAI2EN description: SAI2 clock enable bit_offset: 23 bit_size: 1 - name: DFSDMEN description: DFSDMEN bit_offset: 24 bit_size: 1 - name: DFSDM2EN description: DFSDM2 clock enable bit_offset: 25 bit_size: 1 - name: LTDCEN description: LTDC clock enable bit_offset: 26 bit_size: 1 - name: DSIEN description: DSI clocks enable bit_offset: 27 bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enabled in low power mode register fields: - name: TIM1LPEN description: TIM1 clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: TIM8LPEN description: TIM8 clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: USART1LPEN description: USART1 clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: USART6LPEN description: USART6 clock enable during Sleep mode bit_offset: 5 bit_size: 1 - name: UART9LPEN description: UART9 clock enable during Sleep mode bit_offset: 6 bit_size: 1 - name: UART10LPEN description: UART10 clock enable during Sleep mode bit_offset: 7 bit_size: 1 - name: ADC1LPEN description: ADC1 clock enable during Sleep mode bit_offset: 8 bit_size: 1 - name: ADC2LPEN description: ADC2 clock enable during Sleep mode bit_offset: 9 bit_size: 1 - name: ADC3LPEN description: ADC 3 clock enable during Sleep mode bit_offset: 10 bit_size: 1 - name: SDIOLPEN description: SDIO clock enable during Sleep mode bit_offset: 11 bit_size: 1 - name: SPI1LPEN description: SPI 1 clock enable during Sleep mode bit_offset: 12 bit_size: 1 - name: SPI4LPEN description: SPI4 clock enable during Sleep mode bit_offset: 13 bit_size: 1 - name: SYSCFGLPEN description: System configuration controller clock enable during Sleep mode bit_offset: 14 bit_size: 1 - name: EXTITLPEN description: EXTI and External IT clock enable during sleep mode bit_offset: 15 bit_size: 1 - name: TIM9LPEN description: TIM9 clock enable during sleep mode bit_offset: 16 bit_size: 1 - name: TIM10LPEN description: TIM10 clock enable during Sleep mode bit_offset: 17 bit_size: 1 - name: TIM11LPEN description: TIM11 clock enable during Sleep mode bit_offset: 18 bit_size: 1 - name: SPI5LPEN description: SPI5 clock enable during Sleep mode bit_offset: 20 bit_size: 1 - name: SPI6LPEN description: SPI 6 clock enable during Sleep mode bit_offset: 21 bit_size: 1 - name: SAI1LPEN description: SAI1 clock enable during Sleep mode bit_offset: 22 bit_size: 1 - name: SAI2LPEN description: SAI2 clock enable bit_offset: 23 bit_size: 1 - name: DFSDMLPEN description: DFSDMLPEN bit_offset: 24 bit_size: 1 - name: DFSDM2LPEN description: DFSDM2 clock enable during Sleep mode bit_offset: 25 bit_size: 1 - name: LTDCLPEN description: LTDC clock enable during Sleep mode bit_offset: 26 bit_size: 1 - name: DSILPEN description: DSI clocks enable during Sleep mode bit_offset: 27 bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: TIM1RST description: TIM1 reset bit_offset: 0 bit_size: 1 - name: TIM8RST description: TIM8 reset bit_offset: 1 bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 4 bit_size: 1 - name: USART6RST description: USART6 reset bit_offset: 5 bit_size: 1 - name: UART9RST description: UART9 reset bit_offset: 6 bit_size: 1 - name: UART10RST description: UART10 reset bit_offset: 7 bit_size: 1 - name: ADCRST description: ADC interface reset (common to all ADCs) bit_offset: 8 bit_size: 1 - name: SDIORST description: SDIO reset bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI 1 reset bit_offset: 12 bit_size: 1 - name: SPI4RST description: SPI4 reset bit_offset: 13 bit_size: 1 - name: SYSCFGRST description: System configuration controller reset bit_offset: 14 bit_size: 1 - name: TIM9RST description: TIM9 reset bit_offset: 16 bit_size: 1 - name: TIM10RST description: TIM10 reset bit_offset: 17 bit_size: 1 - name: TIM11RST description: TIM11 reset bit_offset: 18 bit_size: 1 - name: SPI5RST description: SPI5 reset bit_offset: 20 bit_size: 1 - name: SPI6RST description: SPI6 reset bit_offset: 21 bit_size: 1 - name: SAI1RST description: SAI1 reset bit_offset: 22 bit_size: 1 - name: SAI2RST description: SAI2 reset bit_offset: 23 bit_size: 1 - name: DFSDMRST description: DFSDMRST bit_offset: 24 bit_size: 1 - name: DFSDM2RST description: DFSDM2 reset bit_offset: 25 bit_size: 1 - name: LTDCRST description: LTDC reset bit_offset: 26 bit_size: 1 - name: DSIRST description: DSI host reset bit_offset: 27 bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - name: LSEON description: External low-speed oscillator enable bit_offset: 0 bit_size: 1 - name: LSERDY description: External low-speed oscillator ready bit_offset: 1 bit_size: 1 - name: LSEBYP description: External low-speed oscillator bypass bit_offset: 2 bit_size: 1 - name: LSEMOD description: External low-speed oscillator bypass bit_offset: 3 bit_size: 1 enum: LSEMOD - name: RTCSEL description: RTC clock source selection bit_offset: 8 bit_size: 2 enum: RTCSEL - name: RTCEN description: RTC clock enable bit_offset: 15 bit_size: 1 - name: BDRST description: Backup domain software reset bit_offset: 16 bit_size: 1 fieldset/CFGR: description: clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 enum_read: SWSR - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 enum: HPRE - name: MCO1EN description: MCO output enable bit_offset: 8 bit_size: 1 - name: MCO2EN description: MCO output enable bit_offset: 9 bit_size: 1 - name: PPRE1 description: APB Low speed prescaler (APB1) bit_offset: 10 bit_size: 3 enum: PPRE - name: PPRE2 description: APB high-speed prescaler (APB2) bit_offset: 13 bit_size: 3 enum: PPRE - name: RTCPRE description: HSE division factor for RTC clock bit_offset: 16 bit_size: 5 - name: MCO1 description: Microcontroller clock output 1 bit_offset: 21 bit_size: 2 enum: MCO1 - name: I2SSRC description: I2S clock selection bit_offset: 23 bit_size: 1 enum: ISSRC - name: MCO1PRE description: MCO1 prescaler bit_offset: 24 bit_size: 3 enum: MCOPRE - name: MCO2PRE description: MCO2 prescaler bit_offset: 27 bit_size: 3 enum: MCOPRE - name: MCO2 description: Microcontroller clock output 2 bit_offset: 30 bit_size: 2 enum: MCO2 fieldset/CIR: description: clock interrupt register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 - name: PLLRDYF description: Main PLL (PLL) ready interrupt flag bit_offset: 4 bit_size: 1 - name: PLLI2SRDYF description: PLLI2S ready interrupt flag bit_offset: 5 bit_size: 1 - name: PLLSAIRDYF description: PLLSAI ready interrupt flag bit_offset: 6 bit_size: 1 - name: CSSF description: Clock security system interrupt flag bit_offset: 7 bit_size: 1 - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 8 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 9 bit_size: 1 - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 10 bit_size: 1 - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 11 bit_size: 1 - name: PLLRDYIE description: Main PLL (PLL) ready interrupt enable bit_offset: 12 bit_size: 1 - name: PLLI2SRDYIE description: PLLI2S ready interrupt enable bit_offset: 13 bit_size: 1 - name: PLLSAIRDYIE description: PLLSAI Ready Interrupt Enable bit_offset: 14 bit_size: 1 - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 16 bit_size: 1 - name: LSERDYC description: LSE ready interrupt clear bit_offset: 17 bit_size: 1 - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 18 bit_size: 1 - name: HSERDYC description: HSE ready interrupt clear bit_offset: 19 bit_size: 1 - name: PLLRDYC description: Main PLL(PLL) ready interrupt clear bit_offset: 20 bit_size: 1 - name: PLLI2SRDYC description: PLLI2S ready interrupt clear bit_offset: 21 bit_size: 1 - name: PLLSAIRDYC description: PLLSAI Ready Interrupt Clear bit_offset: 22 bit_size: 1 - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 fieldset/CKGATENR: description: clocks gated enable register fields: - name: AHB2APB1_CKEN description: AHB to APB1 Bridge clock enable bit_offset: 0 bit_size: 1 - name: AHB2APB2_CKEN description: AHB to APB2 Bridge clock enable bit_offset: 1 bit_size: 1 - name: CM4DBG_CKEN description: Cortex M4 ETM clock enable bit_offset: 2 bit_size: 1 - name: SPARE_CKEN description: Spare clock enable bit_offset: 3 bit_size: 1 - name: SRAM_CKEN description: SRAM controller clock enable bit_offset: 4 bit_size: 1 - name: FLASH_CKEN description: Flash interface clock enable bit_offset: 5 bit_size: 1 - name: RCC_CKEN description: RCC clock enable bit_offset: 6 bit_size: 1 - name: EVTCL_CKEN description: EVTCL clock enable bit_offset: 7 bit_size: 1 fieldset/CR: description: clock control register fields: - name: HSION description: Internal high-speed clock enable bit_offset: 0 bit_size: 1 - name: HSIRDY description: Internal high-speed clock ready flag bit_offset: 1 bit_size: 1 - name: HSITRIM description: Internal high-speed clock trimming bit_offset: 3 bit_size: 5 - name: HSICAL description: Internal high-speed clock calibration bit_offset: 8 bit_size: 8 - name: HSEON description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 - name: CSSON description: Clock security system enable bit_offset: 19 bit_size: 1 - name: PLLON description: Main PLL (PLL) enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: Main PLL (PLL) clock ready flag bit_offset: 25 bit_size: 1 - name: PLLI2SON description: PLLI2S enable bit_offset: 26 bit_size: 1 - name: PLLI2SRDY description: PLLI2S clock ready flag bit_offset: 27 bit_size: 1 - name: PLLSAION description: PLLSAI enable bit_offset: 28 bit_size: 1 - name: PLLSAIRDY description: PLLSAI clock ready flag bit_offset: 29 bit_size: 1 fieldset/CSR: description: clock control & status register fields: - name: LSION description: Internal low-speed oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - name: RMVF description: Remove reset flag bit_offset: 24 bit_size: 1 - name: BORRSTF description: BOR reset flag bit_offset: 25 bit_size: 1 - name: PADRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - name: WDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 fieldset/DCKCFGR: description: Dedicated Clock Configuration Register fields: - name: PLLI2SDIVQ description: PLLI2S division factor for SAI1 clock bit_offset: 0 bit_size: 5 enum: PLLISDIVQ - name: PLLI2SDIVR description: PLLI2S division factor for SAI1 A/B clock bit_offset: 0 bit_size: 5 enum: PLLISDIVR - name: PLLDIVR description: PLL division factor for SAI1 A/B clock bit_offset: 8 bit_size: 5 enum: PLLDIVR - name: PLLSAIDIVQ description: PLLSAI division factor for SAI1 clock bit_offset: 8 bit_size: 5 enum: PLLSAIDIVQ - name: CKDFSDM2ASEL description: DFSDM2 audio clock selection bit_offset: 14 bit_size: 1 enum: CKDFSDMASEL - name: CKDFSDM1ASEL description: DFSDM1 audio clock selection bit_offset: 15 bit_size: 5 enum: CKDFSDMASEL - name: PLLSAIDIVR description: division factor for LCD_CLK bit_offset: 16 bit_size: 2 enum: PLLSAIDIVR - name: SAI1ASRC description: SAI1-A clock source selection bit_offset: 20 bit_size: 2 enum: SAIASRC - name: SAI1SRC description: SAI1 clock source selection bit_offset: 20 bit_size: 2 enum: SAI1SRC - name: SAI1BSRC description: SAI1-B clock source selection bit_offset: 22 bit_size: 2 enum: SAIBSRC - name: SAI2SRC description: SAI2 clock source selection bit_offset: 22 bit_size: 2 enum: SAI2SRC - name: TIMPRE description: Timers clocks prescalers selection bit_offset: 24 bit_size: 1 enum: TIMPRE - name: I2S1SRC description: I2S APB1 clocks source selection (I2S2/3) bit_offset: 25 bit_size: 2 enum: I2S1SRC - name: I2SSRC description: I2SSRC bit_offset: 25 bit_size: 2 enum: ISSRC - name: CK48MSEL description: 48 MHz clock source selection bit_offset: 27 bit_size: 1 enum: CKMSEL - name: I2S2SRC description: I2S APB2 clocks source selection (I2S1/4/5) bit_offset: 27 bit_size: 2 enum: I2S1SRC - name: SDIOSEL description: SDIO clock source selection bit_offset: 28 bit_size: 1 enum: SDIOSEL - name: DSISEL description: DSI clock source selection bit_offset: 29 bit_size: 1 enum: DSISEL - name: CKDFSDM1SEL description: DFSDM1 Kernel clock selection bit_offset: 31 bit_size: 1 enum: CKDFSDMSEL fieldset/DCKCFGR2: description: dedicated clocks configuration register 2 fields: - name: FMPI2C1SEL description: FMPI2C1 kernel clock source selection bit_offset: 22 bit_size: 2 enum: FMPICSEL - name: CECSEL description: HDMI CEC clock source selection bit_offset: 26 bit_size: 1 enum: CECSEL - name: CK48MSEL description: SDIO/USB clock selection bit_offset: 27 bit_size: 1 enum: CKMSEL - name: SDIOSEL description: SDIO clock selection bit_offset: 28 bit_size: 1 enum: SDIOSEL - name: SPDIFRXSEL description: SPDIF clock selection bit_offset: 29 bit_size: 1 enum: SPDIFRXSEL - name: LPTIM1SEL description: LPTIM1SEL bit_offset: 30 bit_size: 2 enum: LPTIMSEL fieldset/PLLCFGR: description: PLL configuration register fields: - name: PLLM description: Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock bit_offset: 0 bit_size: 6 - name: PLLN description: Main PLL (PLL) multiplication factor for VCO bit_offset: 6 bit_size: 9 - name: PLLP description: Main PLL (PLL) division factor for main system clock bit_offset: 16 bit_size: 2 enum: PLLP - name: PLLSRC description: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source bit_offset: 22 bit_size: 1 enum: PLLSRC - name: PLLQ description: "Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks" bit_offset: 24 bit_size: 4 - name: PLLR description: PLL division factor for I2S and System clocks bit_offset: 28 bit_size: 3 fieldset/PLLI2SCFGR: description: PLLI2S configuration register fields: - name: PLLI2SM description: Division factor for the audio PLL (PLLI2S) input clock bit_offset: 0 bit_size: 6 - name: PLLI2SN description: PLLI2S multiplication factor for VCO bit_offset: 6 bit_size: 9 - name: PLLI2SP description: PLLI2S division factor for SPDIF-IN clock bit_offset: 16 bit_size: 2 enum: PLLISP - name: PLLI2SSRC description: PLLI2S entry clock source bit_offset: 22 bit_size: 1 enum: PLLISSRC - name: PLLI2SQ description: PLLI2S division factor for USB OTG FS/SDIO/RNG clock bit_offset: 24 bit_size: 4 - name: PLLI2SR description: PLLI2S division factor for I2S clocks bit_offset: 28 bit_size: 3 fieldset/PLLSAICFGR: description: PLL configuration register fields: - name: PLLSAIM description: Division factor for audio PLLSAI input clock bit_offset: 0 bit_size: 6 - name: PLLSAIN description: PLLSAI division factor for VCO bit_offset: 6 bit_size: 9 - name: PLLSAIP description: PLLSAI division factor for 48 MHz clock bit_offset: 16 bit_size: 2 enum: PLLSAIP - name: PLLSAIQ description: PLLSAI division factor for SAI1 clock bit_offset: 24 bit_size: 4 - name: PLLSAIR description: PLLSAI division factor for LCD clock bit_offset: 28 bit_size: 3 fieldset/SSCGR: description: spread spectrum clock generation register fields: - name: MODPER description: Modulation period bit_offset: 0 bit_size: 13 - name: INCSTEP description: Incrementation step bit_offset: 13 bit_size: 15 - name: SPREADSEL description: Spread Select bit_offset: 30 bit_size: 1 enum: SPREADSEL - name: SSCGEN description: Spread spectrum modulation enable bit_offset: 31 bit_size: 1 enum/CECSEL: bit_size: 1 variants: - name: LSE description: LSE clock is selected as HDMI-CEC clock value: 0 - name: HSI_Div488 description: HSI divided by 488 clock is selected as HDMI-CEC clock value: 1 enum/CKDFSDMASEL: bit_size: 1 variants: - name: I2S1 description: CK_I2S_APB1 selected as audio clock value: 0 - name: I2S2 description: CK_I2S_APB2 selected as audio clock value: 1 enum/CKDFSDMSEL: bit_size: 1 variants: - name: APB2 description: APB2 clock used as Kernel clock value: 0 - name: SYSCLK description: System clock used as Kernel clock value: 1 enum/CKMSEL: bit_size: 1 variants: - name: PLL description: 48MHz clock from PLL is selected value: 0 - name: PLLSAI description: 48MHz clock from PLLSAI is selected value: 1 enum/DSISEL: bit_size: 1 variants: - name: DSI_PHY description: DSI-PHY used as DSI byte lane clock source (usual case) value: 0 - name: PLLR description: "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)" value: 1 enum/FMPICSEL: bit_size: 2 variants: - name: APB description: APB clock selected as I2C clock value: 0 - name: SYSCLK description: System clock selected as I2C clock value: 1 - name: HSI description: HSI clock selected as I2C clock value: 2 enum/HPRE: bit_size: 4 variants: - name: Div1 description: SYSCLK not divided value: 0 - name: Div2 description: SYSCLK divided by 2 value: 8 - name: Div4 description: SYSCLK divided by 4 value: 9 - name: Div8 description: SYSCLK divided by 8 value: 10 - name: Div16 description: SYSCLK divided by 16 value: 11 - name: Div64 description: SYSCLK divided by 64 value: 12 - name: Div128 description: SYSCLK divided by 128 value: 13 - name: Div256 description: SYSCLK divided by 256 value: 14 - name: Div512 description: SYSCLK divided by 512 value: 15 enum/I2S1SRC: bit_size: 2 variants: - name: PLLI2SR description: I2Sx clock frequency = f(PLLI2S_R) value: 0 - name: I2S_CKIN description: I2Sx clock frequency = I2S_CKIN Alternate function input frequency value: 1 - name: PLLR description: I2Sx clock frequency = f(PLL_R) value: 2 - name: HSI_HSE description: "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])" value: 3 enum/I2SSRC: bit_size: 1 variants: - name: PLLI2S description: PLLI2S clock used as I2S clock source value: 0 - name: CKIN description: External clock mapped on the I2S_CKIN pin used as I2S clock source value: 1 enum/ISSRC: bit_size: 1 variants: - name: PLLI2S description: PLLI2S clock used as I2S clock source value: 0 - name: CKIN description: External clock mapped on the I2S_CKIN pin used as I2S clock source value: 1 enum/LPTIMSEL: bit_size: 2 variants: - name: APB1 description: APB1 clock (PCLK1) selected as LPTILM1 clock value: 0 - name: LSI description: LSI clock is selected as LPTILM1 clock value: 1 - name: HSI description: HSI clock is selected as LPTILM1 clock value: 2 - name: LSE description: LSE clock is selected as LPTILM1 clock value: 3 enum/LSEMOD: bit_size: 1 variants: - name: Low description: LSE oscillator low power mode selection value: 0 - name: High description: LSE oscillator high drive mode selection value: 1 enum/MCO1: bit_size: 2 variants: - name: HSI description: HSI clock selected value: 0 - name: LSE description: LSE oscillator selected value: 1 - name: HSE description: HSE oscillator clock selected value: 2 - name: PLL description: PLL clock selected value: 3 enum/MCO2: bit_size: 2 variants: - name: SYSCLK description: System clock (SYSCLK) selected value: 0 - name: PLLI2S description: PLLI2S clock selected value: 1 - name: HSE description: HSE oscillator clock selected value: 2 - name: PLL description: PLL clock selected value: 3 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: No division value: 0 - name: Div2 description: Division by 2 value: 4 - name: Div3 description: Division by 3 value: 5 - name: Div4 description: Division by 4 value: 6 - name: Div5 description: Division by 5 value: 7 enum/PLLDIVR: bit_size: 5 variants: - name: Div1 description: PLLSAIDIVQ = /1 value: 0 - name: Div2 description: PLLSAIDIVQ = /2 value: 1 - name: Div3 description: PLLSAIDIVQ = /3 value: 2 - name: Div4 description: PLLSAIDIVQ = /4 value: 3 - name: Div5 description: PLLSAIDIVQ = /5 value: 4 - name: Div6 description: PLLSAIDIVQ = /6 value: 5 - name: Div7 description: PLLSAIDIVQ = /7 value: 6 - name: Div8 description: PLLSAIDIVQ = /8 value: 7 - name: Div9 description: PLLSAIDIVQ = /9 value: 8 - name: Div10 description: PLLSAIDIVQ = /10 value: 9 - name: Div11 description: PLLSAIDIVQ = /11 value: 10 - name: Div12 description: PLLSAIDIVQ = /12 value: 11 - name: Div13 description: PLLSAIDIVQ = /13 value: 12 - name: Div14 description: PLLSAIDIVQ = /14 value: 13 - name: Div15 description: PLLSAIDIVQ = /15 value: 14 - name: Div16 description: PLLSAIDIVQ = /16 value: 15 - name: Div17 description: PLLSAIDIVQ = /17 value: 16 - name: Div18 description: PLLSAIDIVQ = /18 value: 17 - name: Div19 description: PLLSAIDIVQ = /19 value: 18 - name: Div20 description: PLLSAIDIVQ = /20 value: 19 - name: Div21 description: PLLSAIDIVQ = /21 value: 20 - name: Div22 description: PLLSAIDIVQ = /22 value: 21 - name: Div23 description: PLLSAIDIVQ = /23 value: 22 - name: Div24 description: PLLSAIDIVQ = /24 value: 23 - name: Div25 description: PLLSAIDIVQ = /25 value: 24 - name: Div26 description: PLLSAIDIVQ = /26 value: 25 - name: Div27 description: PLLSAIDIVQ = /27 value: 26 - name: Div28 description: PLLSAIDIVQ = /28 value: 27 - name: Div29 description: PLLSAIDIVQ = /29 value: 28 - name: Div30 description: PLLSAIDIVQ = /30 value: 29 - name: Div31 description: PLLSAIDIVQ = /31 value: 30 - name: Div32 description: PLLSAIDIVQ = /32 value: 31 enum/PLLISDIVQ: bit_size: 5 variants: - name: Div1 description: PLLI2SDIVQ = /1 value: 0 - name: Div2 description: PLLI2SDIVQ = /2 value: 1 - name: Div3 description: PLLI2SDIVQ = /3 value: 2 - name: Div4 description: PLLI2SDIVQ = /4 value: 3 - name: Div5 description: PLLI2SDIVQ = /5 value: 4 - name: Div6 description: PLLI2SDIVQ = /6 value: 5 - name: Div7 description: PLLI2SDIVQ = /7 value: 6 - name: Div8 description: PLLI2SDIVQ = /8 value: 7 - name: Div9 description: PLLI2SDIVQ = /9 value: 8 - name: Div10 description: PLLI2SDIVQ = /10 value: 9 - name: Div11 description: PLLI2SDIVQ = /11 value: 10 - name: Div12 description: PLLI2SDIVQ = /12 value: 11 - name: Div13 description: PLLI2SDIVQ = /13 value: 12 - name: Div14 description: PLLI2SDIVQ = /14 value: 13 - name: Div15 description: PLLI2SDIVQ = /15 value: 14 - name: Div16 description: PLLI2SDIVQ = /16 value: 15 - name: Div17 description: PLLI2SDIVQ = /17 value: 16 - name: Div18 description: PLLI2SDIVQ = /18 value: 17 - name: Div19 description: PLLI2SDIVQ = /19 value: 18 - name: Div20 description: PLLI2SDIVQ = /20 value: 19 - name: Div21 description: PLLI2SDIVQ = /21 value: 20 - name: Div22 description: PLLI2SDIVQ = /22 value: 21 - name: Div23 description: PLLI2SDIVQ = /23 value: 22 - name: Div24 description: PLLI2SDIVQ = /24 value: 23 - name: Div25 description: PLLI2SDIVQ = /25 value: 24 - name: Div26 description: PLLI2SDIVQ = /26 value: 25 - name: Div27 description: PLLI2SDIVQ = /27 value: 26 - name: Div28 description: PLLI2SDIVQ = /28 value: 27 - name: Div29 description: PLLI2SDIVQ = /29 value: 28 - name: Div30 description: PLLI2SDIVQ = /30 value: 29 - name: Div31 description: PLLI2SDIVQ = /31 value: 30 - name: Div32 description: PLLI2SDIVQ = /32 value: 31 enum/PLLISDIVR: bit_size: 5 variants: - name: Div1 description: PLLI2SDIVQ = /1 value: 0 - name: Div2 description: PLLI2SDIVQ = /2 value: 1 - name: Div3 description: PLLI2SDIVQ = /3 value: 2 - name: Div4 description: PLLI2SDIVQ = /4 value: 3 - name: Div5 description: PLLI2SDIVQ = /5 value: 4 - name: Div6 description: PLLI2SDIVQ = /6 value: 5 - name: Div7 description: PLLI2SDIVQ = /7 value: 6 - name: Div8 description: PLLI2SDIVQ = /8 value: 7 - name: Div9 description: PLLI2SDIVQ = /9 value: 8 - name: Div10 description: PLLI2SDIVQ = /10 value: 9 - name: Div11 description: PLLI2SDIVQ = /11 value: 10 - name: Div12 description: PLLI2SDIVQ = /12 value: 11 - name: Div13 description: PLLI2SDIVQ = /13 value: 12 - name: Div14 description: PLLI2SDIVQ = /14 value: 13 - name: Div15 description: PLLI2SDIVQ = /15 value: 14 - name: Div16 description: PLLI2SDIVQ = /16 value: 15 - name: Div17 description: PLLI2SDIVQ = /17 value: 16 - name: Div18 description: PLLI2SDIVQ = /18 value: 17 - name: Div19 description: PLLI2SDIVQ = /19 value: 18 - name: Div20 description: PLLI2SDIVQ = /20 value: 19 - name: Div21 description: PLLI2SDIVQ = /21 value: 20 - name: Div22 description: PLLI2SDIVQ = /22 value: 21 - name: Div23 description: PLLI2SDIVQ = /23 value: 22 - name: Div24 description: PLLI2SDIVQ = /24 value: 23 - name: Div25 description: PLLI2SDIVQ = /25 value: 24 - name: Div26 description: PLLI2SDIVQ = /26 value: 25 - name: Div27 description: PLLI2SDIVQ = /27 value: 26 - name: Div28 description: PLLI2SDIVQ = /28 value: 27 - name: Div29 description: PLLI2SDIVQ = /29 value: 28 - name: Div30 description: PLLI2SDIVQ = /30 value: 29 - name: Div31 description: PLLI2SDIVQ = /31 value: 30 - name: Div32 description: PLLI2SDIVQ = /32 value: 31 enum/PLLISP: bit_size: 2 variants: - name: Div2 description: PLL*P=2 value: 0 - name: Div4 description: PLL*P=4 value: 1 - name: Div6 description: PLL*P=6 value: 2 - name: Div8 description: PLL*P=8 value: 3 enum/PLLISSRC: bit_size: 1 variants: - name: HSE_HSI description: HSE or HSI depending on PLLSRC of PLLCFGR value: 0 - name: External description: External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry value: 1 enum/PLLP: bit_size: 2 variants: - name: Div2 description: PLLP=2 value: 0 - name: Div4 description: PLLP=4 value: 1 - name: Div6 description: PLLP=6 value: 2 - name: Div8 description: PLLP=8 value: 3 enum/PLLSAIDIVQ: bit_size: 5 variants: - name: Div1 description: PLLSAIDIVQ = /1 value: 0 - name: Div2 description: PLLSAIDIVQ = /2 value: 1 - name: Div3 description: PLLSAIDIVQ = /3 value: 2 - name: Div4 description: PLLSAIDIVQ = /4 value: 3 - name: Div5 description: PLLSAIDIVQ = /5 value: 4 - name: Div6 description: PLLSAIDIVQ = /6 value: 5 - name: Div7 description: PLLSAIDIVQ = /7 value: 6 - name: Div8 description: PLLSAIDIVQ = /8 value: 7 - name: Div9 description: PLLSAIDIVQ = /9 value: 8 - name: Div10 description: PLLSAIDIVQ = /10 value: 9 - name: Div11 description: PLLSAIDIVQ = /11 value: 10 - name: Div12 description: PLLSAIDIVQ = /12 value: 11 - name: Div13 description: PLLSAIDIVQ = /13 value: 12 - name: Div14 description: PLLSAIDIVQ = /14 value: 13 - name: Div15 description: PLLSAIDIVQ = /15 value: 14 - name: Div16 description: PLLSAIDIVQ = /16 value: 15 - name: Div17 description: PLLSAIDIVQ = /17 value: 16 - name: Div18 description: PLLSAIDIVQ = /18 value: 17 - name: Div19 description: PLLSAIDIVQ = /19 value: 18 - name: Div20 description: PLLSAIDIVQ = /20 value: 19 - name: Div21 description: PLLSAIDIVQ = /21 value: 20 - name: Div22 description: PLLSAIDIVQ = /22 value: 21 - name: Div23 description: PLLSAIDIVQ = /23 value: 22 - name: Div24 description: PLLSAIDIVQ = /24 value: 23 - name: Div25 description: PLLSAIDIVQ = /25 value: 24 - name: Div26 description: PLLSAIDIVQ = /26 value: 25 - name: Div27 description: PLLSAIDIVQ = /27 value: 26 - name: Div28 description: PLLSAIDIVQ = /28 value: 27 - name: Div29 description: PLLSAIDIVQ = /29 value: 28 - name: Div30 description: PLLSAIDIVQ = /30 value: 29 - name: Div31 description: PLLSAIDIVQ = /31 value: 30 - name: Div32 description: PLLSAIDIVQ = /32 value: 31 enum/PLLSAIDIVR: bit_size: 2 variants: - name: Div2 description: PLLSAIDIVR = /2 value: 0 - name: Div4 description: PLLSAIDIVR = /4 value: 1 - name: Div8 description: PLLSAIDIVR = /8 value: 2 - name: Div16 description: PLLSAIDIVR = /16 value: 3 enum/PLLSAIP: bit_size: 2 variants: - name: Div2 description: PLL*P=2 value: 0 - name: Div4 description: PLL*P=4 value: 1 - name: Div6 description: PLL*P=6 value: 2 - name: Div8 description: PLL*P=8 value: 3 enum/PLLSRC: bit_size: 1 variants: - name: HSI description: HSI clock selected as PLL and PLLI2S clock entry value: 0 - name: HSE description: HSE oscillator clock selected as PLL and PLLI2S clock entry value: 1 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK divided by 2 value: 4 - name: Div4 description: HCLK divided by 4 value: 5 - name: Div8 description: HCLK divided by 8 value: 6 - name: Div16 description: HCLK divided by 16 value: 7 enum/RTCSEL: bit_size: 2 variants: - name: NoClock description: No clock value: 0 - name: LSE description: LSE oscillator clock used as RTC clock value: 1 - name: LSI description: LSI oscillator clock used as RTC clock value: 2 - name: HSE description: HSE oscillator clock divided by a prescaler used as RTC clock value: 3 enum/SAI1SRC: bit_size: 2 variants: - name: PLLSAI description: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ value: 0 - name: PLLI2S description: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ value: 1 - name: PLLR description: SAI1 clock frequency = f(PLL_R) value: 2 - name: I2S_CKIN description: I2S_CKIN Alternate function input frequency value: 3 enum/SAI2SRC: bit_size: 2 variants: - name: PLLSAI description: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ value: 0 - name: PLLI2S description: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ value: 1 - name: PLLR description: SAI2 clock frequency = f(PLL_R) value: 2 - name: HSI_HSE description: SAI2 clock frequency = Alternate function input frequency value: 3 enum/SAIASRC: bit_size: 2 variants: - name: PLLSAI description: SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ value: 0 - name: PLLI2S description: SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ value: 1 - name: I2S_CKIN description: SAI1-A clock frequency = Alternate function input frequency value: 2 enum/SAIBSRC: bit_size: 2 variants: - name: PLLSAI description: SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ value: 0 - name: PLLI2S description: SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ value: 1 - name: I2S_CKIN description: SAI1-B clock frequency = Alternate function input frequency value: 2 enum/SDIOSEL: bit_size: 1 variants: - name: CK48M description: 48 MHz clock is selected as SD clock value: 0 - name: SYSCLK description: System clock is selected as SD clock value: 1 enum/SPDIFRXSEL: bit_size: 1 variants: - name: PLL description: SPDIF-Rx clock from PLL is selected value: 0 - name: PLLI2S description: SPDIF-Rx clock from PLLI2S is selected value: 1 enum/SPREADSEL: bit_size: 1 variants: - name: Center description: Center spread value: 0 - name: Down description: Down spread value: 1 enum/SW: bit_size: 2 variants: - name: HSI description: HSI selected as system clock value: 0 - name: HSE description: HSE selected as system clock value: 1 - name: PLL description: PLL selected as system clock value: 2 enum/SWSR: bit_size: 2 variants: - name: HSI description: HSI oscillator used as system clock value: 0 - name: HSE description: HSE oscillator used as system clock value: 1 - name: PLL description: PLL used as system clock value: 2 enum/TIMPRE: bit_size: 1 variants: - name: Mul2 description: "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx" value: 0 - name: Mul4 description: "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx" value: 1