--- block/PWR: description: Power control items: - name: PMCR description: PWR power mode control register byte_offset: 0 fieldset: PMCR - name: PMSR description: PWR status register byte_offset: 4 fieldset: PMSR - name: VOSCR description: PWR voltage scaling control register byte_offset: 16 fieldset: VOSCR - name: VOSSR description: PWR voltage scaling status register byte_offset: 20 fieldset: VOSSR - name: BDCR description: PWR Backup domain control register byte_offset: 32 fieldset: BDCR - name: DBPCR description: PWR Backup domain control register byte_offset: 36 fieldset: DBPCR - name: BDSR description: PWR Backup domain status register byte_offset: 40 fieldset: BDSR - name: UCPDR description: PWR USB Type-C power delivery register byte_offset: 44 fieldset: UCPDR - name: SCCR description: PWR supply configuration control register byte_offset: 48 fieldset: SCCR - name: VMCR description: PWR voltage monitor control register byte_offset: 52 fieldset: VMCR - name: USBSCR description: PWR USB supply control register byte_offset: 56 fieldset: USBSCR - name: VMSR description: PWR voltage monitor status register byte_offset: 60 fieldset: VMSR - name: WUSCR description: PWR wakeup status clear register byte_offset: 64 fieldset: WUSCR - name: WUSR description: PWR wakeup status register byte_offset: 68 fieldset: WUSR - name: WUCR description: PWR wakeup configuration register byte_offset: 72 fieldset: WUCR - name: IORETR description: PWR I/O retention register byte_offset: 80 fieldset: IORETR - name: SECCFGR description: PWR security configuration register byte_offset: 256 fieldset: SECCFGR - name: PRIVCFGR description: PWR privilege configuration register byte_offset: 260 fieldset: PRIVCFGR fieldset/BDCR: description: PWR Backup domain control register fields: - name: BREN description: "Backup RAM retention in Standby and VBAT modes\r When this bit set, the backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled.\r If BREN is cleared, the backup regulator is switched off. The backup RAM can still be used in \tRun and Stop modes. However its content is lost in Standby and VBAT modes.\r If BREN is set, the application must wait till the backup regulator ready flag (BRRDY) is set to indicate that the data written into the SRAM is maintained in Standby and VBAT modes." bit_offset: 0 bit_size: 1 - name: MONEN description: Backup domain voltage and temperature monitoring enable bit_offset: 1 bit_size: 1 - name: VBE description: "VBAT charging enable\r Note: Reset only by POR,." bit_offset: 8 bit_size: 1 - name: VBRS description: VBAT charging resistor selection bit_offset: 9 bit_size: 1 enum: VBRS fieldset/BDSR: description: PWR Backup domain status register fields: - name: BRRDY description: "backup regulator ready\r This bit is set by hardware to indicate that the backup regulator is ready." bit_offset: 16 bit_size: 1 - name: VBATL description: VBAT level monitoring versus low threshold bit_offset: 20 bit_size: 1 - name: VBATH description: VBAT level monitoring versus high threshold bit_offset: 21 bit_size: 1 - name: TEMPL description: temperature level monitoring versus low threshold bit_offset: 22 bit_size: 1 - name: TEMPH description: temperature level monitoring versus high threshold bit_offset: 23 bit_size: 1 fieldset/DBPCR: description: PWR Backup domain control register fields: - name: DBP description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write \taccess. This bit must be set to enable write access to these registers." bit_offset: 0 bit_size: 1 fieldset/IORETR: description: PWR I/O retention register fields: - name: IORETEN description: "IO retention enable:\r When entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode. \r Note: the IO state is not retained if the DBG_STANDBY bit is set in DBGMCU_CR register." bit_offset: 0 bit_size: 1 - name: JTAGIORETEN description: "IO retention enable for JTAG IOs\r when entering into standby mode, the output is sampled, and apply to the output IO during the standby power mode" bit_offset: 16 bit_size: 1 fieldset/PMCR: description: PWR power mode control register fields: - name: LPMS description: "low-power mode selection\r This bit defines the Deepsleep mode." bit_offset: 0 bit_size: 1 - name: SVOS description: "system Stop mode voltage scaling selection\r These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." bit_offset: 2 bit_size: 2 enum: SVOS - name: CSSF description: "clear Standby and Stop flags (always read as 0)\r This bit is cleared to 0 by hardware." bit_offset: 7 bit_size: 1 - name: FLPS description: "Flash memory low-power mode in Stop mode\r This bit is used to obtain the best trade-off between low-power consumption and restart time when exiting from Stop mode.\r When it is set, the Flash memory enters low-power mode when the CPU domain is in Stop mode.\r Note: When system enters stop mode with SVOS5 enabled, Flash memory is automatically forced in low-power mode." bit_offset: 9 bit_size: 1 - name: BOOSTE description: "analog switch VBOOST control\r This bit enables the booster to guarantee the analog switch AC performance when the VDD supply voltage is below 2.7 V (reduction of the total harmonic distortion to have the same switch performance over the full supply voltage range) The VDD supply voltage can be monitored through the PVD and the PLS bits." bit_offset: 12 bit_size: 1 - name: AVD_READY description: "analog voltage ready\r This bit is only used when the analog switch boost needs to be enabled (see BOOSTE bit).\r It must be set by software when the expected VDDA analog supply level is available.\r The correct analog supply level is indicated by the AVDO bit (PWR_VMSR register) after setting the AVDEN bit (PWR_VMCR register) and selecting the supply level to be monitored \t(ALS bits)." bit_offset: 13 bit_size: 1 - name: ETHERNETSO description: ETHERNET RAM shut-off in Stop mode. bit_offset: 16 bit_size: 1 - name: SRAM3SO description: AHB SRAM3 shut-off in Stop mode. bit_offset: 23 bit_size: 1 - name: SRAM2_16SO description: AHB SRAM2 16-Kbyte shut-off in Stop mode. bit_offset: 24 bit_size: 1 - name: SRAM2_48SO description: AHB SRAM2 48-Kbyte shut-off in Stop mode. bit_offset: 25 bit_size: 1 - name: SRAM1SO description: AHB SRAM1 shut-off in Stop mode bit_offset: 26 bit_size: 1 fieldset/PMSR: description: PWR status register fields: - name: STOPF description: "Stop flag\r This bit is set by hardware and cleared only by any reset or by setting the CSSF bit." bit_offset: 5 bit_size: 1 - name: SBF description: "System standby flag\r This bit is set by hardware and cleared only by a POR or by setting the CSSF bit." bit_offset: 6 bit_size: 1 fieldset/PRIVCFGR: description: PWR privilege configuration register fields: - name: SPRIV description: "PWR secure functions privilege configuration\r Set and reset by software. This bit can be written only by a secure privileged access." bit_offset: 0 bit_size: 1 enum: PRIV - name: NSPRIV description: "PWR non-secure functions privilege configuration\r Set and reset by software. This bit can be written only by privileged access, secure or non-secure." bit_offset: 1 bit_size: 1 enum: PRIV fieldset/SCCR: description: PWR supply configuration control register fields: - name: BYPASS description: power management unit bypass bit_offset: 0 bit_size: 1 - name: LDOEN description: "LDO enable \r The value is set by hardware when the package uses the LDO regulator." bit_offset: 8 bit_size: 1 - name: SMPSEN description: "SMPS enable \r The value is set by hardware when the package uses the SMPS regulator." bit_offset: 9 bit_size: 1 fieldset/SECCFGR: description: PWR security configuration register fields: - name: WUP1SEC description: WUPx secure protection bit_offset: 0 bit_size: 1 enum: SEC - name: WUP2SEC description: WUPx secure protection bit_offset: 1 bit_size: 1 enum: SEC - name: WUP3SEC description: WUPx secure protection bit_offset: 2 bit_size: 1 enum: SEC - name: WUP4SEC description: WUPx secure protection bit_offset: 3 bit_size: 1 enum: SEC - name: WUP5SEC description: WUPx secure protection bit_offset: 4 bit_size: 1 enum: SEC - name: WUP6SEC description: WUPx secure protection bit_offset: 5 bit_size: 1 enum: SEC - name: WUP7SEC description: WUPx secure protection bit_offset: 6 bit_size: 1 enum: SEC - name: WUP8SEC description: WUPx secure protection bit_offset: 7 bit_size: 1 enum: SEC - name: RETSEC description: retention secure protection bit_offset: 11 bit_size: 1 enum: SEC - name: LPMSEC description: low-power modes secure protection bit_offset: 12 bit_size: 1 enum: SEC - name: SCMSEC description: supply configuration and monitoring secure protection. bit_offset: 13 bit_size: 1 enum: SEC - name: VBSEC description: backup domain secure protection bit_offset: 14 bit_size: 1 enum: SEC - name: VUSBSEC description: voltage USB secure protection bit_offset: 15 bit_size: 1 enum: SEC fieldset/UCPDR: description: PWR USB Type-C power delivery register fields: - name: UCPD_DBDIS description: "USB Type-C and power delivery dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all case, either to stop this pull-down or to hand over control to the UCPD (which should therefore be initialized before doing the disable)." bit_offset: 0 bit_size: 1 - name: UCPD_STBY description: "USB Type-c and Power delivery Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode. This bit must be written to 1 just before entering Standby mode when using UCPD, and it must be written to 0 after exiting the standby mode and before writing any UCPD register." bit_offset: 1 bit_size: 1 fieldset/USBSCR: description: PWR USB supply control register fields: - name: USB33DEN description: VDDUSB voltage level detector enable bit_offset: 24 bit_size: 1 - name: USB33SV description: "independent USB supply valid\r This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose. Setting this bit is mandatory to use the USBFS peripheral. If VDDUSB is not always present in the application, the VDDUSB voltage monitor can be used to determine whether this supply is ready or not." bit_offset: 25 bit_size: 1 fieldset/VMCR: description: PWR voltage monitor control register fields: - name: PVDE description: PVD enable bit_offset: 0 bit_size: 1 - name: PLS description: "programmable voltage detector (PVD) level selection\r These bits select the voltage threshold detected by the PVD." bit_offset: 1 bit_size: 3 enum: PLS - name: AVDEN description: peripheral voltage monitor on VDDA enable bit_offset: 8 bit_size: 1 - name: ALS description: "analog voltage detector (AVD) level selection\r These bits select the voltage threshold detected by the AVD." bit_offset: 9 bit_size: 2 enum: ALS fieldset/VMSR: description: PWR voltage monitor status register fields: - name: AVDO description: "analog voltage detector output on VDDA\r This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit.\r Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after standby or reset until the AVDEN bit is set." bit_offset: 19 bit_size: 1 enum: AVDO - name: VDDIO2RDY description: "voltage detector output on VDDIO2\r This bit is set and cleared by hardware." bit_offset: 20 bit_size: 1 - name: PVDO description: "programmable voltage detect output\r This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit.\r Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." bit_offset: 22 bit_size: 1 enum: PVDO - name: USB33RDY description: VDDUSB ready bit_offset: 24 bit_size: 1 fieldset/VOSCR: description: PWR voltage scaling control register fields: - name: VOS description: "voltage scaling selection according to performance\r These bits control the VCORE voltage level and allow to obtain the best trade-off between power consumption and performance:\r - In bypass mode, these bits must also be set according to the external provided core voltage level and related performance.\r - When increasing the performance, the voltage scaling must be changed before increasing the system frequency.\r - When decreasing performance, the system frequency must first be decreased before changing the voltage scaling." bit_offset: 4 bit_size: 2 enum: VOS fieldset/VOSSR: description: PWR voltage scaling status register fields: - name: VOSRDY description: Ready bit for VCORE voltage scaling output selection. bit_offset: 3 bit_size: 1 - name: ACTVOSRDY description: Voltage level ready for currently used VOS bit_offset: 13 bit_size: 1 - name: ACTVOS description: "voltage output scaling currently applied to VCORE\r This field provides the last VOS value." bit_offset: 14 bit_size: 2 enum: ACTVOS fieldset/WUCR: description: PWR wakeup configuration register fields: - name: WUPPUPD description: "wakeup pin pull configuration for WKUPx\r These bits define the I/O pad pull configuration used when WUPENx = 1. The associated GPIO port pull configuration must be set to the same value or to 00. The wakeup pin pull configuration is kept in Standby mode." bit_offset: 16 bit_size: 2 array: len: 8 stride: 2 enum: WUPPUPD - name: WUPEN description: "enable wakeup pin WUPx\r These bits are set and cleared by software.\r Note: an additional wakeup event is detected if WUPx pin is enabled (by setting the WUPENx bit) when WUPx pin level is already high when WUPPx selects rising edge, or low when WUPPx selects falling edge." bit_offset: 0 bit_size: 1 array: len: 8 stride: 1 - name: WUPP description: "wakeup pin polarity bit for WUPx\r These bits define the polarity used for event detection on WUPx external wakeup pin." bit_offset: 8 bit_size: 1 array: len: 8 stride: 1 enum: WUPP fieldset/WUSCR: description: PWR wakeup status clear register fields: - name: CWUF description: "clear wakeup pin flag for WUFx\r These bits are always read as 0." bit_offset: 0 bit_size: 1 array: len: 8 stride: 1 fieldset/WUSR: description: PWR wakeup status register fields: - name: WUF description: "wakeup pin WUFx flag\r This bit is set by hardware and cleared only by a RESET pin or by setting the CWUFx bit in PWR_WUSCR register." bit_offset: 0 bit_size: 1 array: len: 8 stride: 1 enum/ACTVOS: bit_size: 2 variants: - name: B_0x0 description: VOS3 (lowest power) value: 0 - name: B_0x1 description: VOS2 value: 1 - name: B_0x2 description: VOS1 value: 2 - name: B_0x3 description: VOS0 (highest frequency) value: 3 enum/ALS: bit_size: 2 variants: - name: B_0x0 description: 1.7 V value: 0 - name: B_0x1 description: 2.1 V value: 1 - name: B_0x2 description: 2.5 V value: 2 - name: B_0x3 description: 2.8 V value: 3 enum/AVDO: bit_size: 1 variants: - name: B_0x0 description: "VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits." value: 0 - name: B_0x1 description: "VDDA is lower than the AVD threshold selected with the ALS[2:0] bits." value: 1 enum/PLS: bit_size: 3 variants: - name: B_0x0 description: 1.95 V value: 0 - name: B_0x1 description: 2.1 V value: 1 - name: B_0x2 description: 2.25 V value: 2 - name: B_0x3 description: 2.4 V value: 3 - name: B_0x4 description: 2.55 V value: 4 - name: B_0x5 description: 2.7 V value: 5 - name: B_0x6 description: 2.85 V value: 6 - name: B_0x7 description: PVD_IN pin value: 7 enum/PRIV: bit_size: 1 variants: - name: B_0x0 description: Read and write to PWR secure functions can be done by privileged or unprivileged access. value: 0 - name: B_0x1 description: Read and write to PWR secure functions can be done by privileged access only. value: 1 enum/PVDO: bit_size: 1 variants: - name: B_0x0 description: "VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits." value: 0 - name: B_0x1 description: "VDD is lower than the PVD threshold selected through the PLS[2:0] bits." value: 1 enum/SEC: bit_size: 1 variants: - name: B_0x0 description: PWR_SCCR and PWR_VMCR can be read and written with secure or non-secure access. value: 0 - name: B_0x1 description: PWR_SCCR and PWR_VMCR can be read and written only with secure access. value: 1 enum/SVOS: bit_size: 2 variants: - name: B_0x0 description: reserved value: 0 - name: B_0x1 description: SVOS5 scale 5 value: 1 - name: B_0x2 description: SVOS4 scale 4 value: 2 - name: B_0x3 description: SVOS3 scale 3 (default). value: 3 enum/VBRS: bit_size: 1 variants: - name: B_0x0 description: Charge VBAT through a 5 kΩ resistor. value: 0 - name: B_0x1 description: Charge VBAT through a 1.5 kΩ resistor. value: 1 enum/VOS: bit_size: 2 variants: - name: B_0x0 description: scale 3 (default) value: 0 - name: B_0x1 description: scale 2 value: 1 - name: B_0x2 description: scale 1 value: 2 - name: B_0x3 description: scale 0 value: 3 enum/WUPP: bit_size: 1 variants: - name: B_0x0 description: detection on high level (rising edge) value: 0 - name: B_0x1 description: detection on low level (falling edge) value: 1 enum/WUPPUPD: bit_size: 2 variants: - name: B_0x0 description: no pull-up value: 0 - name: B_0x1 description: pull-up value: 1 - name: B_0x2 description: pull-down value: 2 - name: B_0x3 description: reserved value: 3