block/RCC: description: Reset and clock controller items: - name: CR description: RCC clock control register byte_offset: 0 fieldset: CR - name: HSICFGR description: RCC HSI calibration register byte_offset: 16 fieldset: HSICFGR - name: CRRCR description: RCC clock recovery RC register byte_offset: 20 fieldset: CRRCR - name: CSICFGR description: RCC CSI calibration register byte_offset: 24 fieldset: CSICFGR - name: CFGR description: RCC clock configuration register byte_offset: 28 fieldset: CFGR - name: CFGR2 description: RCC CPU domain clock configuration register 2 byte_offset: 32 fieldset: CFGR2 - name: PLLCFGR description: RCC PLL clock source selection register array: len: 2 stride: 4 byte_offset: 40 fieldset: PLLCFGR - name: PLLDIVR description: RCC PLL1 dividers register array: len: 2 stride: 8 byte_offset: 52 fieldset: PLLDIVR - name: PLLFRACR description: RCC PLL1 fractional divider register array: len: 2 stride: 8 byte_offset: 56 fieldset: PLLFRACR - name: CIER description: RCC clock source interrupt enable register byte_offset: 80 fieldset: CIER - name: CIFR description: RCC clock source interrupt flag register byte_offset: 84 fieldset: CIFR - name: CICR description: RCC clock source interrupt clear register byte_offset: 88 fieldset: CICR - name: AHB1RSTR description: RCC AHB1 reset register byte_offset: 96 fieldset: AHB1RSTR - name: AHB2RSTR description: RCC AHB2 peripheral reset register byte_offset: 100 fieldset: AHB2RSTR - name: APB1LRSTR description: RCC APB1 peripheral low reset register byte_offset: 116 fieldset: APB1LRSTR - name: APB1HRSTR description: RCC APB1 peripheral high reset register byte_offset: 120 fieldset: APB1HRSTR - name: APB2RSTR description: RCC APB2 peripheral reset register byte_offset: 124 fieldset: APB2RSTR - name: APB3RSTR description: RCC APB3 peripheral reset register byte_offset: 128 fieldset: APB3RSTR - name: AHB1ENR description: RCC AHB1 peripherals clock register byte_offset: 136 fieldset: AHB1ENR - name: AHB2ENR description: RCC AHB2 peripheral clock register byte_offset: 140 fieldset: AHB2ENR - name: APB1LENR description: RCC APB1 peripheral clock register byte_offset: 156 fieldset: APB1LENR - name: APB1HENR description: RCC APB1 peripheral clock register byte_offset: 160 fieldset: APB1HENR - name: APB2ENR description: RCC APB2 peripheral clock register byte_offset: 164 fieldset: APB2ENR - name: APB3ENR description: RCC APB3 peripheral clock register byte_offset: 168 fieldset: APB3ENR - name: AHB1LPENR description: RCC AHB1 sleep clock register byte_offset: 176 fieldset: AHB1LPENR - name: AHB2LPENR description: RCC AHB2 sleep clock register byte_offset: 180 fieldset: AHB2LPENR - name: APB1LLPENR description: RCC APB1 sleep clock register byte_offset: 196 fieldset: APB1LLPENR - name: APB1HLPENR description: RCC APB1 sleep clock register byte_offset: 200 fieldset: APB1HLPENR - name: APB2LPENR description: RCC APB2 sleep clock register byte_offset: 204 fieldset: APB2LPENR - name: APB3LPENR description: RCC APB3 sleep clock register byte_offset: 208 fieldset: APB3LPENR - name: CCIPR1 description: RCC kernel clock configuration register byte_offset: 216 fieldset: CCIPR1 - name: CCIPR2 description: RCC kernel clock configuration register byte_offset: 220 fieldset: CCIPR2 - name: CCIPR3 description: RCC kernel clock configuration register byte_offset: 224 fieldset: CCIPR3 - name: CCIPR4 description: RCC kernel clock configuration register byte_offset: 228 fieldset: CCIPR4 - name: CCIPR5 description: RCC kernel clock configuration register byte_offset: 232 fieldset: CCIPR5 - name: BDCR description: RCC Backup domain control register byte_offset: 240 fieldset: BDCR - name: RSR description: RCC reset status register byte_offset: 244 fieldset: RSR fieldset/AHB1ENR: description: RCC AHB1 peripherals clock register fields: - name: GPDMA1EN description: "GPDMA1 clock enable\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPDMA2EN description: "GPDMA2 clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: FLITFEN description: "Flash interface clock enable\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: CRCEN description: "CRC clock enable\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: RAMCFGEN description: "RAMCFG clock enable\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: BKPRAMEN description: "BKPRAM clock enable\r Set and reset by software" bit_offset: 28 bit_size: 1 - name: SRAM1EN description: "SRAM1 clock enable\r Set and reset by software." bit_offset: 31 bit_size: 1 fieldset/AHB1LPENR: description: RCC AHB1 sleep clock register fields: - name: GPDMA1LPEN description: "GPDMA1 clock enable during sleep mode\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPDMA2LPEN description: "GPDMA2 clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: FLITFLPEN description: "Flash interface (FLITF) clock enable during sleep mode\r Set and reset by software." bit_offset: 8 bit_size: 1 - name: CRCLPEN description: "CRC clock enable during sleep mode\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: RAMCFGLPEN description: "RAMCFG clock enable during sleep mode\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: BKPRAMLPEN description: "BKPRAM clock enable during sleep mode\r Set and reset by software" bit_offset: 28 bit_size: 1 - name: ICACHELPEN description: "ICACHE clock enable during sleep mode\r Set and reset by software" bit_offset: 29 bit_size: 1 - name: SRAM1LPEN description: "SRAM1 clock enable during sleep mode\r Set and reset by software" bit_offset: 31 bit_size: 1 fieldset/AHB1RSTR: description: RCC AHB1 reset register fields: - name: GPDMA1RST description: "GPDMA1 block reset\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPDMA2RST description: "GPDMA2 block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: CRCRST description: CRC block reset Set and reset by software. bit_offset: 12 bit_size: 1 - name: RAMCFGRST description: "RAMCFG block reset\r Set and reset by software." bit_offset: 17 bit_size: 1 fieldset/AHB2ENR: description: RCC AHB2 peripheral clock register fields: - name: GPIOAEN description: "GPIOA clock enable\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPIOBEN description: "GPIOB clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: GPIOCEN description: "GPIOC clock enable\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: GPIODEN description: "GPIOD clock enable\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: GPIOHEN description: "GPIOH clock enable\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: ADC1EN description: "ADC1 peripherals clock enabled\r Set and reset by software." bit_offset: 10 bit_size: 1 - name: DAC12EN description: "DAC clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: HASHEN description: "HASH clock enable\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: RNGEN description: "RNG clock enable\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: SRAM2EN description: "SRAM2 clock enable\r Set and reset by software." bit_offset: 30 bit_size: 1 fieldset/AHB2LPENR: description: RCC AHB2 sleep clock register fields: - name: GPIOALPEN description: "GPIOA clock enable during sleep mode\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPIOBLPEN description: "GPIOB clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: GPIOCLPEN description: "GPIOC clock enable during sleep mode\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: GPIODLPEN description: "GPIOD clock enable during sleep mode\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: GPIOHLPEN description: "GPIOH clock enable during sleep mode\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: ADC1LPEN description: "ADC1 peripherals clock enable during sleep mode\r Set and reset by software." bit_offset: 10 bit_size: 1 - name: DAC12LPEN description: "DAC clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: HASHLPEN description: "HASH clock enable during sleep mode\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: RNGLPEN description: "RNG clock enable during sleep mode\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: SRAM2LPEN description: "SRAM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 30 bit_size: 1 fieldset/AHB2RSTR: description: RCC AHB2 peripheral reset register fields: - name: GPIOARST description: "GPIOA block reset\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: GPIOBRST description: "GPIOB block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: GPIOCRST description: "GPIOC block reset\r Set and reset by software." bit_offset: 2 bit_size: 1 - name: GPIODRST description: "GPIOD block reset\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: GPIOHRST description: "GPIOH block reset\r Set and reset by software." bit_offset: 7 bit_size: 1 - name: ADC1RST description: "ADC1 block reset\r Set and reset by software." bit_offset: 10 bit_size: 1 - name: DAC12RST description: "DAC block reset\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: HASHRST description: "HASH block reset\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: RNGRST description: "RNG block reset\r Set and reset by software." bit_offset: 18 bit_size: 1 fieldset/APB1HENR: description: RCC APB1 peripheral clock register fields: - name: DTSEN description: "DTS clock enable\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: LPTIM2EN description: "LPTIM2 clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: FDCAN1EN description: "FDCAN1 peripheral clock enable\r Set and reset by software." bit_offset: 9 bit_size: 1 fieldset/APB1HLPENR: description: RCC APB1 sleep clock register fields: - name: DTSLPEN description: "DTS clock enable during sleep mode\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: LPTIM2LPEN description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: FDCAN1LPEN description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software." bit_offset: 9 bit_size: 1 fieldset/APB1HRSTR: description: RCC APB1 peripheral high reset register fields: - name: DTSRST description: "DTS block reset\r Set and reset by software." bit_offset: 3 bit_size: 1 - name: LPTIM2RST description: "LPTIM2 block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: FDCAN1RST description: "FDCAN1 block reset\r Set and reset by software." bit_offset: 9 bit_size: 1 fieldset/APB1LENR: description: RCC APB1 peripheral clock register fields: - name: TIM2EN description: "TIM2 clock enable\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: TIM3EN description: "TIM3 clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: TIM6EN description: "TIM6 clock enable\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: TIM7EN description: "TIM7 clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: WWDGEN description: "WWDG clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: OPAMPEN description: "OPAMP clock enable\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: SPI2EN description: "SPI2 clock enable\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: SPI3EN description: "SPI3 clock enable\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: COMPEN description: "COMP clock enable\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: USART2EN description: "USART2 clock enable\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: USART3EN description: "USART3 clock enable\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: I2C1EN description: "I2C1 clock enable\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: I2C2EN description: "I2C2 clock enable\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: I3C1EN description: "I3C1 clock enable\r Set and reset by software." bit_offset: 23 bit_size: 1 - name: CRSEN description: "CRS clock enable\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB1LLPENR: description: RCC APB1 sleep clock register fields: - name: TIM2LPEN description: "TIM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: TIM3LPEN description: "TIM3 clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: TIM6LPEN description: "TIM6 clock enable during sleep mode\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: TIM7LPEN description: "TIM7 clock enable during sleep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: WWDGLPEN description: "WWDG clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: OPAMPLPEN description: "OPAMP clock enable during sleep mode\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: SPI2LPEN description: "SPI2 clock enable during sleep mode\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: SPI3LPEN description: "SPI3 clock enable during sleep mode\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: COMPLPEN description: "COMP clock enable during sleep mode\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: USART2LPEN description: "USART2 clock enable during sleep mode\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: USART3LPEN description: "USART3 clock enable during sleep mode\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: I2C1LPEN description: "I2C1 clock enable during sleep mode\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: I2C2LPEN description: "I2C2 clock enable during sleep mode\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: I3C1LPEN description: "I3C1 clock enable during sleep mode\r Set and reset by software." bit_offset: 23 bit_size: 1 - name: CRSLPEN description: "CRS clock enable during sleep mode\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB1LRSTR: description: RCC APB1 peripheral low reset register fields: - name: TIM2RST description: "TIM2 block reset\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: TIM3RST description: "TIM3 block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: TIM6RST description: "TIM6 block reset\r Set and reset by software." bit_offset: 4 bit_size: 1 - name: TIM7RST description: "TIM7 block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - name: OPAMPRST description: "OPAMP block reset\r Set and reset by software." bit_offset: 13 bit_size: 1 - name: SPI2RST description: "SPI2 block reset\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: SPI3RST description: "SPI3 block reset\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: COMPRST description: "COMP block reset\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: USART2RST description: "USART2 block reset\r Set and reset by software." bit_offset: 17 bit_size: 1 - name: USART3RST description: "USART3 block reset\r Set and reset by software." bit_offset: 18 bit_size: 1 - name: I2C1RST description: "I2C1 block reset\r Set and reset by software." bit_offset: 21 bit_size: 1 - name: I2C2RST description: "I2C2 block reset\r Set and reset by software." bit_offset: 22 bit_size: 1 - name: I3C1RST description: "I3C1 block reset\r Set and reset by software." bit_offset: 23 bit_size: 1 - name: CRSRST description: "CRS block reset\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB2ENR: description: RCC APB2 peripheral clock register fields: - name: TIM1EN description: "TIM1 clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI1EN description: "SPI1 clock enable\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: USART1EN description: "USART1 clock enable\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: USBEN description: "USB clock enable\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB2LPENR: description: RCC APB2 sleep clock register fields: - name: TIM1LPEN description: "TIM1 clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI1LPEN description: "SPI1 clock enable during sleep mode\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: USART1LPEN description: "USART1 clock enable during sleep mode\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: USBLPEN description: "USB clock enable during sleep mode\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB2RSTR: description: RCC APB2 peripheral reset register fields: - name: TIM1RST description: "TIM1 block reset\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: SPI1RST description: "SPI1 block reset\r Set and reset by software." bit_offset: 12 bit_size: 1 - name: USART1RST description: "USART1 block reset\r Set and reset by software." bit_offset: 14 bit_size: 1 - name: USBRST description: "USB block reset\r Set and reset by software." bit_offset: 24 bit_size: 1 fieldset/APB3ENR: description: RCC APB3 peripheral clock register fields: - name: SBSEN description: "SBS clock enable\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: LPUART1EN description: "LPUART1 clock enable\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: I3C2EN description: "I3C2EN clock enable\r Set and reset by software." bit_offset: 9 bit_size: 1 - name: LPTIM1EN description: "LPTIM1 clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: VREFEN description: "VREF clock enable\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: RTCAPBEN description: "RTC APB interface clock enable\r Set and reset by software." bit_offset: 21 bit_size: 1 fieldset/APB3LPENR: description: RCC APB3 sleep clock register fields: - name: SBSLPEN description: "SBS clock enable during sleep mode\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: LPUART1LPEN description: "LPUART1 clock enable during sleep mode\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: I3C2LPEN description: "I3C2 clock enable during sleep mode\r Set and reset by software." bit_offset: 9 bit_size: 1 - name: LPTIM1LPEN description: "LPTIM1 clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: VREFLPEN description: "VREF clock enable during sleep mode\r Set and reset by software." bit_offset: 20 bit_size: 1 - name: RTCAPBLPEN description: "RTC APB interface clock enable during sleep mode\r Set and reset by software." bit_offset: 21 bit_size: 1 fieldset/APB3RSTR: description: RCC APB3 peripheral reset register fields: - name: SBSRST description: "SBS block reset\r Set and reset by software." bit_offset: 1 bit_size: 1 - name: LPUART1RST description: "LPUART1 block reset\r Set and reset by software." bit_offset: 6 bit_size: 1 - name: I3C2RST description: "I3C2RST block reset\r Set and reset by software." bit_offset: 9 bit_size: 1 - name: LPTIM1RST description: "LPTIM1 block reset\r Set and reset by software." bit_offset: 11 bit_size: 1 - name: VREFRST description: "VREF block reset\r Set and reset by software." bit_offset: 20 bit_size: 1 fieldset/BDCR: description: RCC Backup domain control register fields: - name: LSEON description: "LSE oscillator enabled\r Set and reset by software." bit_offset: 0 bit_size: 1 - name: LSERDY description: "LSE oscillator ready\r Set and reset by hardware to indicate when the LSE is stable.\r This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0." bit_offset: 1 bit_size: 1 - name: LSEBYP description: "LSE oscillator bypass\r Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)" bit_offset: 2 bit_size: 1 - name: LSEDRV description: "LSE oscillator driving capability\r Set by software to select the driving capability of the LSE oscillator.\r These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0)." bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: "LSE clock security system enable\r Set by software to enable the clock security system on 32 kHz oscillator.\r LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON." bit_offset: 5 bit_size: 1 - name: LSECSSD description: "LSE clock security system failure detection\r Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator." bit_offset: 6 bit_size: 1 - name: LSEEXT description: "low-speed external clock type in bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the LSEON bit, to be used by the device.\r The LSEEXT bit can be written only if the LSE oscillator is disabled." bit_offset: 7 bit_size: 1 enum: LSEEXT - name: RTCSEL description: "RTC clock source selection\r Set by software to select the clock source for the RTC.\r These bits can be written only one time (except in case of failure detection on LSE).\r These bits must be written before LSECSSON is enabled.\r The VSWRST bit can be used to reset them, then it can be written one time again.\r If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST)." bit_offset: 8 bit_size: 2 enum: RTCSEL - name: RTCEN description: "RTC clock enable\r Set and reset by software." bit_offset: 15 bit_size: 1 - name: VSWRST description: "VSwitch domain software reset\r Set and reset by software." bit_offset: 16 bit_size: 1 - name: LSCOEN description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: LSCOSEL description: "Low-speed clock output selection\r Set and cleared by software." bit_offset: 25 bit_size: 1 enum: LSCOSEL - name: LSION description: "LSI oscillator enable\r Set and cleared by software." bit_offset: 26 bit_size: 1 - name: LSIRDY description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is stable.\r After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles.\r This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0." bit_offset: 27 bit_size: 1 fieldset/CCIPR1: description: RCC kernel clock configuration register fields: - name: USART1SEL description: "USART1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 0 bit_size: 3 enum: USARTSEL - name: USART2SEL description: "USART2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 3 bit_size: 3 enum: USARTSEL - name: USART3SEL description: "USART3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 6 bit_size: 3 enum: USARTSEL - name: TIMICSEL description: "TIM2, TIM3 and LPTIM2 input capture source selection\r Set and reset by software." bit_offset: 31 bit_size: 1 enum: TIMICSEL fieldset/CCIPR2: description: RCC kernel clock configuration register fields: - name: LPTIM1SEL description: "LPTIM1 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 8 bit_size: 3 enum: LPTIMSEL - name: LPTIM2SEL description: "LPTIM2 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 12 bit_size: 3 enum: LPTIMSEL fieldset/CCIPR3: description: RCC kernel clock configuration register fields: - name: SPI1SEL description: "SPI1 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 0 bit_size: 3 enum: SPISEL - name: SPI2SEL description: "SPI2 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 3 bit_size: 3 enum: SPISEL - name: SPI3SEL description: "SPI3 kernel clock source selection\r Set and reset by software.\r others: reserved, the kernel clock is disabled" bit_offset: 6 bit_size: 3 enum: SPISEL - name: LPUART1SEL description: "LPUART1 kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 24 bit_size: 3 enum: LPUARTSEL fieldset/CCIPR4: description: RCC kernel clock configuration register fields: - name: SYSTICKSEL description: "SYSTICK clock source selection\r Note: rcc_hclk frequency must be four times higher than\r lsi_ker_ck/lse_ck (period (LSI/LSE) ≥ 4 * period (HCLK)." bit_offset: 2 bit_size: 2 enum: SYSTICKSEL - name: USBSEL description: USB kernel clock source selection bit_offset: 4 bit_size: 2 enum: USBSEL - name: I2C1SEL description: I2C1 kernel clock source selection bit_offset: 16 bit_size: 2 enum: ICSEL - name: I2C2SEL description: I2C2 kernel clock source selection bit_offset: 18 bit_size: 2 enum: ICSEL - name: I3C1SEL description: I3C1 kernel clock source selection bit_offset: 24 bit_size: 2 enum: ICSEL - name: I3C2SEL description: I3C2 kernel clock source selection bit_offset: 26 bit_size: 2 enum: ICSEL fieldset/CCIPR5: description: RCC kernel clock configuration register fields: - name: ADCDACSEL description: "ADC and DAC kernel clock source selection\r others: reserved, the kernel clock is disabled" bit_offset: 0 bit_size: 3 enum: ADCDACSEL - name: DACSEL description: DAC hold clock bit_offset: 3 bit_size: 1 enum: DACSEL - name: RNGSEL description: RNG kernel clock source selection bit_offset: 4 bit_size: 2 enum: RNGSEL - name: FDCAN1SEL description: FDCAN1 kernel clock source selection bit_offset: 8 bit_size: 2 enum: FDCANSEL - name: CKPERSEL description: per_ck clock source selection bit_offset: 30 bit_size: 2 enum: CKPERSEL fieldset/CFGR: description: RCC clock configuration register fields: - name: SW description: "system clock and trace clock switch\r Set and reset by software to select system clock and trace clock sources (sys_ck).\r Set by hardware in order to:\r -\tforce the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode\r -\tforce the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock\r others: reserved" bit_offset: 0 bit_size: 3 enum: SW - name: SWS description: "system clock switch status\r Set and reset by hardware to indicate which clock source is used as system clock. 000: HSI used as system clock (hsi_ck) (default after reset).\r others: reserved" bit_offset: 3 bit_size: 3 enum: SW - name: STOPWUCK description: "system clock selection after a wakeup from system Stop\r Set and reset by software to select the system wakeup clock from system Stop.\r The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. 0: HSI selected as wakeup clock from system Stop (default after reset)\r STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10)." bit_offset: 6 bit_size: 1 enum: STOPWUCK - name: STOPKERWUCK description: "kernel clock selection after a wakeup from system Stop\r Set and reset by software to select the kernel wakeup clock from system Stop." bit_offset: 7 bit_size: 1 enum: STOPKERWUCK - name: RTCPRE description: "HSE division factor for RTC clock\r Set and cleared by software to divide the HSE to generate a clock for RTC.\r Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.\r ..." bit_offset: 8 bit_size: 6 - name: TIMPRE description: "timers clocks prescaler selection\r This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains." bit_offset: 15 bit_size: 1 enum: TIMPRE - name: MCO1PRE description: "MCO1 prescaler\r Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." bit_offset: 18 bit_size: 4 - name: MCO1 description: "Microcontroller clock output 1\r Set and cleared by software. Clock source selection may generate glitches on MCO1.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 22 bit_size: 3 enum: MCO1 - name: MCO2PRE description: "MCO2 prescaler\r Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.\r ..." bit_offset: 25 bit_size: 4 - name: MCO2 description: "microcontroller clock output 2\r Set and cleared by software. Clock source selection may generate glitches on MCO2.\r It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.\r others: reserved" bit_offset: 29 bit_size: 3 enum: MCO2 fieldset/CFGR2: description: RCC CPU domain clock configuration register 2 fields: - name: HPRE description: "AHB prescaler\r Set and reset by software to control the division factor of rcc_hclk. Changing\r this division ratio has an impact on the frequency of all bus matrix clocks\r 0xxx: rcc_hclk = sys_ck (default after reset)" bit_offset: 0 bit_size: 4 enum: HPRE - name: PPRE1 description: "APB low-speed prescaler (APB1)\r Set and reset by software to control the division factor of rcc_pclk1.\r The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk after PPRE write.\r 0xx: rcc_pclk1 = rcc_hclk1 (default after reset)" bit_offset: 4 bit_size: 3 enum: PPRE - name: PPRE2 description: "APB high-speed prescaler (APB2)\r Set and reset by software to control APB high-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE2 write.\r 0xx: rcc_pclk2 = rcc_hclk1" bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE3 description: "APB low-speed prescaler (APB3)\r Set and reset by software to control APB low-speed clocks division factor.\r The clocks are divided with the new prescaler factor from 1 to 16 APB cycles after PPRE3 write.\r 0xx: rcc_pclk3 = rcc_hclk1" bit_offset: 12 bit_size: 3 enum: PPRE - name: AHB1DIS description: "AHB1 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB1\r peripherals from RCC_AHB1ENR are used and when their clocks are disabled in\r RCC_AHB1ENR. When this bit is set, all the AHB1 peripherals clocks from\r RCC_AHB1ENR are off.\r enable control bits" bit_offset: 16 bit_size: 1 - name: AHB2DIS description: "AHB2 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB2\r peripherals from RCC_AHB2ENR are used and when their clocks are disabled in\r RCC_AHB2ENR. When this bit is set, all the AHB2 peripherals clocks from\r RCC_AHB2ENR are off.\r enable control bits" bit_offset: 17 bit_size: 1 - name: AHB4DIS description: "AHB4 clock disable\r This bit can be set in order to further reduce power consumption, when none of the AHB4\r peripherals from RCC_AHB4ENR are used and when their clocks are disabled in\r RCC_AHB4ENR. When this bit is set, all the AHB4 peripherals clocks from\r RCC_AHB4ENR are off.\r enable control bits" bit_offset: 19 bit_size: 1 - name: APB1DIS description: "APB1 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB1\r peripherals (except IWDG) are used and when their clocks are disabled in RCC_APB1ENR.\r When this bit is set, all the APB1 peripherals clocks are off, except for IWDG.\r control bits" bit_offset: 20 bit_size: 1 - name: APB2DIS description: "APB2 clock disable value\r This bit can be set in order to further reduce power consumption, when none of the APB2\r peripherals are used and when their clocks are disabled in RCC_APB2ENR. When this bit is\r set, all the APB2 peripherals clocks are off.\r control bits" bit_offset: 21 bit_size: 1 - name: APB3DIS description: "APB3 clock disable value.Set and cleared by software\r This bit can be set in order to further reduce power consumption, when none of the APB3\r peripherals are used and when their clocks are disabled in RCC_APB3ENR. When this bit is\r set, all the APB3 peripherals clocks are off.\r control bits" bit_offset: 22 bit_size: 1 fieldset/CICR: description: RCC clock source interrupt clear register fields: - name: LSIRDYC description: "LSI ready interrupt clear\r Set by software to clear LSIRDYF.\r Reset by hardware when clear done." bit_offset: 0 bit_size: 1 - name: LSERDYC description: "LSE ready interrupt clear\r Set by software to clear LSERDYF.\r Reset by hardware when clear done." bit_offset: 1 bit_size: 1 - name: CSIRDYC description: "HSI ready interrupt clear\r Set by software to clear CSIRDYF.\r Reset by hardware when clear done." bit_offset: 2 bit_size: 1 - name: HSIRDYC description: "HSI ready interrupt clear\r Set by software to clear HSIRDYF.\r Reset by hardware when clear done." bit_offset: 3 bit_size: 1 - name: HSERDYC description: "HSE ready interrupt clear\r Set by software to clear HSERDYF.\r Reset by hardware when clear done." bit_offset: 4 bit_size: 1 - name: HSI48RDYC description: "HSI48 ready interrupt clear\r Set by software to clear HSI48RDYF.\r Reset by hardware when clear done." bit_offset: 5 bit_size: 1 - name: PLLRDYC description: "PLL1 ready interrupt clear\r Set by software to clear PLL1RDYF.\r Reset by hardware when clear done." bit_offset: 6 bit_size: 1 array: len: 2 stride: 1 - name: HSECSSC description: "HSE clock security system interrupt clear\r Set by software to clear HSECSSF.\r Reset by hardware when clear done." bit_offset: 10 bit_size: 1 fieldset/CIER: description: RCC clock source interrupt enable register fields: - name: LSIRDYIE description: "LSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization." bit_offset: 0 bit_size: 1 - name: LSERDYIE description: "LSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization." bit_offset: 1 bit_size: 1 - name: CSIRDYIE description: "CSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization." bit_offset: 2 bit_size: 1 - name: HSIRDYIE description: "HSI ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization." bit_offset: 3 bit_size: 1 - name: HSERDYIE description: "HSE ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization." bit_offset: 4 bit_size: 1 - name: HSI48RDYIE description: "HSI48 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization." bit_offset: 5 bit_size: 1 - name: PLLRDYIE description: "PLL1 ready interrupt enable\r Set and reset by software to enable/disable interrupt caused by PLL1 lock." bit_offset: 6 bit_size: 1 array: len: 2 stride: 1 fieldset/CIFR: description: RCC clock source interrupt flag register fields: - name: LSIRDYF description: "LSI ready interrupt flag\r Reset by software by writing LSIRDYC bit.\r Set by hardware when the LSI clock becomes stable and LSIRDYIE is set." bit_offset: 0 bit_size: 1 - name: LSERDYF description: "LSE ready interrupt flag\r Reset by software by writing LSERDYC bit.\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set." bit_offset: 1 bit_size: 1 - name: CSIRDYF description: "CSI ready interrupt flag\r Reset by software by writing CSIRDYC bit.\r Set by hardware when the CSI clock becomes stable and CSIRDYIE is set." bit_offset: 2 bit_size: 1 - name: HSIRDYF description: "HSI ready interrupt flag\r Reset by software by writing HSIRDYC bit.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set." bit_offset: 3 bit_size: 1 - name: HSERDYF description: "HSE ready interrupt flag\r Reset by software by writing HSERDYC bit.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set." bit_offset: 4 bit_size: 1 - name: HSI48RDYF description: "HSI48 ready interrupt flag\r Reset by software by writing HSI48RDYC bit.\r Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set." bit_offset: 5 bit_size: 1 - name: PLLRDYF description: "PLL1 ready interrupt flag\r Reset by software by writing PLL1RDYC bit.\r Set by hardware when the PLL1 locks and PLL1RDYIE is set." bit_offset: 6 bit_size: 1 array: len: 2 stride: 1 - name: HSECSSF description: "HSE clock security system interrupt flag\r Reset by software by writing HSECSSC bit.\r Set by hardware in case of HSE clock failure." bit_offset: 10 bit_size: 1 fieldset/CR: description: RCC clock control register fields: - name: HSION description: "HSI clock enable\r Set and cleared by software.\r Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.\r This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock, or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." bit_offset: 0 bit_size: 1 - name: HSIRDY description: "HSI clock ready flag\r Set by hardware to indicate that the HSI oscillator is stable." bit_offset: 1 bit_size: 1 - name: HSIKERON description: "HSI clock enable in Stop mode\r Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION." bit_offset: 2 bit_size: 1 - name: HSIDIV description: "HSI clock divider\r Set and reset by software.\r These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The\r HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to 1). In that case, the new HSIDIV value is ignored." bit_offset: 3 bit_size: 2 enum: HSIDIV - name: HSIDIVF description: "HSI divider flag\r Set and reset by hardware.\r As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the\r current status of the HSI divider. HSIDIVF goes immediately to 0 when HSIDIV value is changed, and is set back to 1 when the output frequency matches the value programmed into HSIDIV." bit_offset: 5 bit_size: 1 - name: CSION description: "CSI clock enable\r Set and reset by software to enable/disable CSI clock for system and/or peripheral.\r Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = 1 or STOPKERWUCK = 1.\r This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock, or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." bit_offset: 8 bit_size: 1 - name: CSIRDY description: "CSI clock ready flag\r Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request)." bit_offset: 9 bit_size: 1 - name: CSIKERON description: "CSI clock enable in Stop mode\r Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION." bit_offset: 10 bit_size: 1 - name: HSI48ON description: "HSI48 clock enable\r Set by software and cleared by software or by the hardware when the system enters to Stop\r or Standby mode." bit_offset: 12 bit_size: 1 - name: HSI48RDY description: "HSI48 clock ready flag\r Set by hardware to indicate that the HSI48 oscillator is stable." bit_offset: 13 bit_size: 1 - name: HSEON description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE when entering Stop or Standby mode.\r This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock, or if the\r HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to 1)." bit_offset: 16 bit_size: 1 - name: HSERDY description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable." bit_offset: 17 bit_size: 1 - name: HSEBYP description: "HSE clock bypass\r Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit to be used by the device.\r The HSEBYP bit can be written only if the HSE oscillator is disabled." bit_offset: 18 bit_size: 1 - name: HSECSSON description: "HSE clock security system enable\r Set by software to enable clock security system on HSE.\r This bit is “set only” (disabled by a system reset or when the system enters in Standby mode). When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected." bit_offset: 19 bit_size: 1 - name: HSEEXT description: "external high speed clock type in Bypass mode\r Set and reset by software to select the external clock type (analog or digital).\r The external clock must be enabled with the HSEON bit to be used by the device. The HSEEXT bit can be written only if the HSE oscillator is disabled." bit_offset: 20 bit_size: 1 enum: HSEEXT - name: PLLON description: "PLL1 enable\r Set and cleared by software to enable PLL1.\r Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents\r writing this bit to 0, if the PLL1 output is used as the system clock." bit_offset: 24 bit_size: 1 array: len: 2 stride: 2 - name: PLLRDY description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked." bit_offset: 25 bit_size: 1 array: len: 2 stride: 2 fieldset/CRRCR: description: RCC clock recovery RC register fields: - name: HSI48CAL description: "Internal RC 48 MHz clock calibration\r Set by hardware by option-byte loading during system reset NRESET. Read-only." bit_offset: 0 bit_size: 10 fieldset/CSICFGR: description: RCC CSI calibration register fields: - name: CSICAL description: "CSI clock calibration\r Set by hardware by option byte loading during system reset NRESET. Adjusted by software through trimming bits CSITRIM.\r This field represents the sum of engineering option byte calibration value and CSITRIM bits value." bit_offset: 0 bit_size: 8 - name: CSITRIM description: "CSI clock trimming\r Set by software to adjust calibration.\r CSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_CSI_OPT) in order to form the calibration trimming value.\r CSICAL = CSITRIM + FLASH_CSI_OPT.\r Note: The reset value of the field is 0x20." bit_offset: 16 bit_size: 6 fieldset/HSICFGR: description: RCC HSI calibration register fields: - name: HSICAL description: "HSI clock calibration\r Set by hardware by option byte loading during system reset nreset. Adjusted by software through trimming bits HSITRIM.\r This field represents the sum of engineering option byte calibration value and HSITRIM bits value." bit_offset: 0 bit_size: 12 - name: HSITRIM description: "HSI clock trimming\r Set by software to adjust calibration.\r HSITRIM field is added to the engineering option bytes loaded during reset phase (FLASH_HSI_OPT) in order to form the calibration trimming value.\r HSICAL = HSITRIM + FLASH_HSI_OPT.\r After a change of HSITRIM it takes one system clock cycle before the new HSITRIM value is updated\r Note: The reset value of the field is 0x40." bit_offset: 16 bit_size: 7 fieldset/PLLCFGR: description: RCC PLL clock source selection register fields: - name: PLLSRC description: "DIVMx and PLLs clock source selection\r Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled.\r In order to save power, when no PLL is used, the value of PLL1SRC must be set to '00'. 00: no clock send to DIVMx divider and PLLs (default after reset)." bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLRGE description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1. This bit must be written before enabling the PLL1." bit_offset: 2 bit_size: 2 enum: PLLRGE - name: PLLFRACEN description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of FRACN1 into the sigma-delta modulator.\r In order to latch the FRACN1 value into the sigma-delta modulator, PLL1FRACEN must be set to 0, then set to 1. The transition 0 to 1 transfers the content of FRACN1 into the modulator." bit_offset: 4 bit_size: 1 - name: PLLVCOSEL description: "PLL1 VCO selection\r Set and reset by software to select the proper VCO frequency range used for PLL1. This bit must be written before enabling the PLL1." bit_offset: 5 bit_size: 1 enum: PLLVCOSEL - name: DIVM description: "prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1.\r The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1 or PLL1RDY = 1).\r In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0.\r ...\r ..." bit_offset: 8 bit_size: 6 - name: PLLPEN description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1_p_ck output of the PLL1.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled." bit_offset: 16 bit_size: 1 - name: PLLQEN description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1_q_ck output of the PLL1.\r In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 17 bit_size: 1 - name: PLLREN description: "PLL1 DIVR divider output enable\r Set and reset by software to enable the pll1_r_ck output of the PLL1.\r To save power, DIVR1EN and DIVR1 bits must be set to 0 when the pll1_r_ck is not used. This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)." bit_offset: 18 bit_size: 1 fieldset/PLLDIVR: description: RCC PLL1 dividers register fields: - name: PLLN description: "Multiplication factor for PLL1VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r Others: reserved" bit_offset: 0 bit_size: 9 - name: PLLP description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1_p_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..." bit_offset: 9 bit_size: 7 - name: PLLQ description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the pll1_q_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 16 bit_size: 7 - name: PLLR description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1_r_ck clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..." bit_offset: 24 bit_size: 7 fieldset/PLLFRACR: description: RCC PLL1 fractional divider register fields: - name: PLLFRACN description: "fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO. These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r The software must set correctly these bits to insure that the VCO output frequency is between its valid frequency range, that is:\r * 128 to 560 MHz if PLL1VCOSEL = 0\r * \t150 to 420 MHz if PLL1VCOSEL = 1\r VCO output frequency = Fref1_ck x (PLL1N + (PLL1FRACN / 213)), with\r * \tPLL1N between 8 and 420\r * \tPLL1FRACN can be between 0 and 213- 1\r * \tThe input frequency Fref1_ck must be between 1 and 16 MHz.\r To change the PLL1FRACN value on-the-fly even if the PLL is enabled, the application must proceed as follows:\r * \tSet the bit PLL1FRACEN to 0\r * \tWrite the new fractional value into PLL1FRACN\r * \tSet the bit PLL1FRACEN to 1" bit_offset: 3 bit_size: 13 fieldset/RSR: description: RCC reset status register fields: - name: RMVF description: "remove reset flag\r Set and reset by software to reset the value of the reset flags." bit_offset: 23 bit_size: 1 - name: PINRSTF description: "pin reset flag (NRST)\r Reset by software by writing the RMVF bit.\r Set by hardware when a reset from pin occurs." bit_offset: 26 bit_size: 1 - name: BORRSTF description: "BOR reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a BOR reset occurs (pwr_bor_rst)." bit_offset: 27 bit_size: 1 - name: SFTRSTF description: "system reset from CPU reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when the system reset is due to CPU.The CPU can generate a system reset by writing SYSRESETREQ bit of AIRCR register of the core M33." bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: "independent watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when an independent watchdog reset occurs." bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: "window watchdog reset flag\r Reset by software by writing the RMVF bit.\r Set by hardware when a window watchdog reset occurs." bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: "Low-power reset flag\r Set by hardware when a reset occurs due to Stop or Standby mode entry, whereas the corresponding nRST_STOP, nRST_STBY option bit is cleared.\r Cleared by writing to the RMVF bit." bit_offset: 31 bit_size: 1 enum/ADCDACSEL: bit_size: 3 variants: - name: HCLK description: rcc_hclk selected as kernel clock (default after reset) value: 0 - name: SYSCLK description: sys_ck selected as kernel clock value: 1 - name: PLL2_R description: pll2_r_ck selected as kernel clock value: 2 - name: HSE description: hse_ck selected as kernel clock value: 3 - name: HSI_KER description: hsi_ker_ck selected as kernel clock value: 4 - name: CSI_KER description: csi_ker_ck selected as kernel clock value: 5 enum/CKPERSEL: bit_size: 2 variants: - name: HSI description: hsi_ker_ck selected as kernel clock (default after reset) value: 0 - name: CSI description: csi_ker_ck selected as kernel clock value: 1 - name: HSE description: hse_ck selected as kernel clock value: 2 enum/DACSEL: bit_size: 1 variants: - name: DAC_HOLD description: dac_hold_ck selected as kernel clock (default after reset) value: 0 - name: DAC_HOLD_2 description: dac_hold_ck selected as kernel clock value: 1 enum/FDCANSEL: bit_size: 2 variants: - name: HSE description: hse_ck selected as kernel clock (default after reset) value: 0 - name: PLL1_Q description: pll1_q_ck selected as kernel clock value: 1 - name: PLL2_Q description: pll2_q_ck selected as kernel clock value: 2 enum/HPRE: bit_size: 4 variants: - name: Div1 description: sys_ck not divided value: 0 - name: Div2 description: sys_ck divided by 2 value: 8 - name: Div4 description: sys_ck divided by 4 value: 9 - name: Div8 description: sys_ck divided by 8 value: 10 - name: Div16 description: sys_ck divided by 16 value: 11 - name: Div64 description: sys_ck divided by 64 value: 12 - name: Div128 description: sys_ck divided by 128 value: 13 - name: Div256 description: sys_ck divided by 256 value: 14 - name: Div512 description: sys_ck divided by 512 value: 15 enum/HSEEXT: bit_size: 1 variants: - name: Analog description: HSE in analog mode (default after reset) value: 0 - name: Digital description: HSE in digital mode value: 1 enum/HSIDIV: bit_size: 2 variants: - name: Div1 description: No division value: 0 - name: Div2 description: Division by 2 value: 1 - name: Div4 description: Division by 4 value: 2 - name: Div8 description: Division by 8 value: 3 enum/ICSEL: bit_size: 2 variants: - name: RCC_PCLK1 description: rcc_pclk1 selected as peripheral clock value: 0 - name: PLL3_R description: pll3_r selected as peripheral clock value: 1 - name: HSI_KER description: hsi_ker selected as peripheral clock value: 2 - name: CSI_KER description: csi_ker selected as peripheral clock value: 3 enum/LPTIMSEL: bit_size: 3 variants: - name: RCC_PCLK3 description: rcc_pclk3 selected as peripheral clock value: 0 - name: PLL2_P description: pll2_p selected as peripheral clock value: 1 - name: LSE description: LSE selected as peripheral clock value: 3 - name: LSI description: LSI selected as peripheral clock value: 4 - name: PER description: PER selected as peripheral clock value: 5 enum/LPUARTSEL: bit_size: 3 variants: - name: RCC_PCLK3 description: rcc_pclk3 selected as kernel clock (default after reset) value: 0 - name: PLL2_Q description: pll2_q_ck selected as kernel clock value: 1 - name: HSI_KER description: hsi_ker_ck selected as kernel clock value: 3 - name: CSI_KER description: csi_ker_ck selected as kernel clock value: 4 - name: LSE description: lse_ck selected as kernel clock value: 5 enum/LSCOSEL: bit_size: 1 variants: - name: LSI description: LSI clock selected value: 0 - name: LSE description: LSE clock selected value: 1 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/LSEEXT: bit_size: 1 variants: - name: Analog description: LSE in analog mode (default after Backup domain reset) value: 0 - name: Digital description: LSE in digital mode (do not use if RTC is active). value: 1 enum/MCO1: bit_size: 3 variants: - name: HSI description: HSI selected for micro-controller clock output value: 0 - name: LSE description: LSE selected for micro-controller clock output value: 1 - name: HSE description: HSE selected for micro-controller clock output value: 2 - name: PLL1_Q description: pll1_q selected for micro-controller clock output value: 3 - name: HSI48 description: HSI48 selected for micro-controller clock output value: 4 enum/MCO2: bit_size: 3 variants: - name: SYSCLK description: System clock selected for micro-controller clock output value: 0 - name: PLL2_P description: pll2_p selected for micro-controller clock output value: 1 - name: HSE description: HSE selected for micro-controller clock output value: 2 - name: PLL1_P description: pll1_p selected for micro-controller clock output value: 3 - name: CSI description: CSI selected for micro-controller clock output value: 4 - name: LSI description: LSI selected for micro-controller clock output value: 5 enum/PLLRGE: bit_size: 2 variants: - name: Range1 description: Frequency is between 1 and 2 MHz value: 0 - name: Range2 description: Frequency is between 2 and 4 MHz value: 1 - name: Range4 description: Frequency is between 4 and 8 MHz value: 2 - name: Range8 description: Frequency is between 8 and 16 MHz value: 3 enum/PLLSRC: bit_size: 2 variants: - name: None description: no clock send to DIVMx divider and PLLs (default after reset) value: 0 - name: HSI description: HSI selected as PLL clock (hsi_ck) value: 1 - name: CSI description: CSI selected as PLL clock (csi_ck) value: 2 - name: HSE description: HSE selected as PLL clock (hse_ck) value: 3 enum/PLLVCOSEL: bit_size: 1 variants: - name: WideVCO description: VCO frequency range 192 to 836 MHz value: 0 - name: MediumVCO description: VCO frequency range 150 to 420 MHz value: 1 enum/PPRE: bit_size: 3 variants: - name: Div1 description: rcc_pclk3 = rcc_hclk1 / 1 value: 0 - name: Div2 description: rcc_pclk3 = rcc_hclk1 / 2 value: 4 - name: Div4 description: rcc_pclk3 = rcc_hclk1 / 4 value: 5 - name: Div8 description: rcc_pclk3 = rcc_hclk1 / 8 value: 6 - name: Div16 description: rcc_pclk3 = rcc_hclk1 / 16 value: 7 enum/RNGSEL: bit_size: 2 variants: - name: HSI48_KER description: hsi48_ker_ck selected as kernel clock (default after reset) value: 0 - name: PLL1_Q description: pll1_q_ck selected as kernel clock value: 1 - name: LSE description: lse_ck selected as kernel clock value: 2 - name: LSI_KER description: lsi_ker_ck selected as kernel clock value: 3 enum/RTCSEL: bit_size: 2 variants: - name: NoClock description: no clock (default after Backup domain reset) value: 0 - name: LSE description: LSE selected as RTC clock value: 1 - name: LSI description: LSI selected as RTC clock value: 2 - name: HSE_DIV_RTCPRE description: HSE divided by RTCPRE value selected as RTC clock value: 3 enum/SPISEL: bit_size: 3 variants: - name: RCC_PCLK4 description: rcc_pclk4 selected as peripheral clock value: 0 - name: PLL2_Q description: pll2_q selected as peripheral clock value: 1 - name: HSI_KER description: hsi_ker selected as peripheral clock value: 3 - name: CSI_KER description: csi_ker selected as peripheral clock value: 4 enum/STOPKERWUCK: bit_size: 1 variants: - name: HSI description: HSI selected as wakeup clock from system Stop (default after reset) value: 0 - name: CSI description: CSI selected as wakeup clock from system Stop value: 1 enum/STOPWUCK: bit_size: 1 variants: - name: CSI description: CSI selected as wakeup clock from system Stop value: 1 enum/SW: bit_size: 3 variants: - name: HSI description: HSI selected as system clock value: 0 - name: CSI description: CSI selected as system clock value: 1 - name: HSE description: HSE selected as system clock value: 2 - name: PLL1 description: PLL1 selected as system clock value: 3 enum/SYSTICKSEL: bit_size: 2 variants: - name: HCLK_DIV_8 description: rcc_hclk/8 selected as clock source (default after reset) value: 0 - name: LSI_KER description: lsi_ker_ck[1] selected as clock source value: 1 - name: LSE description: lse_ck[1] selected as clock source value: 2 enum/TIMICSEL: bit_size: 1 variants: - name: B_0x0 description: No internal clock available for timers input capture (default after reset) value: 0 - name: B_0x1 description: hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture value: 1 enum/TIMPRE: bit_size: 1 variants: - name: DefaultX2 description: The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 (default after reset) value: 0 - name: DefaultX4 description: The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2 corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2 value: 1 enum/USARTSEL: bit_size: 3 variants: - name: RCC_PCLK2 description: rcc_pclk2 selected as peripheral clock value: 0 - name: PLL2_Q description: pll2_q selected as peripheral clock value: 1 - name: HSI_KER description: hsi_ker selected as peripheral clock value: 3 - name: CSI_KER description: csi_ker selected as peripheral clock value: 4 - name: LSE description: LSE selected as peripheral clock value: 5 enum/USBSEL: bit_size: 2 variants: - name: DISABLE description: Disable the kernel clock value: 0 - name: PLL1_Q description: pll1_q selected as peripheral clock value: 1 - name: HSI48 description: HSI48 selected as peripheral clock value: 3