block/FLASH: description: Embedded Flash memory. items: - name: ACR description: Access control register. byte_offset: 0 fieldset: ACR - name: KEYR description: FLASH control key register. byte_offset: 4 fieldset: KEYR - name: CR description: FLASH control register. byte_offset: 16 fieldset: CR - name: SR description: FLASH status register. byte_offset: 20 fieldset: SR - name: FCR description: FLASH status register. byte_offset: 24 fieldset: FCR - name: IER description: FLASH interrupt enable register. byte_offset: 32 fieldset: IER - name: ISR description: FLASH interrupt status register. byte_offset: 36 fieldset: ISR - name: ICR description: FLASH interrupt clear register. byte_offset: 40 fieldset: ICR - name: CRCCR description: FLASH CRC control register. byte_offset: 48 fieldset: CRCCR - name: CRCSADDR description: FLASH CRC start address register. byte_offset: 52 fieldset: CRCSADDR - name: CRCEADDR description: FLASH CRC end address register. byte_offset: 56 fieldset: CRCEADDR - name: CRCDATAR description: FLASH CRC data register. byte_offset: 60 fieldset: CRCDATAR - name: ECCSFADDR description: FLASH ECC single error fail address. byte_offset: 64 fieldset: ECCSFADDR - name: ECCDFADDR description: FLASH ECC double error fail address. byte_offset: 68 fieldset: ECCDFADDR - name: OPTKEYR description: FLASH options key register. byte_offset: 256 fieldset: OPTKEYR - name: OPTCR description: FLASH options control register. byte_offset: 260 fieldset: OPTCR - name: OPTISR description: FLASH options interrupt status register. byte_offset: 264 fieldset: OPTISR - name: OPTICR description: FLASH options interrupt clear register. byte_offset: 268 fieldset: OPTICR - name: OBKCR description: FLASH option byte key control register. byte_offset: 272 fieldset: OBKCR - name: OBKDR description: FLASH option bytes key data register 0. array: len: 8 stride: 4 byte_offset: 280 - name: NVSR description: FLASH non-volatile status register. byte_offset: 512 fieldset: NVSR - name: NVSRP description: FLASH security status register programming. byte_offset: 516 fieldset: NVSRP - name: ROTSR description: FLASH RoT status register. byte_offset: 520 fieldset: ROTSR - name: ROTSRP description: FLASH RoT status register programming. byte_offset: 524 fieldset: ROTSRP - name: OTPLSR description: FLASH OTP lock status register. byte_offset: 528 fieldset: OTPLSR - name: OTPLSRP description: FLASH OTP lock status register programming. byte_offset: 532 fieldset: OTPLSRP - name: WRPSR description: FLASH write protection status register. byte_offset: 536 fieldset: WRPSR - name: WRPSRP description: FLASH write protection status register programming. byte_offset: 540 fieldset: WRPSRP - name: HDPSR description: FLASH hide protection status register. byte_offset: 560 fieldset: HDPSR - name: HDPSRP description: FLASH hide protection status register programming. byte_offset: 564 fieldset: HDPSRP - name: EPOCHSR description: FLASH epoch status register. byte_offset: 592 fieldset: EPOCHSR - name: EPOCHSRP description: FLASH RoT status register programming. byte_offset: 596 fieldset: EPOCHSRP - name: OBW1SR description: FLASH option byte word 1 status register. byte_offset: 608 fieldset: OBW1SR - name: OBW1SRP description: FLASH option byte word 1 status register programming. byte_offset: 612 fieldset: OBW1SRP - name: OBW2SR description: FLASH option byte word 2 status register. byte_offset: 616 fieldset: OBW2SR - name: OBW2SRP description: FLASH option byte word 2 status register programming. byte_offset: 620 fieldset: OBW2SRP fieldset/ACR: description: Access control register. fields: - name: LATENCY description: 'Read latency These bits are used to control the number of wait states used during read operations on both non-volatile memory banks. The application software has to program them to the correct value depending on the embedded Flash memory interface frequency and voltage conditions. Please refer to Table 27 for details. ... Note: Embedded Flash does not verify that the configuration is correct.' bit_offset: 0 bit_size: 4 - name: WRHIGHFREQ description: 'Flash signal delay These bits are used to control the delay between non-volatile memory signals during programming operations. Application software has to program them to the correct value depending on the embedded Flash memory interface frequency. Please refer to Table 27 for details. Note: Embedded Flash does not verify that the configuration is correct.' bit_offset: 4 bit_size: 2 fieldset/CR: description: FLASH control register. fields: - name: LOCK description: Configuration lock bit When this bit is set write to all other bits in this register, and to FLASH_IER register, are ignored. Clearing this bit requires the correct write sequence to FLASH_KEYR register (see this register for details). If a wrong sequence is executed, or if the unlock sequence is performed twice, this bit remains locked until the next system reset. During the write access to set LOCK bit from 0 to 1, it is possible to change the other bits of this register. bit_offset: 0 bit_size: 1 - name: PG description: Internal buffer control bit Setting this bit enables internal buffer for write operations. This allows preparing program operations even if a sector or bank erase is ongoing. When PG is cleared, the internal buffer is disabled for write operations, and all the data stored in the buffer but not sent to the operation queue are lost. bit_offset: 1 bit_size: 1 - name: SER description: 'Sector erase request Setting this bit requests a sector erase. Write protection error is triggered when a sector erase is required on at least one protected sector. BER has a higher priority than SER: if both bits are set, the embedded Flash memory executes a bank erase.' bit_offset: 2 bit_size: 1 - name: BER description: 'Bank erase request Setting this bit requests a bank erase operation (user Flash memory only). Write protection error is triggered when a bank erase is required and some sectors are protected. BER has a higher priority than SER: if both are set, the embedded Flash memory executes a bank erase.' bit_offset: 3 bit_size: 1 - name: FW description: 'Force write This bit forces a write operation even if the write buffer is not full. In this case all bits not written are set by hardware. The embedded Flash memory resets FW when the corresponding operation has been acknowledged. Note: Using a force-write operation prevents the application from updating later the missing bits with something else than 1, because it is likely that it will lead to permanent ECC error. Write forcing is effective only if the write buffer is not empty (in particular, FW does not start several write operations when the force-write operations are performed consecutively).' bit_offset: 4 bit_size: 1 - name: START description: Erase start control bit This bit is used to start a sector erase or a bank erase operation. The embedded Flash memory resets START when the corresponding operation has been acknowledged. The user application cannot access any embedded Flash memory register until the operation is acknowledged. bit_offset: 5 bit_size: 1 - name: SSN description: Sector erase selection number These bits are used to select the target sector for an erase operation (they are unused otherwise). ... bit_offset: 6 bit_size: 2 - name: PG_OTP description: Program Enable for OTP Area Set this bit to enable write operations to OTP area. bit_offset: 16 bit_size: 1 - name: CRC_EN description: CRC enable Setting this bit enables the CRC calculation. CRC_EN does not start CRC calculation but enables CRC configuration through FLASH_CRCCR register. When CRC calculation is performed it can be disabled by clearing CRC_EN bit. Doing so sets CRCDATA to 0x0, clears CRC configuration and resets the content of FLASH_CRCDATAR register. bit_offset: 17 bit_size: 1 - name: ALL_BANKS description: All banks select bit When this bit is set the erase is done on all Flash Memory sectors. ALL_BANKS is used only if a bank erase is required (BER=1). In all others operations, this control bit is ignored. bit_offset: 24 bit_size: 1 fieldset/CRCCR: description: FLASH CRC control register. fields: - name: CRC_SECT description: CRC sector number CRC_SECT is used to select one user Flash sectors to be added to the list of sectors on which the CRC is calculated. The CRC can be computed either between two addresses (using registers FLASH_CRCSADDR and FLASH_CRCEADDR) or on a list of sectors using this register. If this latter option is selected, it is possible to add a sector to the list of sectors by programming the sector number in CRC_SECT and then setting ADD_SECT bit. The list of sectors can be erased either by setting CLEAN_SECT bit or by disabling the CRC computation. ... bit_offset: 0 bit_size: 2 - name: CRC_BY_SECT description: CRC sector mode select bit When this bit is set the CRC calculation is performed at sector level, on the sectors present in the list of sectors. To add a sector to this list, use ADD_SECT and CRC_SECT bits. To clean the list, use CLEAN_SECT bit. When CRC_BY_SECT is cleared the CRC calculation is performed on all addresses defined between start and end addresses defined in FLASH_CRCSADDR and FLASH_CRCEADDR registers. bit_offset: 9 bit_size: 1 - name: ADD_SECT description: CRC sector select bit When this bit is set the sector whose number is written in CRC_SECT is added to the list of sectors on which the CRC is calculated. bit_offset: 10 bit_size: 1 - name: CLEAN_SECT description: CRC sector list clear bit When this bit is set the list of sectors on which the CRC is calculated is cleared. bit_offset: 11 bit_size: 1 - name: START_CRC description: CRC start bit START_CRC bit triggers a CRC calculation using the current configuration. No CRC calculation can launched when an option byte change operation is ongoing because all read accesses to embedded Flash memory registers are put on hold until the option byte change operation has completed. This bit is cleared when CRC computation starts. bit_offset: 16 bit_size: 1 - name: CLEAN_CRC description: CRC clear bit Setting CLEAN_CRC to 1 clears the current CRC result stored in the FLASH_CRCDATAR register. bit_offset: 17 bit_size: 1 - name: CRC_BURST description: CRC burst size CRC_BURST bits set the size of the bursts that are generated by the CRC calculation unit. A Flash word is 128-bit. bit_offset: 20 bit_size: 2 enum: CRC_BURST - name: ALL_SECT description: All sectors selection When this bit is set all the sectors in user Flash are added to list of sectors on which the CRC shall be calculated. This bit is cleared when CRC computation starts. bit_offset: 24 bit_size: 1 fieldset/CRCDATAR: description: FLASH CRC data register. fields: - name: CRC_DATA description: CRC result This bitfield contains the result of the last CRC calculation. The value is valid only when CRC calculation completed (CRCENDF is set in FLASH_ISR register). CRC_DATA is cleared when CRC_EN is cleared in FLASH_CR register (CRC disabled), or when CLEAN_CRC bit is set in FLASH_CRCCR register. bit_offset: 0 bit_size: 32 fieldset/CRCEADDR: description: FLASH CRC end address register. fields: - name: CRC_END_ADDR description: CRC end address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the Flash word starting the last burst of the CRC calculation. The burst size is defined in CRC_BURST of FLASH_CRCCR register. The least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. bit_offset: 6 bit_size: 11 fieldset/CRCSADDR: description: FLASH CRC start address register. fields: - name: CRC_START_ADDR description: CRC start address This register is used when CRC_BY_SECT is cleared. It must be programmed to the address of the first Flash word to use for the CRC calculation, done burst by burst. CRC computation starts at an address aligned to the burst size defined in CRC_BURST of FLASH_CRCCR register. Hence least significant bits [5:0] of the address are set by hardware to 0 (minimum burst size= 64 bytes). The address is relative to the Flash bank. bit_offset: 6 bit_size: 11 fieldset/ECCDFADDR: description: FLASH ECC double error fail address. fields: - name: DED_FADD description: ECC double error detection fail address When a double ECC detection occurs during a read operation, the DED_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when the DBECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC double error detection error is saved in this register. bit_offset: 0 bit_size: 32 fieldset/ECCSFADDR: description: FLASH ECC single error fail address. fields: - name: SEC_FADD description: ECC single error correction fail address When a single ECC error correction occurs during a read operation, the SEC_FADD bitfield contains the system bus address that generated the error. This register is automatically cleared when SNECCERRF flag that generated the error is cleared. Note that only the first address that generated an ECC single error correction error is saved in this register. bit_offset: 0 bit_size: 32 fieldset/EPOCHSR: description: FLASH epoch status register. fields: - name: EPOCH description: Epoch This value is distributed by hardware to the SAES peripheral. bit_offset: 0 bit_size: 24 fieldset/EPOCHSRP: description: FLASH RoT status register programming. fields: - name: EPOCH description: Epoch programming Write to change corresponding bits in FLASH_EPOCHSR register. bit_offset: 0 bit_size: 24 fieldset/FCR: description: FLASH status register. fields: - name: RCHECKF description: Root code check flag clear Set this bit to clear RCHECKF bit in FLASH_SR. bit_offset: 25 bit_size: 1 fieldset/HDPSR: description: FLASH hide protection status register. fields: - name: HDP_AREA_START description: Hide protection user Flash area start This option sets the start address that contains the first 256-byte block of the hide protection (HDP) area in user Flash area. If HDP_AREA_END=HDP_AREA_START all the sectors are protected. If HDP_AREA_END