block/TIM: description: Advanced-timers items: - name: CR1 description: control register 1 byte_offset: 0 fieldset: CR1 - name: CR2 description: control register 2 byte_offset: 4 fieldset: CR2 - name: SMCR description: slave mode control register byte_offset: 8 fieldset: SMCR - name: DIER description: DMA/Interrupt enable register byte_offset: 12 fieldset: DIER - name: SR description: status register byte_offset: 16 fieldset: SR - name: EGR description: event generation register byte_offset: 20 access: Write fieldset: EGR - name: CCMR_Input description: capture/compare mode register 1-2 (input mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Input - name: CCMR_Output description: capture/compare mode register 1-2 (output mode) array: len: 2 stride: 4 byte_offset: 24 fieldset: CCMR_Output - name: CCER description: capture/compare enable register byte_offset: 32 fieldset: CCER - name: CNT description: counter byte_offset: 36 fieldset: CNT - name: PSC description: prescaler byte_offset: 40 fieldset: PSC - name: ARR description: auto-reload register (Dither mode disabled) byte_offset: 44 fieldset: ARR - name: ARR_DITHER description: auto-reload register (Dither mode enabled) byte_offset: 44 fieldset: ARR_DITHER - name: RCR description: repetition counter register byte_offset: 48 fieldset: RCR - name: CCR description: capture/compare register x (x=1-4) (Dither mode disabled) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR - name: CCR_DITHER description: capture/compare register x (x=1-4) (Dither mode enabled) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_DITHER - name: ECR description: encoder control register byte_offset: 88 fieldset: ECR - name: TISEL description: input selection register byte_offset: 92 fieldset: TISEL - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1 - name: AF2 description: alternate function register 2 byte_offset: 100 fieldset: AF2 - name: DCR description: DMA control register byte_offset: 988 fieldset: DCR - name: DMAR description: DMA address for full transfer byte_offset: 992 fieldset: DMAR fieldset/AF1: description: alternate function register 1 fields: - name: ETRSEL description: etr_in source selection bit_offset: 14 bit_size: 4 fieldset/AF2: description: alternate function register 2 fields: - name: OCRSEL description: ocref_clr source selection bit_offset: 16 bit_size: 3 fieldset/ARR: description: auto-reload register (Dither mode disabled) fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 fieldset/ARR_DITHER: description: auto-reload register (Dither mode enabled) fields: - name: DITHER description: Dither value bit_offset: 0 bit_size: 4 - name: ARR description: Auto-reload value bit_offset: 4 bit_size: 16 fieldset/CCER: description: capture/compare enable register fields: - name: CCE description: Capture/Compare x (x=1-6) output enable bit_offset: 0 bit_size: 1 array: len: 6 stride: 4 - name: CCP description: Capture/Compare x (x=1-6) output Polarity bit_offset: 1 bit_size: 1 array: len: 6 stride: 4 - name: CCNP description: Capture/Compare x (x=1-4) output Polarity bit_offset: 3 bit_size: 1 array: len: 4 stride: 4 fieldset/CCMR_Input: description: capture/compare mode register x (x=1-2) (input mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 2 stride: 8 enum: CCMR_Input_CCS - name: ICPSC description: Input capture y prescaler bit_offset: 2 bit_size: 2 array: len: 2 stride: 8 - name: ICF description: Input capture y filter bit_offset: 4 bit_size: 4 array: len: 2 stride: 8 enum: FilterValue fieldset/CCMR_Output: description: capture/compare mode register x (x=1-3) (output mode) fields: - name: CCS description: Capture/Compare y selection bit_offset: 0 bit_size: 2 array: len: 2 stride: 8 enum: CCMR_Output_CCS - name: OCFE description: Output compare y fast enable bit_offset: 2 bit_size: 1 array: len: 2 stride: 8 - name: OCPE description: Output compare y preload enable bit_offset: 3 bit_size: 1 array: len: 2 stride: 8 - name: OCM description: Output compare y mode bit_offset: 4 bit_size: 3 array: len: 2 stride: 8 enum: OCM - name: OCCE description: Output compare y clear enable bit_offset: 7 bit_size: 1 array: len: 2 stride: 8 fieldset/CCR: description: capture/compare register x (x=1-4,6) (Dither mode disabled) fields: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 fieldset/CCR_DITHER: description: capture/compare register x (x=1-4,6) (Dither mode enabled) fields: - name: DITHER description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 4 - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 4 bit_size: 16 fieldset/CNT: description: counter fields: - name: CNT description: counter value bit_offset: 0 bit_size: 16 - name: UIFCPY description: UIF copy bit_offset: 31 bit_size: 1 fieldset/CR1: description: control register 1 fields: - name: CEN description: Counter enable bit_offset: 0 bit_size: 1 - name: UDIS description: Update disable bit_offset: 1 bit_size: 1 - name: URS description: Update request source bit_offset: 2 bit_size: 1 enum: URS - name: OPM description: One-pulse mode enbaled bit_offset: 3 bit_size: 1 - name: DIR description: Direction bit_offset: 4 bit_size: 1 enum: DIR - name: CMS description: Center-aligned mode selection bit_offset: 5 bit_size: 2 enum: CMS - name: ARPE description: Auto-reload preload enable bit_offset: 7 bit_size: 1 - name: CKD description: Clock division bit_offset: 8 bit_size: 2 enum: CKD - name: UIFREMAP description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - name: DITHEN description: Dithering enable bit_offset: 12 bit_size: 1 fieldset/CR2: description: control register 2 fields: - name: CCDS description: Capture/compare DMA selection bit_offset: 3 bit_size: 1 enum: CCDS - name: MMS description: Master mode selection bit_offset: 4 bit_size: 3 enum: MMS - name: TI1S description: TI1 selection bit_offset: 7 bit_size: 1 enum: TI1S fieldset/DCR: description: DMA control register fields: - name: DBA description: DMA base address bit_offset: 0 bit_size: 5 - name: DBL description: DMA burst length bit_offset: 8 bit_size: 5 - name: DBSS description: DMA burst source selection bit_offset: 16 bit_size: 4 enum: DBSS fieldset/DIER: description: DMA/Interrupt enable register fields: - name: UIE description: Update interrupt enable bit_offset: 0 bit_size: 1 - name: CCIE description: Capture/Compare 1 interrupt enable bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: TIE description: Trigger interrupt enable bit_offset: 6 bit_size: 1 - name: BIE description: Break interrupt enable bit_offset: 7 bit_size: 1 - name: UDE description: Update DMA request enable bit_offset: 8 bit_size: 1 - name: CCDE description: Capture/Compare x (x=1-4) DMA request enable bit_offset: 9 bit_size: 1 array: len: 4 stride: 1 - name: TDE description: Trigger DMA request enable bit_offset: 14 bit_size: 1 - name: IDXIE description: Index interrupt enable bit_offset: 20 bit_size: 1 - name: DIRIE description: Direction change interrupt enable bit_offset: 21 bit_size: 1 - name: IERRIE description: Index error interrupt enable bit_offset: 22 bit_size: 1 - name: TERRIE description: Transition error interrupt enable bit_offset: 23 bit_size: 1 fieldset/DMAR: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 fieldset/ECR: description: encoder control register fields: - name: IE description: Index enable bit_offset: 0 bit_size: 1 - name: IDIR description: Index direction bit_offset: 1 bit_size: 2 enum: IDIR - name: IBLK description: Index blanking bit_offset: 3 bit_size: 2 enum: IBLK - name: FIDX description: First index bit_offset: 5 bit_size: 1 enum: FIDX - name: IPOS description: Index positioning bit_offset: 6 bit_size: 2 - name: PW description: Pulse width bit_offset: 16 bit_size: 8 - name: PWPRSC description: Pulse width prescaler bit_offset: 24 bit_size: 2 fieldset/EGR: description: event generation register fields: - name: UG description: Update generation bit_offset: 0 bit_size: 1 - name: CCG description: Capture/compare x (x=1-4) generation bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: TG description: Trigger generation bit_offset: 6 bit_size: 1 fieldset/PSC: description: prescaler fields: - name: PSC description: Prescaler value bit_offset: 0 bit_size: 16 fieldset/RCR: description: repetition counter register fields: - name: REP description: Repetition counter value bit_offset: 0 bit_size: 16 fieldset/SMCR: description: slave mode control register fields: - name: SMS description: Slave mode selection bit_offset: 0 bit_size: 3 enum: SMS - name: TS description: Trigger selection bit_offset: 4 bit_size: 3 enum: TS - name: MSM description: Master/Slave mode bit_offset: 7 bit_size: 1 enum: MSM - name: ETF description: External trigger filter bit_offset: 8 bit_size: 4 enum: FilterValue - name: ETPS description: External trigger prescaler bit_offset: 12 bit_size: 2 enum: ETPS - name: ECE description: External clock mode 2 enable bit_offset: 14 bit_size: 1 - name: ETP description: External trigger polarity bit_offset: 15 bit_size: 1 enum: ETP - name: SMSPE description: SMS preload enable bit_offset: 24 bit_size: 1 - name: SMSPS description: SMS preload source bit_offset: 25 bit_size: 1 enum: SMSPS fieldset/SR: description: status register fields: - name: UIF description: Update interrupt flag bit_offset: 0 bit_size: 1 - name: CCIF description: Capture/compare x (x=1-4) interrupt flag bit_offset: 1 bit_size: 1 array: len: 4 stride: 1 - name: TIF description: Trigger interrupt flag bit_offset: 6 bit_size: 1 - name: CCOF description: Capture/Compare x (x=1-4) overcapture flag bit_offset: 9 bit_size: 1 array: len: 4 stride: 1 - name: IDXIF description: Index interrupt flag bit_offset: 20 bit_size: 1 - name: DIRIF description: Direction change interrupt flag bit_offset: 21 bit_size: 1 - name: IERRIF description: Index error interrupt flag bit_offset: 22 bit_size: 1 - name: TERRIF description: Transition error interrupt flag bit_offset: 23 bit_size: 1 fieldset/TISEL: description: input selection register fields: - name: TISEL description: Selects TIM_TIx (x=1-4) input bit_offset: 0 bit_size: 4 array: len: 4 stride: 8 enum/CCDS: bit_size: 1 variants: - name: OnCompare description: CCx DMA request sent when CCx event occurs value: 0 - name: OnUpdate description: CCx DMA request sent when update event occurs value: 1 enum/CCMR_Input_CCS: bit_size: 2 variants: - name: TI4 description: 'CCx channel is configured as input, normal mapping: ICx mapped to TIx' value: 1 - name: TI3 description: CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4) value: 2 - name: TRC description: CCx channel is configured as input, ICx is mapped on TRC value: 3 enum/CCMR_Output_CCS: bit_size: 2 variants: - name: Output description: CCx channel is configured as output value: 0 enum/CKD: bit_size: 2 variants: - name: Div1 description: t_DTS = t_CK_INT value: 0 - name: Div2 description: t_DTS = 2 × t_CK_INT value: 1 - name: Div4 description: t_DTS = 4 × t_CK_INT value: 2 enum/CMS: bit_size: 2 variants: - name: EdgeAligned description: The counter counts up or down depending on the direction bit value: 0 - name: CenterAligned1 description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down. value: 1 - name: CenterAligned2 description: The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up. value: 2 - name: CenterAligned3 description: The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down. value: 3 enum/DBSS: bit_size: 4 variants: - name: Update description: Update value: 1 - name: CC1 description: CC1 value: 2 - name: CC2 description: CC2 value: 3 - name: CC3 description: CC3 value: 4 - name: CC4 description: CC4 value: 5 - name: COM description: COM value: 6 - name: Trigger description: Trigger value: 7 enum/DIR: bit_size: 1 variants: - name: Up description: Counter used as upcounter value: 0 - name: Down description: Counter used as downcounter value: 1 enum/ETP: bit_size: 1 variants: - name: NotInverted description: ETR is noninverted, active at high level or rising edge value: 0 - name: Inverted description: ETR is inverted, active at low level or falling edge value: 1 enum/ETPS: bit_size: 2 variants: - name: Div1 description: Prescaler OFF value: 0 - name: Div2 description: ETRP frequency divided by 2 value: 1 - name: Div4 description: ETRP frequency divided by 4 value: 2 - name: Div8 description: ETRP frequency divided by 8 value: 3 enum/FIDX: bit_size: 1 variants: - name: AlwaysActive description: Index is always active value: 0 - name: FirstOnly description: the first Index only resets the counter value: 1 enum/FilterValue: bit_size: 4 variants: - name: NoFilter description: No filter, sampling is done at fDTS value: 0 - name: FCK_INT_N2 description: fSAMPLING=fCK_INT, N=2 value: 1 - name: FCK_INT_N4 description: fSAMPLING=fCK_INT, N=4 value: 2 - name: FCK_INT_N8 description: fSAMPLING=fCK_INT, N=8 value: 3 - name: FDTS_Div2_N6 description: fSAMPLING=fDTS/2, N=6 value: 4 - name: FDTS_Div2_N8 description: fSAMPLING=fDTS/2, N=8 value: 5 - name: FDTS_Div4_N6 description: fSAMPLING=fDTS/4, N=6 value: 6 - name: FDTS_Div4_N8 description: fSAMPLING=fDTS/4, N=8 value: 7 - name: FDTS_Div8_N6 description: fSAMPLING=fDTS/8, N=6 value: 8 - name: FDTS_Div8_N8 description: fSAMPLING=fDTS/8, N=8 value: 9 - name: FDTS_Div16_N5 description: fSAMPLING=fDTS/16, N=5 value: 10 - name: FDTS_Div16_N6 description: fSAMPLING=fDTS/16, N=6 value: 11 - name: FDTS_Div16_N8 description: fSAMPLING=fDTS/16, N=8 value: 12 - name: FDTS_Div32_N5 description: fSAMPLING=fDTS/32, N=5 value: 13 - name: FDTS_Div32_N6 description: fSAMPLING=fDTS/32, N=6 value: 14 - name: FDTS_Div32_N8 description: fSAMPLING=fDTS/32, N=8 value: 15 enum/IBLK: bit_size: 2 variants: - name: AlwaysActive description: Index always active value: 0 - name: CC3P description: Index disabled when tim_ti3 input is active, as per CC3P bitfield value: 1 - name: CC4P description: Index disabled when tim_ti4 input is active, as per CC4P bitfield value: 2 enum/IDIR: bit_size: 2 variants: - name: Both description: Index resets the counter whatever the direction value: 0 - name: Up description: Index resets the counter when up-counting only value: 1 - name: Down description: Index resets the counter when down-counting only value: 2 enum/MMS: bit_size: 3 variants: - name: Reset description: The UG bit from the TIMx_EGR register is used as trigger output value: 0 - name: Enable description: The counter enable signal, CNT_EN, is used as trigger output value: 1 - name: Update description: The update event is selected as trigger output value: 2 - name: ComparePulse description: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred value: 3 - name: CompareOC1 description: OC1REF signal is used as trigger output value: 4 - name: CompareOC2 description: OC2REF signal is used as trigger output value: 5 - name: CompareOC3 description: OC3REF signal is used as trigger output value: 6 - name: CompareOC4 description: OC4REF signal is used as trigger output value: 7 enum/MSM: bit_size: 1 variants: - name: NoSync description: No action value: 0 - name: Sync description: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. value: 1 enum/OCM: bit_size: 3 variants: - name: Frozen description: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs value: 0 - name: ActiveOnMatch description: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register value: 1 - name: InactiveOnMatch description: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register value: 2 - name: Toggle description: OCyREF toggles when TIMx_CNT=TIMx_CCRy value: 3 - name: ForceInactive description: OCyREF is forced low value: 4 - name: ForceActive description: OCyREF is forced high value: 5 - name: PwmMode1 description: In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active value: 6 - name: PwmMode2 description: Inversely to PwmMode1 value: 7 enum/SMS: bit_size: 3 variants: - name: Disabled description: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. value: 0 - name: Encoder_Mode_1 description: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. value: 1 - name: Encoder_Mode_2 description: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. value: 2 - name: Encoder_Mode_3 description: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. value: 3 - name: Reset_Mode description: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. value: 4 - name: Gated_Mode description: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. value: 5 - name: Trigger_Mode description: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. value: 6 - name: Ext_Clock_Mode description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. value: 7 enum/SMSPS: bit_size: 1 variants: - name: Update description: The transfer is triggered by the Timer’s Update event value: 0 - name: Index description: The transfer is triggered by the Index event value: 1 enum/TI1S: bit_size: 1 variants: - name: Normal description: The TIMx_CH1 pin is connected to TI1 input value: 0 - name: XOR description: The TIMx_CH1, CH2, CH3 pins are connected to TI1 input value: 1 enum/TS: bit_size: 3 variants: - name: ITR0 description: Internal Trigger 0 (ITR0) value: 0 - name: ITR1 description: Internal Trigger 1 (ITR1) value: 1 - name: ITR2 description: Internal Trigger 2 (ITR2) value: 2 - name: ITR3 description: Internal Trigger 3 (ITR3) value: 3 - name: TI1F_ED description: TI1 Edge Detector (TI1F_ED) value: 4 - name: TI1FP1 description: Filtered Timer Input 1 (TI1FP1) value: 5 - name: TI2FP2 description: Filtered Timer Input 2 (TI2FP2) value: 6 - name: ETRF description: External Trigger input (ETRF) value: 7 enum/URS: bit_size: 1 variants: - name: AnyEvent description: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request value: 0 - name: CounterOnly description: Only counter overflow/underflow generates an update interrupt or DMA request value: 1