--- block/RCC: description: Reset and clock control items: - name: CR description: Clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register byte_offset: 8 fieldset: CFGR - name: CIR description: Clock interrupt register byte_offset: 12 fieldset: CIR - name: AHBRSTR description: AHB peripheral reset register byte_offset: 16 fieldset: AHBRSTR - name: APB2RSTR description: APB2 peripheral reset register byte_offset: 20 fieldset: APB2RSTR - name: APB1RSTR description: APB1 peripheral reset register byte_offset: 24 fieldset: APB1RSTR - name: AHBENR description: AHB peripheral clock enable register byte_offset: 28 fieldset: AHBENR - name: APB2ENR description: APB2 peripheral clock enable register byte_offset: 32 fieldset: APB2ENR - name: APB1ENR description: APB1 peripheral clock enable register byte_offset: 36 fieldset: APB1ENR - name: AHBLPENR description: AHB peripheral clock enable in low power mode register byte_offset: 40 fieldset: AHBLPENR - name: APB2LPENR description: APB2 peripheral clock enable in low power mode register byte_offset: 44 fieldset: APB2LPENR - name: APB1LPENR description: APB1 peripheral clock enable in low power mode register byte_offset: 48 fieldset: APB1LPENR - name: CSR description: Control/status register byte_offset: 52 fieldset: CSR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - name: GPIOAEN description: IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: IO port C clock enable bit_offset: 2 bit_size: 1 - name: GPIODEN description: IO port D clock enable bit_offset: 3 bit_size: 1 - name: GPIOEEN description: IO port E clock enable bit_offset: 4 bit_size: 1 - name: GPIOHEN description: IO port H clock enable bit_offset: 5 bit_size: 1 - name: GPIOFEN description: IO port F clock enable bit_offset: 6 bit_size: 1 - name: GPIOGEN description: IO port G clock enable bit_offset: 7 bit_size: 1 - name: CRCEN description: CRC clock enable bit_offset: 12 bit_size: 1 - name: FLITFEN description: FLITF clock enable bit_offset: 15 bit_size: 1 - name: DMA1EN description: DMA1 clock enable bit_offset: 24 bit_size: 1 - name: DMA2EN description: DMA2 clock enable bit_offset: 25 bit_size: 1 - name: FSMCEN description: FSMCEN bit_offset: 30 bit_size: 1 fieldset/AHBLPENR: description: AHB peripheral clock enable in low power mode register fields: - name: GPIOALPEN description: IO port A clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: GPIOBLPEN description: IO port B clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: GPIOCLPEN description: IO port C clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: GPIODLPEN description: IO port D clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: GPIOELPEN description: IO port E clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: GPIOHLPEN description: IO port H clock enable during Sleep mode bit_offset: 5 bit_size: 1 - name: GPIOFLPEN description: IO port F clock enable during Sleep mode bit_offset: 6 bit_size: 1 - name: GPIOGLPEN description: IO port G clock enable during Sleep mode bit_offset: 7 bit_size: 1 - name: CRCLPEN description: CRC clock enable during Sleep mode bit_offset: 12 bit_size: 1 - name: FLITFLPEN description: FLITF clock enable during Sleep mode bit_offset: 15 bit_size: 1 - name: SRAMLPEN description: SRAM clock enable during Sleep mode bit_offset: 16 bit_size: 1 - name: DMA1LPEN description: DMA1 clock enable during Sleep mode bit_offset: 24 bit_size: 1 - name: DMA2LPEN description: DMA2 clock enable during Sleep mode bit_offset: 25 bit_size: 1 - name: AESLPEN description: AES clock enable during Sleep mode bit_offset: 27 bit_size: 1 - name: FSMCLPEN description: FSMC clock enable during Sleep mode bit_offset: 30 bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - name: GPIOARST description: IO port A reset bit_offset: 0 bit_size: 1 enum_write: FSMCRSTW - name: GPIOBRST description: IO port B reset bit_offset: 1 bit_size: 1 enum_write: FSMCRSTW - name: GPIOCRST description: IO port C reset bit_offset: 2 bit_size: 1 enum_write: FSMCRSTW - name: GPIODRST description: IO port D reset bit_offset: 3 bit_size: 1 enum_write: FSMCRSTW - name: GPIOERST description: IO port E reset bit_offset: 4 bit_size: 1 enum_write: FSMCRSTW - name: GPIOHRST description: IO port H reset bit_offset: 5 bit_size: 1 enum_write: FSMCRSTW - name: GPIOFRST description: IO port F reset bit_offset: 6 bit_size: 1 enum_write: FSMCRSTW - name: GPIOGRST description: IO port G reset bit_offset: 7 bit_size: 1 enum_write: FSMCRSTW - name: CRCRST description: CRC reset bit_offset: 12 bit_size: 1 enum_write: FSMCRSTW - name: FLITFRST description: FLITF reset bit_offset: 15 bit_size: 1 enum_write: FSMCRSTW - name: DMA1RST description: DMA1 reset bit_offset: 24 bit_size: 1 enum_write: FSMCRSTW - name: DMA2RST description: DMA2 reset bit_offset: 25 bit_size: 1 enum_write: FSMCRSTW - name: FSMCRST description: FSMC reset bit_offset: 30 bit_size: 1 enum_write: FSMCRSTW fieldset/APB1ENR: description: APB1 peripheral clock enable register fields: - name: TIM2EN description: Timer 2 clock enable bit_offset: 0 bit_size: 1 - name: TIM3EN description: Timer 3 clock enable bit_offset: 1 bit_size: 1 - name: TIM4EN description: Timer 4 clock enable bit_offset: 2 bit_size: 1 - name: TIM5EN description: Timer 5 clock enable bit_offset: 3 bit_size: 1 - name: TIM6EN description: Timer 6 clock enable bit_offset: 4 bit_size: 1 - name: TIM7EN description: Timer 7 clock enable bit_offset: 5 bit_size: 1 - name: LCDEN description: LCD clock enable bit_offset: 9 bit_size: 1 - name: WWDGEN description: Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN description: SPI 2 clock enable bit_offset: 14 bit_size: 1 - name: SPI3EN description: SPI 3 clock enable bit_offset: 15 bit_size: 1 - name: USART2EN description: USART 2 clock enable bit_offset: 17 bit_size: 1 - name: USART3EN description: USART 3 clock enable bit_offset: 18 bit_size: 1 - name: USART4EN description: UART 4 clock enable bit_offset: 19 bit_size: 1 - name: USART5EN description: UART 5 clock enable bit_offset: 20 bit_size: 1 - name: I2C1EN description: I2C 1 clock enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: I2C 2 clock enable bit_offset: 22 bit_size: 1 - name: USBEN description: USB clock enable bit_offset: 23 bit_size: 1 - name: PWREN description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: DACEN description: DAC interface clock enable bit_offset: 29 bit_size: 1 - name: COMPEN description: COMP interface clock enable bit_offset: 31 bit_size: 1 fieldset/APB1LPENR: description: APB1 peripheral clock enable in low power mode register fields: - name: TIM2LPEN description: Timer 2 clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: TIM3LPEN description: Timer 3 clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: TIM4LPEN description: Timer 4 clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: TIM5LPEN description: Timer 5 clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: TIM6LPEN description: Timer 6 clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: TIM7LPEN description: Timer 7 clock enable during Sleep mode bit_offset: 5 bit_size: 1 - name: LCDLPEN description: LCD clock enable during Sleep mode bit_offset: 9 bit_size: 1 - name: WWDGLPEN description: Window watchdog clock enable during Sleep mode bit_offset: 11 bit_size: 1 - name: SPI2LPEN description: SPI 2 clock enable during Sleep mode bit_offset: 14 bit_size: 1 - name: SPI3LPEN description: SPI 3 clock enable during Sleep mode bit_offset: 15 bit_size: 1 - name: USART2LPEN description: USART 2 clock enable during Sleep mode bit_offset: 17 bit_size: 1 - name: USART3LPEN description: USART 3 clock enable during Sleep mode bit_offset: 18 bit_size: 1 - name: UART4LPEN description: USART 4 clock enable during Sleep mode bit_offset: 19 bit_size: 1 - name: UART5LPEN description: USART 5 clock enable during Sleep mode bit_offset: 20 bit_size: 1 - name: I2C1LPEN description: I2C 1 clock enable during Sleep mode bit_offset: 21 bit_size: 1 - name: I2C2LPEN description: I2C 2 clock enable during Sleep mode bit_offset: 22 bit_size: 1 - name: USBLPEN description: USB clock enable during Sleep mode bit_offset: 23 bit_size: 1 - name: PWRLPEN description: Power interface clock enable during Sleep mode bit_offset: 28 bit_size: 1 - name: DACLPEN description: DAC interface clock enable during Sleep mode bit_offset: 29 bit_size: 1 - name: COMPLPEN description: COMP interface clock enable during Sleep mode bit_offset: 31 bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register fields: - name: TIM2RST description: Timer 2 reset bit_offset: 0 bit_size: 1 enum_write: COMPRSTW - name: TIM3RST description: Timer 3 reset bit_offset: 1 bit_size: 1 enum_write: COMPRSTW - name: TIM4RST description: Timer 4 reset bit_offset: 2 bit_size: 1 enum_write: COMPRSTW - name: TIM5RST description: Timer 5 reset bit_offset: 3 bit_size: 1 enum_write: COMPRSTW - name: TIM6RST description: Timer 6reset bit_offset: 4 bit_size: 1 enum_write: COMPRSTW - name: TIM7RST description: Timer 7 reset bit_offset: 5 bit_size: 1 enum_write: COMPRSTW - name: LCDRST description: LCD reset bit_offset: 9 bit_size: 1 enum_write: COMPRSTW - name: WWDRST description: Window watchdog reset bit_offset: 11 bit_size: 1 enum_write: COMPRSTW - name: SPI2RST description: SPI 2 reset bit_offset: 14 bit_size: 1 enum_write: COMPRSTW - name: SPI3RST description: SPI 3 reset bit_offset: 15 bit_size: 1 enum_write: COMPRSTW - name: USART2RST description: USART 2 reset bit_offset: 17 bit_size: 1 enum_write: COMPRSTW - name: USART3RST description: USART 3 reset bit_offset: 18 bit_size: 1 enum_write: COMPRSTW - name: UART4RST description: UART 4 reset bit_offset: 19 bit_size: 1 enum_write: COMPRSTW - name: UART5RST description: UART 5 reset bit_offset: 20 bit_size: 1 enum_write: COMPRSTW - name: I2C1RST description: I2C 1 reset bit_offset: 21 bit_size: 1 enum_write: COMPRSTW - name: I2C2RST description: I2C 2 reset bit_offset: 22 bit_size: 1 enum_write: COMPRSTW - name: USBRST description: USB reset bit_offset: 23 bit_size: 1 enum_write: COMPRSTW - name: PWRRST description: Power interface reset bit_offset: 28 bit_size: 1 enum_write: COMPRSTW - name: DACRST description: DAC interface reset bit_offset: 29 bit_size: 1 enum_write: COMPRSTW - name: COMPRST description: COMP interface reset bit_offset: 31 bit_size: 1 enum_write: COMPRSTW fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - name: SYSCFGEN description: System configuration controller clock enable bit_offset: 0 bit_size: 1 - name: TIM9EN description: TIM9 timer clock enable bit_offset: 2 bit_size: 1 - name: TIM10EN description: TIM10 timer clock enable bit_offset: 3 bit_size: 1 - name: TIM11EN description: TIM11 timer clock enable bit_offset: 4 bit_size: 1 - name: ADC1EN description: ADC1 interface clock enable bit_offset: 9 bit_size: 1 - name: SDIOEN description: SDIO clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: SPI 1 clock enable bit_offset: 12 bit_size: 1 - name: USART1EN description: USART1 clock enable bit_offset: 14 bit_size: 1 fieldset/APB2LPENR: description: APB2 peripheral clock enable in low power mode register fields: - name: SYSCFGLPEN description: System configuration controller clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: TIM9LPEN description: TIM9 timer clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: TIM10LPEN description: TIM10 timer clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: TIM11LPEN description: TIM11 timer clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: ADC1LPEN description: ADC1 interface clock enable during Sleep mode bit_offset: 9 bit_size: 1 - name: SDIOLPEN description: SDIO clock enable during Sleep mode bit_offset: 11 bit_size: 1 - name: SPI1LPEN description: SPI 1 clock enable during Sleep mode bit_offset: 12 bit_size: 1 - name: USART1LPEN description: USART1 clock enable during Sleep mode bit_offset: 14 bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: SYSCFGRST description: SYSCFGRST bit_offset: 0 bit_size: 1 enum_write: USARTRSTW - name: TIM9RST description: TIM9RST bit_offset: 2 bit_size: 1 enum_write: USARTRSTW - name: TM10RST description: TM10RST bit_offset: 3 bit_size: 1 enum_write: USARTRSTW - name: TM11RST description: TM11RST bit_offset: 4 bit_size: 1 enum_write: USARTRSTW - name: ADC1RST description: ADC1RST bit_offset: 9 bit_size: 1 enum_write: USARTRSTW - name: SDIORST description: SDIORST bit_offset: 11 bit_size: 1 enum_write: USARTRSTW - name: SPI1RST description: SPI1RST bit_offset: 12 bit_size: 1 enum_write: USARTRSTW - name: USART1RST description: USART1RST bit_offset: 14 bit_size: 1 enum_write: USARTRSTW fieldset/CFGR: description: Clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 enum_read: SWSR - name: HPRE description: AHB prescaler bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 description: APB low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE2 description: APB high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 enum: PPRE - name: PLLSRC description: PLL entry clock source bit_offset: 16 bit_size: 1 enum: PLLSRC - name: PLLMUL description: PLL multiplication factor bit_offset: 18 bit_size: 4 enum: PLLMUL - name: PLLDIV description: PLL output division bit_offset: 22 bit_size: 2 enum: PLLDIV - name: MCOSEL description: Microcontroller clock output selection bit_offset: 24 bit_size: 3 enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CIR: description: Clock interrupt register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 enum_read: MSIRDYFR - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 enum_read: MSIRDYFR - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 2 bit_size: 1 enum_read: MSIRDYFR - name: HSERDYF description: HSE ready interrupt flag bit_offset: 3 bit_size: 1 enum_read: MSIRDYFR - name: PLLRDYF description: PLL ready interrupt flag bit_offset: 4 bit_size: 1 enum_read: MSIRDYFR - name: MSIRDYF description: MSI ready interrupt flag bit_offset: 5 bit_size: 1 enum_read: MSIRDYFR - name: LSECSSF description: LSE Clock security system interrupt flag bit_offset: 6 bit_size: 1 enum_read: LSECSSFR - name: CSSF description: Clock security system interrupt flag bit_offset: 7 bit_size: 1 enum_read: CSSFR - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 8 bit_size: 1 enum: MSIRDYIE - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 9 bit_size: 1 enum: MSIRDYIE - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 10 bit_size: 1 enum: MSIRDYIE - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 11 bit_size: 1 enum: MSIRDYIE - name: PLLRDYIE description: PLL ready interrupt enable bit_offset: 12 bit_size: 1 enum: MSIRDYIE - name: MSIRDYIE description: MSI ready interrupt enable bit_offset: 13 bit_size: 1 enum: MSIRDYIE - name: LSECSSIE description: LSE clock security system interrupt enable bit_offset: 14 bit_size: 1 enum: LSECSSIE - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 16 bit_size: 1 enum_write: MSIRDYCW - name: LSERDYC description: LSE ready interrupt clear bit_offset: 17 bit_size: 1 enum_write: MSIRDYCW - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 18 bit_size: 1 enum_write: MSIRDYCW - name: HSERDYC description: HSE ready interrupt clear bit_offset: 19 bit_size: 1 enum_write: MSIRDYCW - name: PLLRDYC description: PLL ready interrupt clear bit_offset: 20 bit_size: 1 enum_write: MSIRDYCW - name: MSIRDYC description: MSI ready interrupt clear bit_offset: 21 bit_size: 1 enum_write: MSIRDYCW - name: LSECSSC description: LSE Clock security system interrupt clear bit_offset: 22 bit_size: 1 enum_write: CSSCW - name: CSSC description: Clock security system interrupt clear bit_offset: 23 bit_size: 1 enum_write: CSSCW fieldset/CR: description: Clock control register fields: - name: HSION description: Internal high-speed clock enable bit_offset: 0 bit_size: 1 - name: HSIRDY description: Internal high-speed clock ready flag bit_offset: 1 bit_size: 1 enum_read: HSERDYR - name: MSION description: MSI clock enable bit_offset: 8 bit_size: 1 - name: MSIRDY description: MSI clock ready flag bit_offset: 9 bit_size: 1 enum_read: HSERDYR - name: HSEON description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 enum_read: HSERDYR - name: HSEBYP description: HSE clock bypass bit_offset: 18 bit_size: 1 enum: HSEBYP - name: PLLON description: PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: PLL clock ready flag bit_offset: 25 bit_size: 1 enum_read: PLLRDYR - name: CSSON description: Clock security system enable bit_offset: 28 bit_size: 1 - name: RTCPRE description: TC/LCD prescaler bit_offset: 29 bit_size: 2 enum: RTCPRE fieldset/CSR: description: Control/status register fields: - name: LSION description: Internal low-speed oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: Internal low-speed oscillator ready bit_offset: 1 bit_size: 1 - name: LSEON description: External low-speed oscillator enable bit_offset: 8 bit_size: 1 - name: LSERDY description: External low-speed oscillator ready bit_offset: 9 bit_size: 1 - name: LSEBYP description: External low-speed oscillator bypass bit_offset: 10 bit_size: 1 - name: LSECSSON description: CSS on LSE enable bit_offset: 11 bit_size: 1 - name: LSECSSD description: CSS on LSE failure Detection bit_offset: 12 bit_size: 1 - name: RTCSEL description: RTC and LCD clock source selection bit_offset: 16 bit_size: 2 - name: RTCEN description: RTC clock enable bit_offset: 22 bit_size: 1 - name: RTCRST description: RTC software reset bit_offset: 23 bit_size: 1 enum_write: RTCRSTW - name: RMVF description: Remove reset flag bit_offset: 24 bit_size: 1 enum_write: RMVFW - name: OBLRSTF description: Options bytes loading reset flag bit_offset: 25 bit_size: 1 enum_read: LPWRSTFR - name: PINRSTF description: PIN reset flag bit_offset: 26 bit_size: 1 enum_read: LPWRSTFR - name: PORRSTF description: POR/PDR reset flag bit_offset: 27 bit_size: 1 enum_read: LPWRSTFR - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 enum_read: LPWRSTFR - name: IWDGRSTF description: Independent watchdog reset flag bit_offset: 29 bit_size: 1 enum_read: LPWRSTFR - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 enum_read: LPWRSTFR - name: LPWRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 enum_read: LPWRSTFR fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: HSICAL description: nternal high speed clock calibration bit_offset: 0 bit_size: 8 - name: HSITRIM description: High speed internal clock trimming bit_offset: 8 bit_size: 5 - name: MSIRANGE description: MSI clock ranges bit_offset: 13 bit_size: 3 - name: MSICAL description: MSI clock calibration bit_offset: 16 bit_size: 8 - name: MSITRIM description: MSI clock trimming bit_offset: 24 bit_size: 8 enum/COMPRSTW: bit_size: 1 variants: - name: Reset description: Reset the module value: 1 enum/CSSCW: bit_size: 1 variants: - name: Clear description: Clear interrupt value: 1 enum/CSSFR: bit_size: 1 variants: - name: NotInterupted description: No clock security interrupt caused by HSE clock failure value: 0 - name: Interupted description: Clock security interrupt caused by HSE clock failure value: 1 enum/FSMCRSTW: bit_size: 1 variants: - name: Reset description: Reset the module value: 1 enum/HPRE: bit_size: 4 variants: - name: Div1 description: system clock not divided value: 0 - name: Div2 description: system clock divided by 2 value: 8 - name: Div4 description: system clock divided by 4 value: 9 - name: Div8 description: system clock divided by 8 value: 10 - name: Div16 description: system clock divided by 16 value: 11 - name: Div64 description: system clock divided by 64 value: 12 - name: Div128 description: system clock divided by 128 value: 13 - name: Div256 description: system clock divided by 256 value: 14 - name: Div512 description: system clock divided by 512 value: 15 enum/HSEBYP: bit_size: 1 variants: - name: NotBypassed description: HSE oscillator not bypassed value: 0 - name: Bypassed description: HSE oscillator bypassed value: 1 enum/HSERDYR: bit_size: 1 variants: - name: NotReady description: Oscillator is not stable value: 0 - name: Ready description: Oscillator is stable value: 1 enum/LPWRSTFR: bit_size: 1 variants: - name: NoReset description: No reset has occured value: 0 - name: Reset description: A reset has occured value: 1 enum/LSECSSFR: bit_size: 1 variants: - name: NoFailure description: No failure detected on the external 32 KHz oscillator value: 0 - name: Failure description: A failure is detected on the external 32 kHz oscillator value: 1 enum/LSECSSIE: bit_size: 1 variants: - name: Disabled description: LSE CSS interrupt disabled value: 0 - name: Enabled description: LSE CSS interrupt enabled value: 1 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: No division value: 0 - name: Div2 description: Division by 2 value: 1 - name: Div4 description: Division by 4 value: 2 - name: Div8 description: Division by 8 value: 3 - name: Div16 description: Division by 16 value: 4 enum/MCOSEL: bit_size: 3 variants: - name: NoClock description: No clock value: 0 - name: SYSCLK description: SYSCLK clock selected value: 1 - name: HSI description: HSI oscillator clock selected value: 2 - name: MSI description: MSI oscillator clock selected value: 3 - name: HSE description: HSE oscillator clock selected value: 4 - name: PLL description: PLL clock selected value: 5 - name: LSI description: LSI oscillator clock selected value: 6 - name: LSE description: LSE oscillator clock selected value: 7 enum/MSIRDYCW: bit_size: 1 variants: - name: Clear description: Clear interrupt value: 1 enum/MSIRDYFR: bit_size: 1 variants: - name: NotStable description: Clock is not stable value: 0 - name: Stable description: Clock is stable value: 1 enum/MSIRDYIE: bit_size: 1 variants: - name: Disabled description: Interrupt disabled value: 0 - name: Enabled description: Interrupt enabled value: 1 enum/PLLDIV: bit_size: 2 variants: - name: Div2 description: PLLVCO / 2 value: 1 - name: Div3 description: PLLVCO / 3 value: 2 - name: Div4 description: PLLVCO / 4 value: 3 enum/PLLMUL: bit_size: 4 variants: - name: Mul3 description: PLL clock entry x 3 value: 0 - name: Mul4 description: PLL clock entry x 4 value: 1 - name: Mul6 description: PLL clock entry x 6 value: 2 - name: Mul8 description: PLL clock entry x 8 value: 3 - name: Mul12 description: PLL clock entry x 12 value: 4 - name: Mul16 description: PLL clock entry x 16 value: 5 - name: Mul24 description: PLL clock entry x 24 value: 6 - name: Mul32 description: PLL clock entry x 32 value: 7 - name: Mul48 description: PLL clock entry x 48 value: 8 enum/PLLRDYR: bit_size: 1 variants: - name: Unlocked description: PLL unlocked value: 0 - name: Locked description: PLL locked value: 1 enum/PLLSRC: bit_size: 1 variants: - name: HSI description: HSI selected as PLL input clock value: 0 - name: HSE description: HSE selected as PLL input clock value: 1 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK divided by 2 value: 4 - name: Div4 description: HCLK divided by 4 value: 5 - name: Div8 description: HCLK divided by 8 value: 6 - name: Div16 description: HCLK divided by 16 value: 7 enum/RMVFW: bit_size: 1 variants: - name: Clear description: Clears the reset flag value: 1 enum/RTCPRE: bit_size: 2 variants: - name: Div2 description: HSE divided by 2 value: 0 - name: Div4 description: HSE divided by 4 value: 1 - name: Div8 description: HSE divided by 8 value: 2 - name: Div16 description: HSE divided by 16 value: 3 enum/RTCRSTW: bit_size: 1 variants: - name: Reset description: Resets the RTC peripheral value: 1 enum/SW: bit_size: 2 variants: - name: HSI description: MSI oscillator used as system clock value: 0 - name: MSI description: HSI oscillator used as system clock value: 1 - name: HSE description: HSE oscillator used as system clock value: 2 - name: PLL description: PLL used as system clock value: 3 enum/SWSR: bit_size: 2 variants: - name: HSI description: MSI oscillator used as system clock value: 0 - name: MSI description: HSI oscillator used as system clock value: 1 - name: HSE description: HSE oscillator used as system clock value: 2 - name: PLL description: PLL used as system clock value: 3 enum/USARTRSTW: bit_size: 1 variants: - name: Reset description: Reset the module value: 1