block/RCC:
  description: Reset and clock control
  items:
  - name: CR
    description: RCC clock control register
    byte_offset: 0
    fieldset: CR
  - name: ICSCR3
    description: RCC internal clock sources calibration register 3
    byte_offset: 16
    fieldset: ICSCR3
  - name: CFGR1
    description: RCC clock configuration register 1
    byte_offset: 28
    fieldset: CFGR1
  - name: CFGR2
    description: RCC clock configuration register 2
    byte_offset: 32
    fieldset: CFGR2
  - name: CFGR3
    description: RCC clock configuration register 3
    byte_offset: 36
    fieldset: CFGR3
  - name: PLL1CFGR
    description: RCC PLL1 configuration register
    byte_offset: 40
    fieldset: PLL1CFGR
  - name: PLL1DIVR
    description: RCC PLL1 dividers register
    byte_offset: 52
    fieldset: PLL1DIVR
  - name: PLL1FRACR
    description: RCC PLL1 fractional divider register
    byte_offset: 56
    fieldset: PLL1FRACR
  - name: CIER
    description: RCC clock interrupt enable register
    byte_offset: 80
    fieldset: CIER
  - name: CIFR
    description: RCC clock interrupt flag register
    byte_offset: 84
    fieldset: CIFR
  - name: CICR
    description: RCC clock interrupt clear register
    byte_offset: 88
    fieldset: CICR
  - name: AHB1RSTR
    description: RCC AHB1 peripheral reset register
    byte_offset: 96
    fieldset: AHB1RSTR
  - name: AHB2RSTR
    description: RCC AHB2 peripheral reset register
    byte_offset: 100
    fieldset: AHB2RSTR
  - name: AHB4RSTR
    description: RCC AHB4 peripheral reset register
    byte_offset: 108
    fieldset: AHB4RSTR
  - name: AHB5RSTR
    description: RCC AHB5 peripheral reset register
    byte_offset: 112
    fieldset: AHB5RSTR
  - name: APB1RSTR1
    description: RCC APB1 peripheral reset register 1
    byte_offset: 116
    fieldset: APB1RSTR1
  - name: APB1RSTR2
    description: RCC APB1 peripheral reset register 2
    byte_offset: 120
    fieldset: APB1RSTR2
  - name: APB2RSTR
    description: RCC APB2 peripheral reset register
    byte_offset: 124
    fieldset: APB2RSTR
  - name: APB7RSTR
    description: RCC APB7 peripheral reset register
    byte_offset: 128
    fieldset: APB7RSTR
  - name: AHB1ENR
    description: RCC AHB1 peripheral clock enable register
    byte_offset: 136
    fieldset: AHB1ENR
  - name: AHB2ENR
    description: RCC AHB2 peripheral clock enable register
    byte_offset: 140
    fieldset: AHB2ENR
  - name: AHB4ENR
    description: RCC AHB4 peripheral clock enable register
    byte_offset: 148
    fieldset: AHB4ENR
  - name: AHB5ENR
    description: RCC AHB5 peripheral clock enable register
    byte_offset: 152
    fieldset: AHB5ENR
  - name: APB1ENR1
    description: RCC APB1 peripheral clock enable register 1
    byte_offset: 156
    fieldset: APB1ENR1
  - name: APB1ENR2
    description: RCC APB1 peripheral clock enable register 2
    byte_offset: 160
    fieldset: APB1ENR2
  - name: APB2ENR
    description: RCC APB2 peripheral clock enable register
    byte_offset: 164
    fieldset: APB2ENR
  - name: APB7ENR
    description: RCC APB7 peripheral clock enable register
    byte_offset: 168
    fieldset: APB7ENR
  - name: AHB1SMENR
    description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
    byte_offset: 176
    fieldset: AHB1SMENR
  - name: AHB2SMENR
    description: RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
    byte_offset: 180
    fieldset: AHB2SMENR
  - name: AHB4SMENR
    description: RCC AHB4 peripheral clocks enable in Sleep and Stop modes register
    byte_offset: 188
    fieldset: AHB4SMENR
  - name: AHB5SMENR
    description: RCC AHB5 peripheral clocks enable in Sleep and Stop modes register
    byte_offset: 192
    fieldset: AHB5SMENR
  - name: APB1SMENR1
    description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1"
    byte_offset: 196
    fieldset: APB1SMENR1
  - name: APB1SMENR2
    description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes \tregister 2"
    byte_offset: 200
    fieldset: APB1SMENR2
  - name: APB2SMENR
    description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
    byte_offset: 204
    fieldset: APB2SMENR
  - name: APB7SMENR
    description: RCC APB7 peripheral clock enable in Sleep and Stop modes register
    byte_offset: 208
    fieldset: APB7SMENR
  - name: CCIPR1
    description: RCC peripherals independent clock configuration register 1
    byte_offset: 224
    fieldset: CCIPR1
  - name: CCIPR2
    description: RCC peripherals independent clock configuration register 2
    byte_offset: 228
    fieldset: CCIPR2
  - name: CCIPR3
    description: RCC peripherals independent clock configuration register 3
    byte_offset: 232
    fieldset: CCIPR3
  - name: BDCR
    description: RCC backup domain control register
    byte_offset: 240
    fieldset: BDCR
  - name: CSR
    description: RCC control/status register
    byte_offset: 244
    fieldset: CSR
  - name: SECCFGR
    description: RCC secure configuration register
    byte_offset: 272
    fieldset: SECCFGR
  - name: PRIVCFGR
    description: RCC privilege configuration register
    byte_offset: 276
    fieldset: PRIVCFGR
  - name: CFGR4
    description: RCC clock configuration register 2
    byte_offset: 512
    fieldset: CFGR4
  - name: RADIOENR
    description: RCC RADIO peripheral clock enable register
    byte_offset: 520
    fieldset: RADIOENR
  - name: ECSCR1
    description: RCC external clock sources calibration register 1
    byte_offset: 528
    fieldset: ECSCR1
fieldset/AHB1ENR:
  description: RCC AHB1 peripheral clock enable register
  fields:
  - name: GPDMA1EN
    description: "GPDMA1 bus clock enable\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: FLASHEN
    description: "FLASH bus clock enable\r Set and cleared by software. This bit can be disabled only when the Flash memory is in power down mode.\r Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 8
    bit_size: 1
  - name: CRCEN
    description: "CRC bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 12
    bit_size: 1
  - name: TSCEN
    description: "Touch sensing controller bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 16
    bit_size: 1
  - name: RAMCFGEN
    description: "RAMCFG bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: GTZC1EN
    description: "GTZC1 bus clock enable \r Set and reset by software.\r Can only be accessed secure when device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 24
    bit_size: 1
  - name: SRAM1EN
    description: "SRAM1 bus clock enable \r Set and reset by software.\r Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 31
    bit_size: 1
fieldset/AHB1RSTR:
  description: RCC AHB1 peripheral reset register
  fields:
  - name: GPDMA1RST
    description: "GPDMA1 reset\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: CRCRST
    description: "CRC reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 12
    bit_size: 1
  - name: TSCRST
    description: "TSC reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 16
    bit_size: 1
fieldset/AHB1SMENR:
  description: RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - name: GPDMA1SMEN
    description: "GPDMA1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPDMA1 SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 0
    bit_size: 1
  - name: FLASHSMEN
    description: "FLASH bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secured when the Flash security state is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 8
    bit_size: 1
  - name: CRCSMEN
    description: "CRC bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC CRCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 12
    bit_size: 1
  - name: TSCSMEN
    description: "TSC bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TSCSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.."
    bit_offset: 16
    bit_size: 1
  - name: RAMCFGSMEN
    description: "RAMCFG bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RAMCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: GTZC1SMEN
    description: "GTZC1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one device is secure (TZEN = 1). When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 24
    bit_size: 1
  - name: ICACHESMEN
    description: "ICACHE bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ICACHE_REGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.."
    bit_offset: 29
    bit_size: 1
  - name: SRAM1SMEN
    description: "SRAM1 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB1 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 31
    bit_size: 1
fieldset/AHB2ENR:
  description: RCC AHB2 peripheral clock enable register
  fields:
  - name: GPIOAEN
    description: "IO port A bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: GPIOBEN
    description: "IO port B bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: GPIOCEN
    description: "IO port C bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 2
    bit_size: 1
  - name: GPIOHEN
    description: "IO port H bus clock enable\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 7
    bit_size: 1
  - name: AESEN
    description: "AES bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 16
    bit_size: 1
  - name: HASHEN
    description: "HASH bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: RNGEN
    description: "RNG bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 18
    bit_size: 1
  - name: SAESEN
    description: "SAES bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 19
    bit_size: 1
  - name: HSEMEN
    description: "HSEM bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 20
    bit_size: 1
  - name: PKAEN
    description: "PKA bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 21
    bit_size: 1
  - name: SRAM2EN
    description: "SRAM2 bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 30
    bit_size: 1
fieldset/AHB2RSTR:
  description: RCC AHB2 peripheral reset register
  fields:
  - name: GPIOARST
    description: "IO port A reset\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: GPIOBRST
    description: "IO port B reset\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: GPIOCRST
    description: "IO port C reset\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 2
    bit_size: 1
  - name: GPIOHRST
    description: "IO port H reset\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 7
    bit_size: 1
  - name: AESRST
    description: "AES hardware accelerator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 16
    bit_size: 1
  - name: HASHRST
    description: "Hash reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: RNGRST
    description: "Random number generator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 18
    bit_size: 1
  - name: SAESRST
    description: "SAES hardware accelerator reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 19
    bit_size: 1
  - name: HSEMRST
    description: "HSEM hardware accelerator reset\r Set and cleared by software.\r Can only be accessed secure when one or more features in the HSEM is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 20
    bit_size: 1
  - name: PKARST
    description: "PKA reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 21
    bit_size: 1
fieldset/AHB2SMENR:
  description: RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - name: GPIOASMEN
    description: "IO port A bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOA SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: GPIOBSMEN
    description: "IO port B bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOB SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: GPIOCSMEN
    description: "IO port C bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOC SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 2
    bit_size: 1
  - name: GPIOHSMEN
    description: "IO port H bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GPIOH SECx. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 7
    bit_size: 1
  - name: AESSMEN
    description: "AES bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC AESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 16
    bit_size: 1
  - name: HASHSMEN
    description: "HASH bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC HASHSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: RNGSMEN
    description: "Random number generator (RNG) bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 18
    bit_size: 1
  - name: SAESSMEN
    description: "SAES accelerator bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SAESSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 19
    bit_size: 1
  - name: PKASMEN
    description: "PKA bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC PKASEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 21
    bit_size: 1
  - name: SRAM2SMEN
    description: "SRAM2 bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_MPCBB2 SECx, INVSECSTATE. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 30
    bit_size: 1
fieldset/AHB4ENR:
  description: RCC AHB4 peripheral clock enable register
  fields:
  - name: PWREN
    description: "PWR bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 2
    bit_size: 1
  - name: ADC4EN
    description: "ADC4 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 5
    bit_size: 1
fieldset/AHB4RSTR:
  description: RCC AHB4 peripheral reset register
  fields:
  - name: ADC4RST
    description: "ADC4 reset\r Set and cleared by software.\r Access can be secred by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 5
    bit_size: 1
fieldset/AHB4SMENR:
  description: RCC AHB4 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - name: PWRSMEN
    description: "PWR bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 2
    bit_size: 1
  - name: ADC4SMEN
    description: "ADC4 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 5
    bit_size: 1
fieldset/AHB5ENR:
  description: RCC AHB5 peripheral clock enable register
  fields:
  - name: RADIOEN
    description: "2.4 GHz RADIO bus clock enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Before accessing the 2.4 GHz RADIO sleep timers registers the RADIOCLKRDY bit must be checked.\r Note: When RADIOSMEN and STRADIOCLKON are both cleared, RADIOCLKRDY bit must be re-checked when exiting low-power modes (Sleep and Stop)."
    bit_offset: 0
    bit_size: 1
fieldset/AHB5RSTR:
  description: RCC AHB5 peripheral reset register
  fields:
  - name: RADIORST
    description: "2.4 GHz RADIO reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
fieldset/AHB5SMENR:
  description: RCC AHB5 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - name: RADIOSMEN
    description: "2.4 GHz RADIO bus clock enable during Sleep and Stop modes when the 2.4 GHz RADIO is active.\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
fieldset/APB1ENR1:
  description: RCC APB1 peripheral clock enable register 1
  fields:
  - name: TIM2EN
    description: "TIM2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: TIM3EN
    description: "TIM3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: WWDGEN
    description: "WWDG bus clock enable\r Set by software to enable the window watchdog bus clock. Reset by hardware system reset.\r This bit can also be set by hardware if the WWDG_SW option bit is reset.\r Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
  - name: USART2EN
    description: "USART2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART2SEC When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.."
    bit_offset: 17
    bit_size: 1
  - name: I2C1EN
    description: "I2C1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 21
    bit_size: 1
fieldset/APB1ENR2:
  description: RCC APB1 peripheral clock enable register 2
  fields:
  - name: LPTIM2EN
    description: "LPTIM2 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 5
    bit_size: 1
fieldset/APB1RSTR1:
  description: RCC APB1 peripheral reset register 1
  fields:
  - name: TIM2RST
    description: "TIM2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: TIM3RST
    description: "TIM3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: USART2RST
    description: "USART2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: I2C1RST
    description: "I2C1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 21
    bit_size: 1
fieldset/APB1RSTR2:
  description: RCC APB1 peripheral reset register 2
  fields:
  - name: LPTIM2RST
    description: "LPTIM2 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 5
    bit_size: 1
fieldset/APB1SMENR1:
  description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes\tregister 1"
  fields:
  - name: TIM2SMEN
    description: "TIM2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: TIM3SMEN
    description: "TIM3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: WWDGSMEN
    description: "Window watchdog bus clock enable during Sleep and Stop modes\r Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG option is activated.\r Access can be secured by GTZC_TZSC WWDGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
  - name: USART2SMEN
    description: "USART2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 17
    bit_size: 1
  - name: I2C1SMEN
    description: "I2C1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 21
    bit_size: 1
fieldset/APB1SMENR2:
  description: "RCC APB1 peripheral clocks enable in Sleep and Stop modes \tregister 2"
  fields:
  - name: LPTIM2SMEN
    description: "LPTIM2 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 5
    bit_size: 1
fieldset/APB2ENR:
  description: RCC APB2 peripheral clock enable register
  fields:
  - name: TIM1EN
    description: "TIM1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
  - name: SPI1EN
    description: "SPI1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 12
    bit_size: 1
  - name: USART1EN
    description: "USART1bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 14
    bit_size: 1
  - name: TIM16EN
    description: "TIM16 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: TIM17EN
    description: "TIM17 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 18
    bit_size: 1
fieldset/APB2RSTR:
  description: RCC APB2 peripheral reset register
  fields:
  - name: TIM1RST
    description: "TIM1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
  - name: SPI1RST
    description: "SPI1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 12
    bit_size: 1
  - name: USART1RST
    description: "USART1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 14
    bit_size: 1
  - name: TIM16RST
    description: "TIM16 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: TIM17RST
    description: "TIM17 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 18
    bit_size: 1
fieldset/APB2SMENR:
  description: RCC APB2 peripheral clocks enable in Sleep and Stop modes register
  fields:
  - name: TIM1SMEN
    description: "TIM1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
  - name: SPI1SMEN
    description: "SPI1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 12
    bit_size: 1
  - name: USART1SMEN
    description: "USART1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 14
    bit_size: 1
  - name: TIM16SMEN
    description: "TIM16 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM16SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: TIM17SMEN
    description: "TIM17 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC TIM17SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 18
    bit_size: 1
fieldset/APB7ENR:
  description: RCC APB7 peripheral clock enable register
  fields:
  - name: SYSCFGEN
    description: "SYSCFG bus clock enable\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: SPI3EN
    description: "SPI3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 5
    bit_size: 1
  - name: LPUART1EN
    description: "LPUART1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 6
    bit_size: 1
  - name: I2C3EN
    description: "I2C3 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 7
    bit_size: 1
  - name: LPTIM1EN
    description: "LPTIM1 bus and kernel clocks enable\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
  - name: RTCAPBEN
    description: "RTC and TAMP bus clock enable\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 21
    bit_size: 1
fieldset/APB7RSTR:
  description: RCC APB7 peripheral reset register
  fields:
  - name: SYSCFGRST
    description: "SYSCFG reset\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: SPI3RST
    description: "SPI3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 5
    bit_size: 1
  - name: LPUART1RST
    description: "LPUART1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 6
    bit_size: 1
  - name: I2C3RST
    description: "I2C3 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 7
    bit_size: 1
  - name: LPTIM1RST
    description: "LPTIM1 reset\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
fieldset/APB7SMENR:
  description: RCC APB7 peripheral clock enable in Sleep and Stop modes register
  fields:
  - name: SYSCFGSMEN
    description: "SYSCFG bus clock enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by SYSCFG SYSCFGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: SPI3SMEN
    description: "SPI3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 5
    bit_size: 1
  - name: LPUART1SMEN
    description: "LPUART1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 6
    bit_size: 1
  - name: I2C3SMEN
    description: "I2C3 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 7
    bit_size: 1
  - name: LPTIM1SMEN
    description: "LPTIM1 bus and kernel clocks enable during Sleep and Stop modes\r Set and cleared by software.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 11
    bit_size: 1
  - name: RTCAPBSMEN
    description: "RTC and TAMP APB clock enable during Sleep and Stop modes\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: This bit must be set to allow the peripheral to wake up from Stop modes."
    bit_offset: 21
    bit_size: 1
fieldset/BDCR:
  description: RCC backup domain control register
  fields:
  - name: LSEON
    description: "LSE oscillator enable\r Set and cleared by software.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: LSERDY
    description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32�kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: LSEBYP
    description: "LSE oscillator bypass\r Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32�kHz oscillator is disabled (LSEON = 0 and LSERDY = 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 2
    bit_size: 1
  - name: LSEDRV
    description: "LSE oscillator drive capability\r Set by software to modulate the drive capability of the LSE oscillator. LSEDRV must be programmed to a different value than 0 before enabling the LSE oscillator in ‘Xtal’ mode.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The oscillator is in ‘Xtal mode’ when it is not in bypass mode."
    bit_offset: 3
    bit_size: 2
    enum: LSEDRV
  - name: LSECSSON
    description: "Low speed external clock security enable\r Set by software to enable the LSECSS. LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware) and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD�=�1). In that case, the software must disable the LSECSSON bit.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 5
    bit_size: 1
  - name: LSECSSD
    description: "Low speed external clock security, LSE failure Detection\r Set by hardware to indicate when a failure is detected by the LSECCS on the external 32�kHz oscillator.\r Reset when LSCSSON bit is cleared.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 6
    bit_size: 1
  - name: LSESYSEN
    description: "LSE system clock (LSESYS) enable\r Set by software to enable the LSE system clock generated by RCC. The lsesys clock is used for peripherals (USART, LPUART, LPTIM, RNG, 2.4 GHz RADIO) and functions (LSCO, MCO, TIM triggers, LPTIM trigger) excluding the RTC, TAMP and LSECSS.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 7
    bit_size: 1
  - name: RTCSEL
    description: "RTC and TAMP kernel clock source enable and selection\r Set by software to enable and select the clock source for the RTC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 8
    bit_size: 2
    enum: RTCSEL
  - name: LSESYSRDY
    description: "LSE system clock (LSESYS) ready\r Set and cleared by hardware to indicate when the LSE system clock is stable.When the LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.\r The LSE clock must be already enabled and stable (LSEON and LSERDY are set). \r When the LSEON bit is cleared, LSERDY goes low after six external low-speed oscillator clock cycles.\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 11
    bit_size: 1
  - name: LSEGFON
    description: "LSE clock glitch filter enable\r Set and cleared by hardware to enable the LSE glitch filter. This bit can be written only when the LSE is disabled (LSEON = 0 and LSERDY = 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 12
    bit_size: 1
  - name: LSETRIM
    description: "LSE trimming\r These bits are initialized at startup and after OBL_LAUNCH with SBF cleared with the factory-programmed LSE calibration value.\r Set and cleared by software. These bits must be modified only once after a BOR reset or an OBL_LAUNCH and before enabling LSE with LSEON (when both LSEON = 0 and LSERDY�= 0).\r Access can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: OBL_LAUNCH of this field occurs only when SBF is cleared and must then only be started by software when LSE oscillator is disabled, LSEON = 0 and LSERDY = 0."
    bit_offset: 13
    bit_size: 2
    enum: LSETRIM
  - name: BDRST
    description: "Backup domain software reset\r Set and cleared by software.\r Can only be accessed secure when one or more features in the RTC or TAMP is secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 16
    bit_size: 1
  - name: RADIOSTSEL
    description: "2.4 GHz RADIO sleep timer kernel clock enable and selection\r Set and cleared by software.\r Access can be secured by GTZC_TZSC RADIOSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 18
    bit_size: 2
    enum: RADIOSTSEL
  - name: LSCOEN
    description: "Low-speed clock output (LSCO) enable\r Set and cleared by software.\r Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 24
    bit_size: 1
  - name: LSCOSEL
    description: "Low-speed clock output selection\r Set and cleared by software.\r Access can be secured by RCC LSISEC and/or RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 25
    bit_size: 1
    enum: LSCOSEL
  - name: LSI1ON
    description: "LSI1 oscillator enable\r Set and cleared by software.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 26
    bit_size: 1
  - name: LSI1RDY
    description: "LSI1 oscillator ready\r Set and cleared by hardware to indicate when the LSI1 oscillator is stable. After the LSI1ON bit is cleared, LSI1RDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI1 is used by IWDG or RTC, even if LSI1ON = 0.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 27
    bit_size: 1
  - name: LSI1PREDIV
    description: "LSI1 Low-speed clock divider configuration\r Set and cleared by software to enable the LSI1 division. This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC.\r Access can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 28
    bit_size: 1
    enum: LSIPREDIV
fieldset/CCIPR1:
  description: RCC peripherals independent clock configuration register 1
  fields:
  - name: USART1SEL
    description: "USART1 kernel clock source selection\r This bits are used to select the USART1 kernel clock source.\r Access can be secured by GTZC_TZSC USART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE."
    bit_offset: 0
    bit_size: 2
    enum: USARTSEL
  - name: USART2SEL
    description: "USART2 kernel clock source selection\r This bits are used to select the USART2 kernel clock source.\r Access can be secured by GTZC_TZSC USART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The USART2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16 or LSE."
    bit_offset: 2
    bit_size: 2
    enum: USARTSEL
  - name: I2C1SEL
    description: "I2C1 kernel clock source selection\r These bits are used to select the I2C1 kernel clock source.\r Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16."
    bit_offset: 10
    bit_size: 2
    enum: ICSEL
  - name: LPTIM2SEL
    description: "Low-power timer 2 kernel clock source selection\r These bits are used to select the LPTIM2 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM2 is functional in Stop 0 and Stop 1 mode only when the kernel clock is LSI, LSE or HSI16 if HSIKERON = 1."
    bit_offset: 18
    bit_size: 2
    enum: LPTIMSEL
  - name: SPI1SEL
    description: "SPI1 kernel clock source selection\r These bits are used to select the SPI1 kernel clock source.\r Access can be secured by GTZC_TZSC SPI1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI1 is functional in Stop 0 and Stop 1 mode only when the kernel clock is HSI16."
    bit_offset: 20
    bit_size: 2
    enum: SPISEL
  - name: SYSTICKSEL
    description: "SysTick clock source selection\r These bits are used to select the SysTick clock source.\r Access can be secured by RCC SYSCLKSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: When LSE or LSI is selected, the AHB frequency must be at least four times higher than the LSI or LSE frequency. In addition, a jitter up to one hclk1 cycle is introduced, due to the LSE or LSI sampling with hclk1 in the SysTick circuitry."
    bit_offset: 22
    bit_size: 2
    enum: SYSTICKSEL
  - name: TIMICSEL
    description: "Clocks sources for TIM16,TIM17 and LPTIM2 internal input capture \r When the TIMICSEL bit is set, the TIM16, TIM17 and LPTIM2 internal input capture can be connected to HSI16/256. \r When TIMICSEL is cleared, the HSI16, clock sources cannot be selected as TIM16, TIM17 or LPTIM2 internal input capture.\r Access can be secured by GTZC_TZSC TIM16SEC, TIM17SEC, or LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The clock division must be disabled (TIMICSEL configured to 0) before selecting or changing a clock sources division."
    bit_offset: 31
    bit_size: 1
    enum: TIMICSEL
fieldset/CCIPR2:
  description: RCC peripherals independent clock configuration register 2
  fields:
  - name: RNGSEL
    description: "RNGSEL kernel clock source selection\r These bits allow to select the RNG kernel clock source.\r Access can be secured by GTZC_TZSC RNGSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 12
    bit_size: 2
    enum: RNGSEL
fieldset/CCIPR3:
  description: RCC peripherals independent clock configuration register 3
  fields:
  - name: LPUART1SEL
    description: "LPUART1 kernel clock source selection\r These bits are used to select the LPUART1 kernel clock source.\r Access can be secured by GTZC_TZSC LPUART1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPUART1 is functional in Stop modes only when the kernel clock is HSI16 or LSE."
    bit_offset: 0
    bit_size: 2
    enum: LPUARTSEL
  - name: SPI3SEL
    description: "SPI3 kernel clock source selection\r These bits are used to select the SPI3 kernel clock source.\r Access can be secured by GTZC_TZSC SPI3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The SPI3 is functional in Stop modes only when the kernel clock is HSI16."
    bit_offset: 3
    bit_size: 2
    enum: SPISEL
  - name: I2C3SEL
    description: "I2C3 kernel clock source selection\r These bits are used to select the I2C3 kernel clock source.\r Access can be secured by GTZC_TZSC I2C3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The I2C3 is functional in Stop modes only when the kernel clock is HSI16"
    bit_offset: 6
    bit_size: 2
    enum: ICSEL
  - name: LPTIM1SEL
    description: "LPTIM1 kernel clock source selection\r These bits are used to select the LPTIM1 kernel clock source.\r Access can be secured by GTZC_TZSC LPTIM1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: The LPTIM1 is functional in Stop modes only when the kernel clock is LSI, LSE, HSI16 with HSIKERON = 1."
    bit_offset: 10
    bit_size: 2
    enum: LPTIMSEL
  - name: ADCSEL
    description: "ADC4 kernel clock source selection\r These bits are used to select the ADC4 kernel clock source.\r Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r others: reserved\r Note: The ADC4 is functional in Stop modes only when the kernel clock is HSI16."
    bit_offset: 12
    bit_size: 3
    enum: ADCSEL
fieldset/CFGR1:
  description: RCC clock configuration register 1
  fields:
  - name: SW
    description: "system clock switch\r Set and cleared by software to select system clock source (SYSCLK).\r Cleared by hardware when entering Stop and Standby modes\r When selecting HSE directly or indirectly as system clock and HSE oscillator clock security fails, cleared by hardware."
    bit_offset: 0
    bit_size: 2
    enum: SW
  - name: SWS
    description: "system clock switch status\r Set and cleared by hardware to indicate which clock source is used as system clock."
    bit_offset: 2
    bit_size: 2
    enum: SW
  - name: MCOSEL
    description: "microcontroller clock output\r Set and cleared by software.\r others: reserved\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching."
    bit_offset: 24
    bit_size: 4
    enum: MCOSEL
  - name: MCOPRE
    description: "microcontroller clock output prescaler\r Set and cleared by software.\r It is highly recommended to change this prescaler before MCO output is enabled.\r others: not allowed"
    bit_offset: 28
    bit_size: 3
    enum: MCOPRE
fieldset/CFGR2:
  description: RCC clock configuration register 2
  fields:
  - name: HPRE
    description: "AHB1, AHB2 and AHB4 prescaler\r Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1).\r The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xx: hclk1 = SYSCLK not divided"
    bit_offset: 0
    bit_size: 3
    enum: HPRE
  - name: PPRE1
    description: "APB1 prescaler\r Set and cleared by software to control the division factor of the APB1 clock (pclk1).\r 0xx: pclk1 = hclk1 not divided"
    bit_offset: 4
    bit_size: 3
    enum: PPRE
  - name: PPRE2
    description: "APB2 prescaler\r Set and cleared by software to control the division factor of the APB2 clock (pclk2).\r 0xx: pclk2 = hclk1 not divided"
    bit_offset: 8
    bit_size: 3
    enum: PPRE
fieldset/CFGR3:
  description: RCC clock configuration register 3
  fields:
  - name: PPRE7
    description: "APB7 prescaler\r Set and cleared by software to control the division factor of the APB7 clock (pclk7).\r 0xx: hclk1 not divided"
    bit_offset: 4
    bit_size: 3
    enum: PPRE
fieldset/CFGR4:
  description: RCC clock configuration register 2
  fields:
  - name: HPRE5
    description: "AHB5 prescaler when SWS select PLL1\r Set and cleared by software to control the division factor of the AHB5 clock (hclk5).\r Must not be changed when SYSCLK source indicated by SWS is PLL1.\r When SYSCLK source indicated by SWS is not PLL1: HPRE5 is not taken into account.\r When SYSCLK source indicated by SWS is PLL1: HPRE5 is taken into account, from the moment the system clock switch occurs\r Depending on the device voltage range, the software must set these bits correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account.\r 0xx: hclk5 = SYSCLK not divided"
    bit_offset: 0
    bit_size: 3
    enum: HPRE5
  - name: HDIV5
    description: "AHB5 divider when SWS select HSI16 or HSE\r Set and reset by software.\r Set to 1 by hardware when entering Stop 1 mode.\r When SYSCLK source indicated by SWS is HSI16 or HSE: HDIV5 is taken into account\r When SYSCLK source indicated by SWS is PLL1: HDIV5 is taken not taken into account\r Depending on the device voltage range, the software must set this bit correctly to ensure that the AHB5 frequency does not exceed the maximum allowed frequency (for more details, refer to Table�99). After a write operation to this bit and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account."
    bit_offset: 4
    bit_size: 1
    enum: HDIV5
fieldset/CICR:
  description: RCC clock interrupt clear register
  fields:
  - name: LSI1RDYC
    description: "LSI1 ready interrupt clear\r Writing this bit to 1 clears the LSI1RDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: LSERDYC
    description: "LSE ready interrupt clear\r Writing this bit to 1 clears the LSERDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: HSIRDYC
    description: "HSI16 ready interrupt clear\r Writing this bit to 1 clears the HSIRDYF flag. Writing 0 has no effect.\\\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 3
    bit_size: 1
  - name: HSERDYC
    description: "HSE ready interrupt clear\r Writing this bit to 1 clears the HSERDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 4
    bit_size: 1
  - name: PLLRDYC
    description: "PLL1 ready interrupt clear\r Writing this bit to 1 clears the PLL1RDYF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 6
    bit_size: 1
  - name: HSECSSC
    description: "High speed external clock security system interrupt clear\r Writing this bit to 1 clears the HSECSSF flag. Writing 0 has no effect.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 10
    bit_size: 1
fieldset/CIER:
  description: RCC clock interrupt enable register
  fields:
  - name: LSI1RDYIE
    description: "LSI1 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI1 oscillator stabilization.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: LSERDYIE
    description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: HSIRDYIE
    description: "HSI16 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator stabilization.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 3
    bit_size: 1
  - name: HSERDYIE
    description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 4
    bit_size: 1
  - name: PLLRDYIE
    description: "PLL1 ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by PLL1 lock.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 6
    bit_size: 1
fieldset/CIFR:
  description: RCC clock interrupt flag register
  fields:
  - name: LSI1RDYF
    description: "LSI1 ready interrupt flag\r Set by hardware when the LSI1 clock becomes stable and LSI1RDYIE is set.\r Cleared by software setting the LSI1RDYC bit.\r Access to the bit can be secured by RCC LSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 0
    bit_size: 1
  - name: LSERDYF
    description: "LSE ready interrupt flag\r Set by hardware when the LSE clock becomes stable and LSERDYIE is set.\r Cleared by software setting the LSERDYC bit.\r Access to the bit can be secured by RCC LSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 1
    bit_size: 1
  - name: HSIRDYF
    description: "HSI16 ready interrupt flag\r Set by hardware when the HSI16 clock becomes stable and HSIRDYIE is set in a response to setting the HSION (see CR). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Cleared by software setting the HSIRDYC bit."
    bit_offset: 3
    bit_size: 1
  - name: HSERDYF
    description: "HSE ready interrupt flag\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 4
    bit_size: 1
  - name: PLLRDYF
    description: "PLL1 ready interrupt flag\r Set by hardware when the PLL1 locks and PLL1RDYIE is set.\r Cleared by software setting the PLL1RDYC bit.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 6
    bit_size: 1
  - name: HSECSSF
    description: "HSE clock security system interrupt flag\r Set by hardware when a clock security failure is detected in the HSE oscillator.\r Cleared by software setting the HSECSSC bit.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 10
    bit_size: 1
fieldset/CR:
  description: RCC clock control register
  fields:
  - name: HSION
    description: "HSI16 clock enable\r Set and cleared by software.\r Cleared by hardware when entering Stop and Standby modes. \r Set by hardware to force the HSI16 oscillator on when exiting Stop and Standby modes.\r Set by hardware to force the HSI16 oscillator on in case of clock security failure of the HSE crystal oscillator.\r This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 8
    bit_size: 1
  - name: HSIKERON
    description: "HSI16 enable for some peripheral kernels\r Set and cleared by software to force HSI16 oscillator on even in Stop modes. \r Keeping the HSI16 oscillator on in Stop modes allows the communication speed not to be reduced by the HSI16 oscillator startup time. This bit has no effect on register bit HSION value.\r Cleared by hardware when entering Standby modes. \r Refer to Peripherals clock gating and autonomous mode for more details.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 9
    bit_size: 1
  - name: HSIRDY
    description: "HSI16 clock ready flag\r Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is enabled by software by setting HSION.\r Access to the bit can be secured by RCC HSISEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.\r Note: Once the HSION bit is cleared, HSIRDY goes low after six HSI16 clock cycles."
    bit_offset: 10
    bit_size: 1
  - name: HSEON
    description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE clock for the CPU when entering Stop and Standby modes and on a HSECSS failure.\r When the HSE is used as 2.4 GHz RADIO kernel clock, enabled by RADIOEN and RADIOSMEN and the 2.4 GHz RADIO is active, HSEON is not be cleared when entering low power mode. In this case only Stop 0 mode is entered as low power mode.\r This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 16
    bit_size: 1
  - name: HSERDY
    description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable. This bit is set both when HSE is enabled by software by setting HSEON and when requested as kernel clock by the 2.4 GHz RADIO.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 17
    bit_size: 1
  - name: HSECSSON
    description: "HSE clock security system enable\r Set by software to enable the HSE clock security system. When HSECSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready and disabled by hardware if a HSE clock failure is detected. This bit is set only and is cleared by reset.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 19
    bit_size: 1
  - name: HSEPRE
    description: "HSE clock for SYSCLK prescaler\r Set and cleared by software to control the division factor of the HSE clock for SYSCLK.\r Access to the bit can be secured by RCC HSESEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 20
    bit_size: 1
    enum: HSEPRE
  - name: PLLON
    description: "PLL1 enable\r Set and cleared by software to enable the main PLL.\r Cleared by hardware when entering Stop or Standby modes and when PLL1 on HSE is selected as sysclk, on a HSECSS failure.\r This bit cannot be reset if the PLL1 clock is used as the system clock.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 24
    bit_size: 1
  - name: PLLRDY
    description: "PLL1 clock ready flag\r Set by hardware to indicate that the PLL1 is locked.\r Access to the bit can be secured by RCC PLL1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 25
    bit_size: 1
fieldset/CSR:
  description: RCC control/status register
  fields:
  - name: RMVF
    description: "Remove reset flag\r Set by software to clear the reset flags.\r Access can be secured by RCC RMVFSEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV."
    bit_offset: 23
    bit_size: 1
  - name: OBLRSTF
    description: "Option byte loader reset flag\r Set by hardware when a reset from the option byte loading occurs.\r Cleared by writing to the RMVF bit."
    bit_offset: 25
    bit_size: 1
  - name: PINRSTF
    description: "NRST pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by writing to the RMVF bit."
    bit_offset: 26
    bit_size: 1
  - name: BORRSTF
    description: "BOR flag\r Set by hardware when a BOR occurs.\r Cleared by writing to the RMVF bit."
    bit_offset: 27
    bit_size: 1
  - name: SFTRSTF
    description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by writing to the RMVF bit."
    bit_offset: 28
    bit_size: 1
  - name: IWDGRSTF
    description: "Independent watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by writing to the RMVF bit."
    bit_offset: 29
    bit_size: 1
  - name: WWDGRSTF
    description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by writing to the RMVF bit."
    bit_offset: 30
    bit_size: 1
  - name: LPWRRSTF
    description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop and Standby modes entry.\r Cleared by writing to the RMVF bit."
    bit_offset: 31
    bit_size: 1
fieldset/ECSCR1:
  description: RCC external clock sources calibration register 1
  fields:
  - name: HSETRIM
    description: "HSE clock trimming \r These bits provide user-programmable capacitor trimming value. It can be programmed to adjust the HSE oscillator frequency."
    bit_offset: 16
    bit_size: 6
fieldset/ICSCR3:
  description: RCC internal clock sources calibration register 3
  fields:
  - name: HSICAL
    description: "HSI16 clock calibration\r These bits are initialized at startup with the factory-programmed HSI16 calibration value. When HSITRIM[4:0] is written, HSICAL[11:0] is updated with the sum of HSITRIM[4:0] and the initial factory trim value."
    bit_offset: 0
    bit_size: 12
  - name: HSITRIM
    description: "HSI16 clock trimming \r These bits provide an additional user-programmable trimming value that is added to the HSICAL[11:0] bits. It can be programmed to adjust to voltage and temperature variations that influence the frequency of the HSI16."
    bit_offset: 16
    bit_size: 5
fieldset/PLL1CFGR:
  description: RCC PLL1 configuration register
  fields:
  - name: PLLSRC
    description: "PLL1 entry clock source\r Set and cleared by software to select PLL1 clock source. These bits can be written only when the PLL1 is disabled.\r Cleared by hardware when entering Stop or Standby modes. \r Note: In order to save power, when no PLL1 clock is used, the value of PLL1SRC must be 0."
    bit_offset: 0
    bit_size: 2
    enum: PLLSRC
  - name: PLLRGE
    description: "PLL1 input frequency range\r Set and reset by software to select the proper reference frequency range used for PLL1.\r This bit must be written before enabling the PLL1.\r 00-01-10: PLL1 input (ref1_ck) clock range frequency between 4 and 8 MHz"
    bit_offset: 2
    bit_size: 2
    enum: PLLRGE
  - name: PLLFRACEN
    description: "PLL1 fractional latch enable\r Set and reset by software to latch the content of PLL1FRACN into the ΣΔ modulator.\r In order to latch the PLL1FRACN value into the ΣΔ modulator, PLL1FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL1FRACN into the modulator (see PLL1 initialization phase for details)."
    bit_offset: 4
    bit_size: 1
  - name: PLLM
    description: "Prescaler for PLL1\r Set and cleared by software to configure the prescaler of the PLL1. The VCO1 input frequency is PLL1 input clock frequency/PLL1M.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). \r ..."
    bit_offset: 8
    bit_size: 3
  - name: PLLPEN
    description: "PLL1 DIVP divider output enable\r Set and reset by software to enable the pll1pclk output of the PLL1.\r To save power, PLL1PEN and PLL1P bits must be set to 0 when the pll1pclk is not used. \r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."
    bit_offset: 16
    bit_size: 1
  - name: PLLQEN
    description: "PLL1 DIVQ divider output enable\r Set and reset by software to enable the pll1qclk output of the PLL1.\r To save power, PLL1QEN and PLL1Q bits must be set to 0 when the pll1qclk is not used. \r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."
    bit_offset: 17
    bit_size: 1
  - name: PLLREN
    description: "PLL1 DIVR divider output enable\r Set and cleared by software to enable the pll1rclk output of the PLL1.\r To save power, PLL1REN and PLL1R bits must be set to 0 when the pll1rclk is not used.\r This bit can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0)."
    bit_offset: 18
    bit_size: 1
  - name: PLLRCLKPRE
    description: "pll1rclk clock for SYSCLK prescaler division enable\r Set and cleared by software to control the division of the pll1rclk clock for SYSCLK."
    bit_offset: 20
    bit_size: 1
    enum: PLLRCLKPRE
  - name: PLLRCLKPRESTEP
    description: "pll1rclk clock for SYSCLK prescaler division step selection\r Set and cleared by software to control the division step of the pll1rclk clock for SYSCLK."
    bit_offset: 21
    bit_size: 1
    enum: PLLRCLKPRESTEP
  - name: PLLRCLKPRERDY
    description: "pll1rclkpre not divided ready.\r Set by hardware after PLL1RCLKPRE has been set from divided to not divide, to indicate that the pll1rclk not divided is available on sysclkpre."
    bit_offset: 22
    bit_size: 1
fieldset/PLL1DIVR:
  description: RCC PLL1 dividers register
  fields:
  - name: PLLN
    description: "Multiplication factor for PLL1 VCO\r Set and reset by software to control the multiplication factor of the VCO.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ...\r ...\r others: reserved\r VCO output frequency = F<sub>ref1_ck</sub> x multiplication factor for PLL1 VCO, when fractional value 0 has been loaded into PLL1FRACN, with: \r Multiplication factor for PLL1 VCO between 4 and 512\r input frequency F<sub>ref1_ck</sub> between 4 and 16�MHz"
    bit_offset: 0
    bit_size: 9
  - name: PLLP
    description: "PLL1 DIVP division factor\r Set and reset by software to control the frequency of the pll1pclk clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r Note that odd division factors are not allowed.\r ..."
    bit_offset: 9
    bit_size: 7
  - name: PLLQ
    description: "PLL1 DIVQ division factor\r Set and reset by software to control the frequency of the PLl1QCLK clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
    bit_offset: 16
    bit_size: 7
  - name: PLLR
    description: "PLL1 DIVR division factor\r Set and reset by software to control the frequency of the pll1rclk clock.\r These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0).\r ..."
    bit_offset: 24
    bit_size: 7
fieldset/PLL1FRACR:
  description: RCC PLL1 fractional divider register
  fields:
  - name: PLLFRACN
    description: "Fractional part of the multiplication factor for PLL1 VCO\r Set and reset by software to control the fractional part of the multiplication factor of the VCO.\r These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.\r VCO output frequency = F<sub>ref1_ck</sub> x [multiplication factor for PLL1 VCO + (PLL1FRACN / 2<sup>13</sup>)], with: \r Multiplication factor for PLL1 VCO must be between 4 and 512.\r PLL1FRACN can be between 0 and 2<sup>13</sup>- 1.\r The input frequency F<sub>ref1_ck</sub> must be between 4 and 16 MHz. \r To change the used fractional value on-the-fly even if the PLL1 is enabled, the application must proceed as follows:\r Set the bit PLL1FRACEN to 0. \r Write the new fractional value into PLL1FRACN. \r Set the bit PLL1FRACEN to 1."
    bit_offset: 3
    bit_size: 13
fieldset/PRIVCFGR:
  description: RCC privilege configuration register
  fields:
  - name: SPRIV
    description: "RCC secure functions privilege configuration\r Set and reset by software.\r This bit can be written only by a secure privileged access."
    bit_offset: 0
    bit_size: 1
  - name: NSPRIV
    description: "RCC non-secure functions privilege configuration\r Set and reset by software.\r This bit can be written only by privileged access, secure or non-secure."
    bit_offset: 1
    bit_size: 1
fieldset/RADIOENR:
  description: RCC RADIO peripheral clock enable register
  fields:
  - name: BBCLKEN
    description: "2.4 GHz RADIO baseband kernel clock (aclk) enable\r Set and cleared by software.\r Note: The HSE oscillator needs to be enabled by either HSEON or STRADIOCLKON."
    bit_offset: 1
    bit_size: 1
  - name: STRADIOCLKON
    description: "2.4 GHz RADIO bus clock enable and HSE oscillator enable by 2.4 GHz RADIO sleep timer wakeup event\r Set by hardware on a 2.4 GHz RADIO sleep timer wakeup event.\r Cleared by software writing zero to this bit.\r Note: Before accessing the 2.4 GHz RADIO registers the RADIOCLKRDY bit must be checked."
    bit_offset: 16
    bit_size: 1
  - name: RADIOCLKRDY
    description: "2.4 GHz RADIO bus clock ready.\r Set and cleared by hardware to indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed.\r Note: Once both RADIOEN and STRADIOCLKON are cleared, RADIOCLKRDY goes low after three hclk5 clock cycles."
    bit_offset: 17
    bit_size: 1
fieldset/SECCFGR:
  description: RCC secure configuration register
  fields:
  - name: HSISEC
    description: "HSI16 clock configuration and status bits security\r Set and reset by software."
    bit_offset: 0
    bit_size: 1
  - name: HSESEC
    description: "HSE clock configuration bits, status bits and HSECSS security\r Set and reset by software."
    bit_offset: 1
    bit_size: 1
  - name: LSISEC
    description: "LSI clock configuration and status bits security\r Set and reset by software."
    bit_offset: 3
    bit_size: 1
  - name: LSESEC
    description: "LSE clock configuration and status bits security\r Set and reset by software."
    bit_offset: 4
    bit_size: 1
  - name: SYSCLKSEC
    description: "SYSCLK selection, clock output on MCO configuration security\r Set and reset by software."
    bit_offset: 5
    bit_size: 1
  - name: PRESCSEC
    description: "AHBx/APBx prescaler configuration bits security\r Set and reset by software."
    bit_offset: 6
    bit_size: 1
  - name: PLLSEC
    description: "PLL1 clock configuration and status bits security\r Set and reset by software."
    bit_offset: 7
    bit_size: 1
  - name: RMVFSEC
    description: "Remove reset flag security\r Set and reset by software."
    bit_offset: 12
    bit_size: 1
enum/ADCSEL:
  bit_size: 3
  variants:
  - name: HCLK1
    description: hclk1 clock selected
    value: 0
  - name: SYSCLK
    description: SYSCLK selected
    value: 1
  - name: PLL1_P
    description: pll1pclk selected
    value: 2
  - name: HSE
    description: HSE clock selected
    value: 3
  - name: HSI16
    description: HSI16 clock selected
    value: 4
enum/HDIV5:
  bit_size: 1
  variants:
  - name: Div1
    description: hclk5 = SYSCLK not divided
    value: 0
  - name: Div2
    description: hclk5 = SYSCLK divided by 2
    value: 1
enum/HPRE:
  bit_size: 3
  variants:
  - name: Div1
    description: DCLK not divided
    value: 0
  - name: Div2
    description: hclk = SYSCLK divided by 2
    value: 4
  - name: Div4
    description: hclk = SYSCLK divided by 4
    value: 5
  - name: Div8
    description: hclk = SYSCLK divided by 8
    value: 6
  - name: Div16
    description: hclk = SYSCLK divided by 16
    value: 7
enum/HPRE5:
  bit_size: 3
  variants:
  - name: Div1
    description: DCLK not divided
    value: 0
  - name: Div2
    description: hclk5 = SYSCLK divided by 2
    value: 4
  - name: Div3
    description: hclk5 = SYSCLK divided by 3
    value: 5
  - name: Div4
    description: hclk5 = SYSCLK divided by 4
    value: 6
  - name: Div6
    description: hclk5 = SYSCLK divided by 6
    value: 7
enum/HSEPRE:
  bit_size: 1
  variants:
  - name: Div1
    description: HSE not divided, SYSCLK = HSE
    value: 0
  - name: Div2
    description: HSE divided, SYSCLK = HSE/2
    value: 1
enum/ICSEL:
  bit_size: 2
  variants:
  - name: PCLK1
    description: pclk1 selected
    value: 0
  - name: SYSCLK
    description: SYSCLK selected
    value: 1
  - name: HSI16
    description: HSI16 selected
    value: 2
enum/LPTIMSEL:
  bit_size: 2
  variants:
  - name: PCLK7
    description: pclk7 selected.
    value: 0
  - name: LSI
    description: LSI selected
    value: 1
  - name: HSI16
    description: HSI16 selected
    value: 2
  - name: LSE
    description: LSE selected
    value: 3
enum/LPUARTSEL:
  bit_size: 2
  variants:
  - name: PCLK7
    description: pclk7 selected
    value: 0
  - name: SYSCLK
    description: SYSCLK selected
    value: 1
  - name: HSI16
    description: HSI16 selected
    value: 2
  - name: LSE
    description: LSE selected
    value: 3
enum/LSCOSEL:
  bit_size: 1
  variants:
  - name: LSI
    description: LSI clock selected
    value: 0
  - name: LSE
    description: LSE clock selected
    value: 1
enum/LSEDRV:
  bit_size: 2
  variants:
  - name: Low
    description: Low driving capability
    value: 0
  - name: MediumLow
    description: Medium low driving capability
    value: 1
  - name: MediumHigh
    description: Medium high driving capability
    value: 2
  - name: High
    description: High driving capability
    value: 3
enum/LSETRIM:
  bit_size: 2
  variants:
  - name: R5_4
    description: current source resistance 5/4 x R
    value: 0
  - name: R
    description: current source resistance R
    value: 1
  - name: R3_4
    description: current source resistance 3/4 x R
    value: 2
  - name: R2_3
    description: current source resistance 2/3 x R
    value: 3
enum/LSIPREDIV:
  bit_size: 1
  variants:
  - name: Div1
    description: LSI not divided
    value: 0
  - name: Div128
    description: LSI divided by 128
    value: 1
enum/MCOPRE:
  bit_size: 3
  variants:
  - name: Div1
    description: MCO divided by 1
    value: 0
  - name: Div2
    description: MCO divided by 2
    value: 1
  - name: Div4
    description: MCO divided by 4
    value: 2
  - name: Div8
    description: MCO divided by 8
    value: 3
  - name: Div16
    description: MCO divided by 16
    value: 4
enum/MCOSEL:
  bit_size: 4
  variants:
  - name: DISABLED
    description: MCO output disabled, no clock on MCO
    value: 0
  - name: SYSCLKPRE
    description: sysclkpre system clock after PLL1RCLKPRE division selected
    value: 1
  - name: HSI16
    description: HSI16 clock selected
    value: 3
  - name: HSE
    description: HSE clock selected
    value: 4
  - name: PLL1_R
    description: pll1rclk clock selected
    value: 5
  - name: LSI
    description: LSI clock selected
    value: 6
  - name: LSE
    description: LSE clock selected
    value: 7
  - name: PLL1_P
    description: pll1pclk clock selected
    value: 8
  - name: PLL1_Q
    description: pll1qclk clock selected
    value: 9
  - name: HCLK5
    description: hclk5 clock selected
    value: 10
enum/PLLRCLKPRE:
  bit_size: 1
  variants:
  - name: Div1
    description: pll1rclk not divided, sysclkpre = pll1rclk
    value: 0
  - name: Divided
    description: pll1rclk divided, sysclkpre = pll1rclk divided
    value: 1
enum/PLLRCLKPRESTEP:
  bit_size: 1
  variants:
  - name: STEP2
    description: pll1rclk 2-step division
    value: 0
  - name: STEP3
    description: pll1rclk 3-step division
    value: 1
enum/PLLRGE:
  bit_size: 2
  variants:
  - name: FREQ_4TO8MHZ
    description: PLL2 input (ref2_ck) clock range frequency between 4 and 8 MHz
    value: 0
  - name: FREQ_8TO16MHZ
    description: PLL2 input (ref2_ck) clock range frequency between 8 and 16 MHz
    value: 3
enum/PLLSRC:
  bit_size: 2
  variants:
  - name: NONE
    description: no clock sent to PLL1
    value: 0
  - name: HSI16
    description: HSI16 clock selected as PLL1 clock entry
    value: 2
  - name: HSE
    description: HSE clock after HSEPRE divider selected as PLL1 clock entry
    value: 3
enum/PPRE:
  bit_size: 3
  variants:
  - name: Div1
    description: HCLK not divided
    value: 0
  - name: Div2
    description: HCLK divided by 2
    value: 4
  - name: Div4
    description: HCLK divided by 4
    value: 5
  - name: Div8
    description: HCLK divided by 8
    value: 6
  - name: Div16
    description: HCLK divided by 16
    value: 7
enum/RADIOSTSEL:
  bit_size: 2
  variants:
  - name: None
    description: no clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled
    value: 0
  - name: LSE
    description: LSE oscillator clock selected
    value: 1
  - name: HSE
    description: HSE oscillator clock divided by 1000 selected
    value: 3
enum/RNGSEL:
  bit_size: 2
  variants:
  - name: LSE
    description: LSE selected
    value: 0
  - name: LSI
    description: LSI selected
    value: 1
  - name: HSI16
    description: HSI16 selected
    value: 2
  - name: PLL1_Q
    description: pll1qclk divide by 2 selected
    value: 3
enum/RTCSEL:
  bit_size: 2
  variants:
  - name: NoClock
    description: no clock selected, RTC and TAMP kernel clock disabled
    value: 0
  - name: LSE
    description: LSE oscillator clock selected, and enabled
    value: 1
  - name: LSI
    description: LSI oscillator clock selected, and enabled
    value: 2
  - name: HSE
    description: HSE oscillator clock divided by 32 selected, and enabled
    value: 3
enum/SPISEL:
  bit_size: 2
  variants:
  - name: PCLK2
    description: pclk2 selected
    value: 0
  - name: SYSCLK
    description: SYSCLK selected
    value: 1
  - name: HSI16
    description: HSI16 selected
    value: 2
enum/SW:
  bit_size: 2
  variants:
  - name: HSI16
    description: HSI16 selected as system clock
    value: 0
  - name: HSE
    description: HSE or HSE/2, as defined by HSEPRE, selected as system clock
    value: 2
  - name: PLL1_R
    description: pll1rclk selected as system clock
    value: 3
enum/SYSTICKSEL:
  bit_size: 2
  variants:
  - name: HCLK1_DIV8
    description: hclk1 divided by 8 selected
    value: 0
  - name: LSI
    description: LSI selected
    value: 1
  - name: LSE
    description: LSE selected
    value: 2
enum/TIMICSEL:
  bit_size: 1
  variants:
  - name: Div1
    description: HSI16 divider disabled
    value: 0
  - name: HSI16_DIV_256
    description: HSI16/256 generated and can be selected by TIM16, TIM17 and LPTIM2 as internal input capture
    value: 1
enum/USARTSEL:
  bit_size: 2
  variants:
  - name: PCLK1
    description: pclk1 selected
    value: 0
  - name: SYSCLK
    description: SYSCLK selected
    value: 1
  - name: HSI16
    description: HSI16 selected
    value: 2
  - name: LSE
    description: LSE selected
    value: 3