block/RCC: description: Reset and clock control items: - name: CR description: Clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register byte_offset: 8 fieldset: CFGR - name: PLLCFGR description: PLL configuration register byte_offset: 12 fieldset: PLLCFGR - name: CIER description: Clock interrupt enable register byte_offset: 24 fieldset: CIER - name: CIFR description: Clock interrupt flag register byte_offset: 28 access: Read fieldset: CIFR - name: CICR description: Clock interrupt clear register byte_offset: 32 access: Write fieldset: CICR - name: AHB1RSTR description: AHB1 peripheral reset register byte_offset: 40 fieldset: AHB1RSTR - name: AHB2RSTR description: AHB2 peripheral reset register byte_offset: 44 fieldset: AHB2RSTR - name: AHB3RSTR description: AHB3 peripheral reset register byte_offset: 48 fieldset: AHB3RSTR - name: APB1RSTR1 description: APB1 peripheral reset register 1 byte_offset: 56 fieldset: APB1RSTR1 - name: APB1RSTR2 description: APB1 peripheral reset register 2 byte_offset: 60 fieldset: APB1RSTR2 - name: APB2RSTR description: APB2 peripheral reset register byte_offset: 64 fieldset: APB2RSTR - name: APB3RSTR description: APB3 peripheral reset register byte_offset: 68 fieldset: APB3RSTR - name: AHB1ENR description: AHB1 peripheral clock enable register byte_offset: 72 fieldset: AHB1ENR - name: AHB2ENR description: AHB2 peripheral clock enable register byte_offset: 76 fieldset: AHB2ENR - name: AHB3ENR description: AHB3 peripheral clock enable register byte_offset: 80 fieldset: AHB3ENR - name: APB1ENR1 description: APB1 peripheral clock enable register 1 byte_offset: 88 fieldset: APB1ENR1 - name: APB1ENR2 description: APB1 peripheral clock enable register 2 byte_offset: 92 fieldset: APB1ENR2 - name: APB2ENR description: APB2 peripheral clock enable register byte_offset: 96 fieldset: APB2ENR - name: APB3ENR description: APB3 peripheral clock enable register byte_offset: 100 fieldset: APB3ENR - name: AHB1SMENR description: AHB1 peripheral clocks enable in Sleep modes register byte_offset: 104 fieldset: AHB1SMENR - name: AHB2SMENR description: AHB2 peripheral clocks enable in Sleep modes register byte_offset: 108 fieldset: AHB2SMENR - name: AHB3SMENR description: AHB3 peripheral clocks enable in Sleep and Stop modes register byte_offset: 112 fieldset: AHB3SMENR - name: APB1SMENR1 description: APB1 peripheral clocks enable in Sleep mode register 1 byte_offset: 120 fieldset: APB1SMENR1 - name: APB1SMENR2 description: APB1 peripheral clocks enable in Sleep mode register 2 byte_offset: 124 fieldset: APB1SMENR2 - name: APB2SMENR description: APB2 peripheral clocks enable in Sleep mode register byte_offset: 128 fieldset: APB2SMENR - name: APB3SMENR description: APB3 peripheral clock enable in Sleep mode register byte_offset: 132 fieldset: APB3SMENR - name: CCIPR description: Peripherals independent clock configuration register byte_offset: 136 fieldset: CCIPR - name: BDCR description: Backup domain control register byte_offset: 144 fieldset: BDCR - name: CSR description: Control/status register byte_offset: 148 fieldset: CSR - name: EXTCFGR description: Extended clock recovery register byte_offset: 264 fieldset: EXTCFGR fieldset/AHB1ENR: description: AHB1 peripheral clock enable register fields: - name: DMA1EN description: CPU1 DMA1 clock enable bit_offset: 0 bit_size: 1 - name: DMA2EN description: CPU1 DMA2 clock enable bit_offset: 1 bit_size: 1 - name: DMAMUX1EN description: CPU1 DMAMUX1 clock enable bit_offset: 2 bit_size: 1 - name: CRCEN description: CPU1 CRC clock enable bit_offset: 12 bit_size: 1 fieldset/AHB1RSTR: description: AHB1 peripheral reset register fields: - name: DMA1RST description: DMA1 reset bit_offset: 0 bit_size: 1 - name: DMA2RST description: DMA2 reset bit_offset: 1 bit_size: 1 - name: DMAMUX1RST description: DMAMUX1 reset bit_offset: 2 bit_size: 1 - name: CRCRST description: CRC reset bit_offset: 12 bit_size: 1 fieldset/AHB1SMENR: description: AHB1 peripheral clocks enable in Sleep modes register fields: - name: DMA1SMEN description: DMA1 clock enable during CPU1 CSleep mode. bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: DMA2 clock enable during CPU1 CSleep mode bit_offset: 1 bit_size: 1 - name: DMAMUX1SMEN description: DMAMUX1 clock enable during CPU1 CSleep mode. bit_offset: 2 bit_size: 1 - name: CRCSMEN description: CRC clock enable during CPU1 CSleep mode. bit_offset: 12 bit_size: 1 fieldset/AHB2ENR: description: AHB2 peripheral clock enable register fields: - name: GPIOAEN description: CPU1 IO port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: CPU1 IO port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: CPU1 IO port C clock enable bit_offset: 2 bit_size: 1 - name: GPIOHEN description: CPU1 IO port H clock enable bit_offset: 7 bit_size: 1 fieldset/AHB2RSTR: description: AHB2 peripheral reset register fields: - name: GPIOARST description: IO port A reset bit_offset: 0 bit_size: 1 - name: GPIOBRST description: IO port B reset bit_offset: 1 bit_size: 1 - name: GPIOCRST description: IO port C reset bit_offset: 2 bit_size: 1 - name: GPIOHRST description: IO port H reset bit_offset: 7 bit_size: 1 fieldset/AHB2SMENR: description: AHB2 peripheral clocks enable in Sleep modes register fields: - name: GPIOASMEN description: IO port A clock enable during CPU1 CSleep mode. bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: IO port B clock enable during CPU1 CSleep mode. bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: IO port C clock enable during CPU1 CSleep mode. bit_offset: 2 bit_size: 1 - name: GPIOHSMEN description: IO port H clock enable during CPU1 CSleep mode. bit_offset: 7 bit_size: 1 fieldset/AHB3ENR: description: AHB3 peripheral clock enable register fields: - name: PKAEN description: PKAEN bit_offset: 16 bit_size: 1 - name: AESEN description: AESEN bit_offset: 17 bit_size: 1 - name: RNGEN description: RNGEN bit_offset: 18 bit_size: 1 - name: HSEMEN description: HSEMEN bit_offset: 19 bit_size: 1 - name: FLASHEN description: CPU1 Flash interface clock enable bit_offset: 25 bit_size: 1 fieldset/AHB3RSTR: description: AHB3 peripheral reset register fields: - name: PKARST description: PKARST bit_offset: 16 bit_size: 1 - name: AESRST description: AESRST bit_offset: 17 bit_size: 1 - name: RNGRST description: RNGRST bit_offset: 18 bit_size: 1 - name: HSEMRST description: HSEMRST bit_offset: 19 bit_size: 1 - name: FLASHRST description: Flash interface reset bit_offset: 25 bit_size: 1 fieldset/AHB3SMENR: description: AHB3 peripheral clocks enable in Sleep and Stop modes register fields: - name: PKASMEN description: PKA accelerator clock enable during CPU1 CSleep mode. bit_offset: 16 bit_size: 1 - name: AESSMEN description: AES accelerator clock enable during CPU1 CSleep mode. bit_offset: 17 bit_size: 1 - name: RNGSMEN description: True RNG clocks enable during CPU1 Csleep and CStop modes bit_offset: 18 bit_size: 1 - name: SRAM1SMEN description: SRAM1 interface clock enable during CPU1 CSleep mode. bit_offset: 23 bit_size: 1 - name: SRAM2SMEN description: SRAM2 memory interface clock enable during CPU1 CSleep mode bit_offset: 24 bit_size: 1 - name: FLASHSMEN description: Flash interface clock enable during CPU1 CSleep mode. bit_offset: 25 bit_size: 1 fieldset/APB1ENR1: description: APB1 peripheral clock enable register 1 fields: - name: TIM2EN description: CPU1 TIM2 timer clock enable bit_offset: 0 bit_size: 1 - name: RTCAPBEN description: CPU1 RTC APB clock enable bit_offset: 10 bit_size: 1 - name: WWDGEN description: CPU1 Window watchdog clock enable bit_offset: 11 bit_size: 1 - name: SPI2EN description: CPU1 SPI2 clock enable bit_offset: 14 bit_size: 1 - name: USART2EN description: CPU1 USART2 clock enable bit_offset: 17 bit_size: 1 - name: I2C1EN description: CPU1 I2C1 clocks enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: CPU1 I2C2 clocks enable bit_offset: 22 bit_size: 1 - name: I2C3EN description: CPU1 I2C3 clocks enable bit_offset: 23 bit_size: 1 - name: DACEN description: CPU1 DAC clock enable bit_offset: 29 bit_size: 1 - name: LPTIM1EN description: CPU1 Low power timer 1 clocks enable bit_offset: 31 bit_size: 1 fieldset/APB1ENR2: description: APB1 peripheral clock enable register 2 fields: - name: LPUART1EN description: CPU1 Low power UART 1 clocks enable bit_offset: 0 bit_size: 1 - name: LPTIM2EN description: CPU1 Low power timer 2 clocks enable bit_offset: 5 bit_size: 1 - name: LPTIM3EN description: CPU1 Low power timer 3 clocks enable bit_offset: 6 bit_size: 1 fieldset/APB1RSTR1: description: APB1 peripheral reset register 1 fields: - name: TIM2RST description: TIM2 timer reset bit_offset: 0 bit_size: 1 - name: SPI2RST description: SPI2 reset bit_offset: 14 bit_size: 1 - name: USART2RST description: USART2 reset bit_offset: 17 bit_size: 1 - name: I2C1RST description: I2C1 reset bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C2 reset bit_offset: 22 bit_size: 1 - name: I2C3RST description: I2C3 reset bit_offset: 23 bit_size: 1 - name: DACRST description: DAC reset bit_offset: 29 bit_size: 1 - name: LPTIM1RST description: Low Power Timer 1 reset bit_offset: 31 bit_size: 1 fieldset/APB1RSTR2: description: APB1 peripheral reset register 2 fields: - name: LPUART1RST description: Low-power UART 1 reset bit_offset: 0 bit_size: 1 - name: LPTIM2RST description: Low-power timer 2 reset bit_offset: 5 bit_size: 1 - name: LPTIM3RST description: Low-power timer 3 reset bit_offset: 6 bit_size: 1 fieldset/APB1SMENR1: description: APB1 peripheral clocks enable in Sleep mode register 1 fields: - name: TIM2SMEN description: TIM2 timer clock enable during CPU1 CSleep mode. bit_offset: 0 bit_size: 1 - name: RTCAPBSMEN description: RTC bus clock enable during CPU1 CSleep mode. bit_offset: 10 bit_size: 1 - name: WWDGSMEN description: Window watchdog clocks enable during CPU1 CSleep mode. bit_offset: 11 bit_size: 1 - name: SPI2SMEN description: SPI2 clock enable during CPU1 CSleep mode. bit_offset: 14 bit_size: 1 - name: USART2SMEN description: USART2 clock enable during CPU1 CSleep mode. bit_offset: 17 bit_size: 1 - name: I2C1SMEN description: I2C1 clock enable during CPU1 Csleep and CStop modes bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clock enable during CPU1 Csleep and CStop modes bit_offset: 22 bit_size: 1 - name: I2C3SMEN description: I2C3 clock enable during CPU1 Csleep and CStop modes bit_offset: 23 bit_size: 1 - name: DACSMEN description: DAC clock enable during CPU1 CSleep mode. bit_offset: 29 bit_size: 1 - name: LPTIM1SMEN description: Low power timer 1 clock enable during CPU1 Csleep and CStop mode bit_offset: 31 bit_size: 1 fieldset/APB1SMENR2: description: APB1 peripheral clocks enable in Sleep mode register 2 fields: - name: LPUART1SMEN description: Low power UART 1 clock enable during CPU1 Csleep and CStop modes. bit_offset: 0 bit_size: 1 - name: LPTIM2SMEN description: Low power timer 2 clock enable during CPU1 Csleep and CStop modes bit_offset: 5 bit_size: 1 - name: LPTIM3SMEN description: Low power timer 3 clock enable during CPU1 Csleep and CStop modes bit_offset: 6 bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register fields: - name: ADCEN description: CPU1 ADC clocks enable bit_offset: 9 bit_size: 1 - name: TIM1EN description: CPU1 TIM1 timer clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: CPU1 SPI1 clock enable bit_offset: 12 bit_size: 1 - name: USART1EN description: CPU1 USART1clocks enable bit_offset: 14 bit_size: 1 - name: TIM16EN description: CPU1 TIM16 timer clock enable bit_offset: 17 bit_size: 1 - name: TIM17EN description: CPU1 TIM17 timer clock enable bit_offset: 18 bit_size: 1 fieldset/APB2RSTR: description: APB2 peripheral reset register fields: - name: ADCRST description: ADC reset bit_offset: 9 bit_size: 1 - name: TIM1RST description: TIM1 timer reset bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI1 reset bit_offset: 12 bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - name: TIM16RST description: TIM16 timer reset bit_offset: 17 bit_size: 1 - name: TIM17RST description: TIM17 timer reset bit_offset: 18 bit_size: 1 fieldset/APB2SMENR: description: APB2 peripheral clocks enable in Sleep mode register fields: - name: ADCSMEN description: ADC clocks enable during CPU1 Csleep and CStop modes bit_offset: 9 bit_size: 1 - name: TIM1SMEN description: TIM1 timer clock enable during CPU1 CSleep mode. bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clock enable during CPU1 CSleep mode. bit_offset: 12 bit_size: 1 - name: USART1SMEN description: USART1 clock enable during CPU1 Csleep and CStop modes. bit_offset: 14 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clock enable during CPU1 CSleep mode. bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: TIM17 timer clock enable during CPU1 CSleep mode. bit_offset: 18 bit_size: 1 fieldset/APB3ENR: description: APB3 peripheral clock enable register fields: - name: SUBGHZSPIEN description: sub-GHz radio SPI clock enable bit_offset: 0 bit_size: 1 fieldset/APB3RSTR: description: APB3 peripheral reset register fields: - name: SUBGHZSPIRST description: Sub-GHz radio SPI reset bit_offset: 0 bit_size: 1 fieldset/APB3SMENR: description: APB3 peripheral clock enable in Sleep mode register fields: - name: SUBGHZSPISMEN description: Sub-GHz radio SPI clock enable during Sleep and Stop modes bit_offset: 0 bit_size: 1 fieldset/BDCR: description: Backup domain control register fields: - name: LSEON description: LSE oscillator enable bit_offset: 0 bit_size: 1 - name: LSERDY description: LSE oscillator ready bit_offset: 1 bit_size: 1 - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - name: LSEDRV description: LSE oscillator drive capability bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: CSS on LSE enable bit_offset: 5 bit_size: 1 - name: LSECSSD description: CSS on LSE failure Detection bit_offset: 6 bit_size: 1 - name: LSESYSEN description: LSE system clock enable bit_offset: 7 bit_size: 1 - name: RTCSEL description: RTC clock source selection bit_offset: 8 bit_size: 2 enum: RTCSEL - name: LSESYSRDY description: LSE system clock ready bit_offset: 11 bit_size: 1 - name: RTCEN description: RTC clock enable bit_offset: 15 bit_size: 1 - name: BDRST description: Backup domain software reset bit_offset: 16 bit_size: 1 - name: LSCOEN description: Low speed clock output enable bit_offset: 24 bit_size: 1 - name: LSCOSEL description: Low speed clock output selection bit_offset: 25 bit_size: 1 fieldset/CCIPR: description: Peripherals independent clock configuration register fields: - name: USART1SEL description: USART1 clock source selection bit_offset: 0 bit_size: 2 - name: USART2SEL description: USART2 clock source selection bit_offset: 2 bit_size: 2 - name: SPI2SEL description: SPI2 I2S clock source selection bit_offset: 8 bit_size: 2 - name: LPUART1SEL description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 - name: I2C1SEL description: I2C1 clock source selection bit_offset: 12 bit_size: 2 - name: I2C2SEL description: I2C2 clock source selection bit_offset: 14 bit_size: 2 - name: I2C3SEL description: I2C3 clock source selection bit_offset: 16 bit_size: 2 - name: LPTIM1SEL description: Low power timer 1 clock source selection bit_offset: 18 bit_size: 2 - name: LPTIM2SEL description: Low power timer 2 clock source selection bit_offset: 20 bit_size: 2 - name: LPTIM3SEL description: Low power timer 3 clock source selection bit_offset: 22 bit_size: 2 - name: ADCSEL description: ADC clock source selection bit_offset: 28 bit_size: 2 enum: ADCSEL - name: RNGSEL description: RNG clock source selection bit_offset: 30 bit_size: 2 enum: RNGSEL fieldset/CFGR: description: Clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 2 enum: SW - name: SWS description: System clock switch status bit_offset: 2 bit_size: 2 enum: SW - name: HPRE description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.) bit_offset: 4 bit_size: 4 enum: HPRE - name: PPRE1 description: PCLK1 low-speed prescaler (APB1) bit_offset: 8 bit_size: 3 enum: PPRE - name: PPRE2 description: PCLK2 high-speed prescaler (APB2) bit_offset: 11 bit_size: 3 enum: PPRE - name: STOPWUCK description: Wakeup from Stop and CSS backup clock selection bit_offset: 15 bit_size: 1 - name: HPREF description: HCLK1 prescaler flag (CPU1, AHB1, AHB2, and SRAM1) bit_offset: 16 bit_size: 1 - name: PPRE1F description: PCLK1 prescaler flag (APB1) bit_offset: 17 bit_size: 1 - name: PPRE2F description: PCLK2 prescaler flag (APB2) bit_offset: 18 bit_size: 1 - name: MCOSEL description: Microcontroller clock output bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCOPRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 0 bit_size: 1 - name: LSERDYC description: LSE ready interrupt clear bit_offset: 1 bit_size: 1 - name: MSIRDYC description: MSI ready interrupt clear bit_offset: 2 bit_size: 1 - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 3 bit_size: 1 - name: HSERDYC description: HSE ready interrupt clear bit_offset: 4 bit_size: 1 - name: PLLRDYC description: PLL ready interrupt clear bit_offset: 5 bit_size: 1 - name: CSSC description: HSE Clock security system interrupt clear bit_offset: 8 bit_size: 1 - name: LSECSSC description: LSE Clock security system interrupt clear bit_offset: 9 bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 0 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 1 bit_size: 1 - name: MSIRDYIE description: MSI ready interrupt enable bit_offset: 2 bit_size: 1 - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 3 bit_size: 1 - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 4 bit_size: 1 - name: PLLRDYIE description: PLL ready interrupt enable bit_offset: 5 bit_size: 1 - name: LSECSSIE description: LSE clock security system interrupt enable bit_offset: 9 bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: MSIRDYF description: MSI ready interrupt flag bit_offset: 2 bit_size: 1 - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 3 bit_size: 1 - name: HSERDYF description: HSE ready interrupt flag bit_offset: 4 bit_size: 1 - name: PLLRDYF description: PLL ready interrupt flag bit_offset: 5 bit_size: 1 - name: CSSF description: HSE Clock security system interrupt flag bit_offset: 8 bit_size: 1 - name: LSECSSF description: LSE Clock security system interrupt flag bit_offset: 9 bit_size: 1 fieldset/CR: description: Clock control register fields: - name: MSION description: MSI clock enable bit_offset: 0 bit_size: 1 - name: MSIRDY description: MSI clock ready flag (After reset this bit will be read 1 once the MSI is ready) bit_offset: 1 bit_size: 1 - name: MSIPLLEN description: MSI clock PLL enable bit_offset: 2 bit_size: 1 - name: MSIRGSEL description: MSI range control selection bit_offset: 3 bit_size: 1 enum: MSIRGSEL - name: MSIRANGE description: MSI clock ranges bit_offset: 4 bit_size: 4 enum: MSIRANGE - name: HSION description: HSI clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON description: HSI always enable for peripheral kernel clocks. bit_offset: 9 bit_size: 1 - name: HSIRDY description: HSI clock ready flag. (After wakeup from Stop this bit will be read 1 once the HSI is ready) bit_offset: 10 bit_size: 1 - name: HSIASFS description: HSI automatic start from Stop bit_offset: 11 bit_size: 1 - name: HSIKERDY description: HSI kernel clock ready flag for peripherals requests. bit_offset: 12 bit_size: 1 - name: HSEON description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 - name: CSSON description: HSE Clock security system enable bit_offset: 19 bit_size: 1 - name: HSEPRE description: HSE sysclk prescaler bit_offset: 20 bit_size: 1 enum: HSEPRE - name: HSEBYPPWR description: Enable HSE VDDTCXO output on package pin PB0-VDDTCXO. bit_offset: 21 bit_size: 1 - name: PLLON description: Main PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: Main PLL clock ready flag bit_offset: 25 bit_size: 1 fieldset/CSR: description: Control/status register fields: - name: LSION description: LSI oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: LSI oscillator ready bit_offset: 1 bit_size: 1 - name: LSIPRE description: LSI frequency prescaler bit_offset: 4 bit_size: 1 - name: MSISRANGE description: MSI clock ranges bit_offset: 8 bit_size: 4 - name: RFRSTF description: Radio in reset status flag bit_offset: 14 bit_size: 1 - name: RFRST description: Radio reset bit_offset: 15 bit_size: 1 - name: RMVF description: Remove reset flag bit_offset: 23 bit_size: 1 - name: RFILARSTF description: Radio illegal access flag bit_offset: 24 bit_size: 1 - name: OBLRSTF description: Option byte loader reset flag bit_offset: 25 bit_size: 1 - name: PINRSTF description: Pin reset flag bit_offset: 26 bit_size: 1 - name: BORRSTF description: BOR flag bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: Independent window watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 fieldset/EXTCFGR: description: Extended clock recovery register fields: - name: SHDHPRE description: HCLK3 shared prescaler (AHB3, Flash, and SRAM2) bit_offset: 0 bit_size: 4 enum: HPRE - name: SHDHPREF description: HCLK3 shared prescaler flag (AHB3, Flash, and SRAM2) bit_offset: 16 bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: MSICAL description: MSI clock calibration bit_offset: 0 bit_size: 8 - name: MSITRIM description: MSI clock trimming bit_offset: 8 bit_size: 8 - name: HSICAL description: HSI clock calibration bit_offset: 16 bit_size: 8 - name: HSITRIM description: HSI clock trimming bit_offset: 24 bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - name: PLLSRC description: Main PLL entry clock source bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLM description: Division factor for the main PLL input clock bit_offset: 4 bit_size: 3 enum: PLLM - name: PLLN description: Main PLL multiplication factor for VCO bit_offset: 8 bit_size: 7 enum: PLLN - name: PLLPEN description: Main PLL PLLPCLK output enable bit_offset: 16 bit_size: 1 - name: PLLP description: Main PLL division factor for PLLPCLK. bit_offset: 17 bit_size: 5 enum: PLLP - name: PLLQEN description: Main PLL PLLQCLK output enable bit_offset: 24 bit_size: 1 - name: PLLQ description: Main PLL division factor for PLLQCLK bit_offset: 25 bit_size: 3 enum: PLLQ - name: PLLREN description: Main PLL PLLRCLK output enable bit_offset: 28 bit_size: 1 - name: PLLR description: Main PLL division factor for PLLRCLK bit_offset: 29 bit_size: 3 enum: PLLR enum/ADCSEL: bit_size: 2 variants: - name: HSI description: HSI used as ADC clock source value: 1 - name: PLL1_P description: PLLPCLK used as ADC clock source value: 2 - name: SYS description: SYSCLK used as ADC clock source value: 3 enum/HPRE: bit_size: 4 variants: - name: Div1 description: DCLK not divided value: 0 - name: Div3 description: hclk = SYSCLK divided by 3 value: 1 - name: Div5 description: hclk = SYSCLK divided by 5 value: 2 - name: Div6 description: hclk = SYSCLK divided by 6 value: 5 - name: Div10 description: hclk = SYSCLK divided by 8 value: 6 - name: Div32 description: hclk = SYSCLK divided by 32 value: 7 - name: Div2 description: hclk = SYSCLK divided by 2 value: 8 - name: Div4 description: hclk = SYSCLK divided by 4 value: 9 - name: Div8 description: hclk = SYSCLK divided by 8 value: 10 - name: Div16 description: hclk = SYSCLK divided by 16 value: 11 - name: Div64 description: hclk = SYSCLK divided by 64 value: 12 - name: Div128 description: hclk = SYSCLK divided by 128 value: 13 - name: Div256 description: hclk = SYSCLK divided by 256 value: 14 - name: Div512 description: hclk = SYSCLK divided by 256 value: 15 enum/HSEPRE: bit_size: 1 variants: - name: Div1 value: 0 - name: Div2 value: 1 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/MCOPRE: bit_size: 3 variants: - name: Div1 description: No division value: 0 - name: Div2 description: Division by 2 value: 1 - name: Div4 description: Division by 4 value: 2 - name: Div8 description: Division by 8 value: 3 - name: Div16 description: Division by 16 value: 4 enum/MCOSEL: bit_size: 4 variants: - name: DISABLE description: No clock value: 0 - name: SYS description: SYSCLK clock selected value: 1 - name: MSI description: MSI oscillator clock selected value: 2 - name: HSI description: HSI oscillator clock selected value: 3 - name: HSE description: HSE oscillator clock selected value: 4 - name: PLL1_R description: Main PLLRCLK clock selected value: 5 - name: LSI description: LSI oscillator clock selected value: 6 - name: LSE description: LSE oscillator clock selected value: 8 - name: PLL1_P description: Main PLLCLK oscillator clock selected value: 13 - name: PLL1_Q description: Main PLLQCLK oscillator clock selected value: 14 enum/MSIRANGE: bit_size: 4 variants: - name: Range100K description: range 0 around 100 kHz value: 0 - name: Range200K description: range 1 around 200 kHz value: 1 - name: Range400K description: range 2 around 400 kHz value: 2 - name: Range800K description: range 3 around 800 kHz value: 3 - name: Range1M description: range 4 around 1 MHz value: 4 - name: Range2M description: range 5 around 2 MHz value: 5 - name: Range4M description: range 6 around 4 MHz value: 6 - name: Range8M description: range 7 around 8 MHz value: 7 - name: Range16M description: range 8 around 16 MHz value: 8 - name: Range24M description: range 9 around 24 MHz value: 9 - name: Range32M description: range 10 around 32 MHz value: 10 - name: Range48M description: range 11 around 48 MHz value: 11 enum/MSIRGSEL: bit_size: 1 variants: - name: CSR description: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register value: 0 - name: CR description: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register value: 1 enum/PLLM: bit_size: 3 variants: - name: Div1 value: 0 - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 enum/PLLN: bit_size: 7 variants: - name: Mul6 value: 6 - name: Mul7 value: 7 - name: Mul8 value: 8 - name: Mul9 value: 9 - name: Mul10 value: 10 - name: Mul11 value: 11 - name: Mul12 value: 12 - name: Mul13 value: 13 - name: Mul14 value: 14 - name: Mul15 value: 15 - name: Mul16 value: 16 - name: Mul17 value: 17 - name: Mul18 value: 18 - name: Mul19 value: 19 - name: Mul20 value: 20 - name: Mul21 value: 21 - name: Mul22 value: 22 - name: Mul23 value: 23 - name: Mul24 value: 24 - name: Mul25 value: 25 - name: Mul26 value: 26 - name: Mul27 value: 27 - name: Mul28 value: 28 - name: Mul29 value: 29 - name: Mul30 value: 30 - name: Mul31 value: 31 - name: Mul32 value: 32 - name: Mul33 value: 33 - name: Mul34 value: 34 - name: Mul35 value: 35 - name: Mul36 value: 36 - name: Mul37 value: 37 - name: Mul38 value: 38 - name: Mul39 value: 39 - name: Mul40 value: 40 - name: Mul41 value: 41 - name: Mul42 value: 42 - name: Mul43 value: 43 - name: Mul44 value: 44 - name: Mul45 value: 45 - name: Mul46 value: 46 - name: Mul47 value: 47 - name: Mul48 value: 48 - name: Mul49 value: 49 - name: Mul50 value: 50 - name: Mul51 value: 51 - name: Mul52 value: 52 - name: Mul53 value: 53 - name: Mul54 value: 54 - name: Mul55 value: 55 - name: Mul56 value: 56 - name: Mul57 value: 57 - name: Mul58 value: 58 - name: Mul59 value: 59 - name: Mul60 value: 60 - name: Mul61 value: 61 - name: Mul62 value: 62 - name: Mul63 value: 63 - name: Mul64 value: 64 - name: Mul65 value: 65 - name: Mul66 value: 66 - name: Mul67 value: 67 - name: Mul68 value: 68 - name: Mul69 value: 69 - name: Mul70 value: 70 - name: Mul71 value: 71 - name: Mul72 value: 72 - name: Mul73 value: 73 - name: Mul74 value: 74 - name: Mul75 value: 75 - name: Mul76 value: 76 - name: Mul77 value: 77 - name: Mul78 value: 78 - name: Mul79 value: 79 - name: Mul80 value: 80 - name: Mul81 value: 81 - name: Mul82 value: 82 - name: Mul83 value: 83 - name: Mul84 value: 84 - name: Mul85 value: 85 - name: Mul86 value: 86 - name: Mul87 value: 87 - name: Mul88 value: 88 - name: Mul89 value: 89 - name: Mul90 value: 90 - name: Mul91 value: 91 - name: Mul92 value: 92 - name: Mul93 value: 93 - name: Mul94 value: 94 - name: Mul95 value: 95 - name: Mul96 value: 96 - name: Mul97 value: 97 - name: Mul98 value: 98 - name: Mul99 value: 99 - name: Mul100 value: 100 - name: Mul101 value: 101 - name: Mul102 value: 102 - name: Mul103 value: 103 - name: Mul104 value: 104 - name: Mul105 value: 105 - name: Mul106 value: 106 - name: Mul107 value: 107 - name: Mul108 value: 108 - name: Mul109 value: 109 - name: Mul110 value: 110 - name: Mul111 value: 111 - name: Mul112 value: 112 - name: Mul113 value: 113 - name: Mul114 value: 114 - name: Mul115 value: 115 - name: Mul116 value: 116 - name: Mul117 value: 117 - name: Mul118 value: 118 - name: Mul119 value: 119 - name: Mul120 value: 120 - name: Mul121 value: 121 - name: Mul122 value: 122 - name: Mul123 value: 123 - name: Mul124 value: 124 - name: Mul125 value: 125 - name: Mul126 value: 126 - name: Mul127 value: 127 enum/PLLP: bit_size: 5 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 - name: Div9 value: 8 - name: Div10 value: 9 - name: Div11 value: 10 - name: Div12 value: 11 - name: Div13 value: 12 - name: Div14 value: 13 - name: Div15 value: 14 - name: Div16 value: 15 - name: Div17 value: 16 - name: Div18 value: 17 - name: Div19 value: 18 - name: Div20 value: 19 - name: Div21 value: 20 - name: Div22 value: 21 - name: Div23 value: 22 - name: Div24 value: 23 - name: Div25 value: 24 - name: Div26 value: 25 - name: Div27 value: 26 - name: Div28 value: 27 - name: Div29 value: 28 - name: Div30 value: 29 - name: Div31 value: 30 enum/PLLQ: bit_size: 3 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 enum/PLLR: bit_size: 3 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 enum/PLLSRC: bit_size: 2 variants: - name: DISABLE description: No clock selected as PLL entry clock source value: 0 - name: MSI description: MSI selected as PLL entry clock source value: 1 - name: HSI description: HSI selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source value: 3 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK divided by 2 value: 4 - name: Div4 description: HCLK divided by 4 value: 5 - name: Div8 description: HCLK divided by 8 value: 6 - name: Div16 description: HCLK divided by 16 value: 7 enum/RNGSEL: bit_size: 2 variants: - name: PLL1_Q value: 0 - name: LSI value: 1 - name: LSE value: 2 - name: MSI value: 3 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE description: No clock selected value: 0 - name: LSE description: LSE oscillator clock selected value: 1 - name: LSI description: LSI oscillator clock selected value: 2 - name: HSE description: HSE oscillator clock divided by 32 selected value: 3 enum/SW: bit_size: 2 variants: - name: MSI value: 0 - name: HSI value: 1 - name: HSE value: 2 - name: PLL1_R value: 3