# DAC v3, only used in L4. # Adds CCR, MCR, SHSR, SHHR, SHRR registers. # Adds CEN fields to CR and BWST and CAL_FLAG fields to SR. # Deletes BOFF fields from CR. block/DAC: description: Digital-to-analog converter items: - name: CR description: control register byte_offset: 0 fieldset: CR - name: SWTRIGR description: software trigger register byte_offset: 4 access: Write fieldset: SWTRIGR - name: DHR12R description: channel 12-bit right-aligned data holding register array: len: 2 stride: 12 byte_offset: 8 fieldset: DHR12R - name: DHR12L description: channel 12-bit left-aligned data holding register array: len: 2 stride: 12 byte_offset: 12 fieldset: DHR12L - name: DHR8R description: channel 8-bit right-aligned data holding register array: len: 2 stride: 12 byte_offset: 16 fieldset: DHR8R - name: DHR12RD description: dual 12-bit right-aligned data holding register byte_offset: 32 fieldset: DHR12RD - name: DHR12LD description: dual 12-bit left aligned data holding register byte_offset: 36 fieldset: DHR12LD - name: DHR8RD description: dual 8-bit right aligned data holding register byte_offset: 40 fieldset: DHR8RD - name: DOR description: channel data output register array: len: 2 stride: 4 byte_offset: 44 access: Read fieldset: DOR - name: SR description: status register byte_offset: 52 fieldset: SR - name: CCR description: calibration control register byte_offset: 56 fieldset: CCR - name: MCR description: mode control register byte_offset: 60 fieldset: MCR - name: SHSR description: sample and hold sample time register array: len: 2 stride: 4 byte_offset: 64 fieldset: SHSR - name: SHHR description: sample and hold hold time register byte_offset: 72 fieldset: SHHR - name: SHRR description: sample and hold refresh time register byte_offset: 76 fieldset: SHRR fieldset/CCR: description: calibration control register fields: - name: OTRIM description: channel offset trimming value bit_offset: 0 bit_size: 5 array: len: 2 stride: 16 fieldset/CR: description: control register fields: - name: EN description: channel enable bit_offset: 0 bit_size: 1 array: len: 2 stride: 16 - name: TEN description: channel trigger enable bit_offset: 2 bit_size: 1 array: len: 2 stride: 16 - name: TSEL description: channel trigger selection bit_offset: 3 bit_size: 3 array: len: 2 stride: 16 - name: WAVE description: channel noise/triangle wave generation enable bit_offset: 6 bit_size: 2 array: len: 2 stride: 16 enum: WAVE - name: MAMP description: channel mask/amplitude selector bit_offset: 8 bit_size: 4 array: len: 2 stride: 16 - name: DMAEN description: channel DMA enable bit_offset: 12 bit_size: 1 array: len: 2 stride: 16 - name: DMAUDRIE description: channel DMA Underrun Interrupt enable bit_offset: 13 bit_size: 1 array: len: 2 stride: 16 - name: CEN description: DAC channel calibration enable bit_offset: 14 bit_size: 1 array: len: 2 stride: 16 fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: - name: DHR description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 fieldset/DHR12LD: description: dual 12-bit left aligned data holding register fields: - name: DHR description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 array: len: 2 stride: 16 fieldset/DHR12R: description: channel 12-bit right-aligned data holding register fields: - name: DHR description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 fieldset/DHR12RD: description: dual 12-bit right-aligned data holding register fields: - name: DHR description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 array: len: 2 stride: 16 fieldset/DHR8R: description: channel 8-bit right-aligned data holding register fields: - name: DHR description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 fieldset/DHR8RD: description: dual 8-bit right aligned data holding register fields: - name: DHR description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 array: len: 2 stride: 8 fieldset/DOR: description: channel data output register fields: - name: DOR description: channel data output bit_offset: 0 bit_size: 12 fieldset/MCR: description: mode control register fields: - name: MODE description: DAC channel mode bit_offset: 0 bit_size: 3 enum: MODE array: len: 2 stride: 16 fieldset/SHHR: description: sample and hold hold time register fields: - name: THOLD description: channel hold time bit_offset: 0 bit_size: 10 array: len: 2 stride: 16 fieldset/SHRR: description: sample and hold refresh time register fields: - name: TREFRESH description: channel refresh time bit_offset: 0 bit_size: 8 array: len: 2 stride: 16 fieldset/SHSR: description: sample and hold sample time register fields: - name: TSAMPLE description: channel sample time bit_offset: 0 bit_size: 10 fieldset/SR: description: status register fields: - name: DMAUDR description: channel DMA underrun flag bit_offset: 13 bit_size: 1 array: len: 2 stride: 16 - name: CAL_FLAG description: channel calibration offset status bit_offset: 14 bit_size: 1 array: len: 2 stride: 16 - name: BWST description: channel busy writing sample time flag bit_offset: 15 bit_size: 1 array: len: 2 stride: 16 fieldset/SWTRIGR: description: software trigger register fields: - name: SWTRIG description: channel software trigger bit_offset: 0 bit_size: 1 array: len: 2 stride: 1 enum/MODE: bit_size: 3 variants: - name: NORMAL_EXT_BUFEN description: Normal mode, external pin only, buffer enabled value: 0 - name: NORMAL_EXT_INT_BUFEN description: Normal mode, external pin and internal peripherals, buffer enabled value: 1 - name: NORMAL_EXT_BUFDIS description: Normal mode, external pin only, buffer disabled value: 2 - name: NORMAL_INT_BUFDIS description: Normal mode, internal peripherals only, buffer disabled value: 3 - name: SAMPHOLD_EXT_BUFEN description: Sample and hold mode, external pin only, buffer enabled value: 4 - name: SAMPHOLD_EXT_INT_BUFEN description: Sample and hold mode, external pin and internal peripherals, buffer enabled value: 5 - name: SAMPHOLD_EXT_INT_BUFDIS description: Sample and hold mode, external pin and internal peripherals, buffer disabled value: 6 - name: SAMPHOLD_INT_BUFDIS description: Sample and hold mode, internal peripherals only, buffer disabled value: 7 enum/WAVE: bit_size: 2 variants: - name: Disabled description: Wave generation disabled value: 0 - name: Noise description: Noise wave generation enabled value: 1 - name: Triangle description: Triangle wave generation enabled value: 2