block/RCC: description: Reset and clock control items: - name: CR description: Clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: Internal clock sources calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: Clock configuration register byte_offset: 8 fieldset: CFGR - name: PLLCFGR description: PLL configuration register byte_offset: 12 fieldset: PLLCFGR - name: CRRCR description: RCC clock recovery RC register byte_offset: 20 access: Read fieldset: CRRCR - name: CIER description: Clock interrupt enable register byte_offset: 24 fieldset: CIER - name: CIFR description: Clock interrupt flag register byte_offset: 28 access: Read fieldset: CIFR - name: CICR description: Clock interrupt clear register byte_offset: 32 access: Write fieldset: CICR - name: GPIORSTR description: GPIO reset register byte_offset: 36 fieldset: GPIORSTR - name: AHBRSTR description: AHB peripheral reset register byte_offset: 40 fieldset: AHBRSTR - name: APBRSTR1 description: APB peripheral reset register 1 byte_offset: 44 fieldset: APBRSTR1 - name: APBRSTR2 description: APB peripheral reset register 2 byte_offset: 48 fieldset: APBRSTR2 - name: GPIOENR description: GPIO clock enable register byte_offset: 52 fieldset: GPIOENR - name: AHBENR description: AHB peripheral clock enable register byte_offset: 56 fieldset: AHBENR - name: APBENR1 description: APB peripheral clock enable register 1 byte_offset: 60 fieldset: APBENR1 - name: APBENR2 description: APB peripheral clock enable register 2 byte_offset: 64 fieldset: APBENR2 - name: GPIOSMENR description: GPIO in Sleep mode clock enable register byte_offset: 68 fieldset: GPIOSMENR - name: AHBSMENR description: AHB peripheral clock enable in Sleep mode register byte_offset: 72 fieldset: AHBSMENR - name: APBSMENR1 description: APB peripheral clock enable in Sleep mode register 1 byte_offset: 76 fieldset: APBSMENR1 - name: APBSMENR2 description: APB peripheral clock enable in Sleep mode register 2 byte_offset: 80 fieldset: APBSMENR2 - name: CCIPR description: Peripherals independent clock configuration register byte_offset: 84 fieldset: CCIPR - name: CCIPR2 description: Peripherals independent clock configuration register 2 byte_offset: 88 fieldset: CCIPR2 - name: BDCR description: RTC domain control register byte_offset: 92 fieldset: BDCR - name: CSR description: Control/status register byte_offset: 96 fieldset: CSR fieldset/AHBENR: description: AHB peripheral clock enable register fields: - name: DMA1EN description: DMA1 clock enable bit_offset: 0 bit_size: 1 - name: DMA2EN description: DMA2 clock enable bit_offset: 1 bit_size: 1 - name: FLASHEN description: Flash memory interface clock enable bit_offset: 8 bit_size: 1 - name: CRCEN description: CRC clock enable bit_offset: 12 bit_size: 1 - name: AESEN description: AES hardware accelerator bit_offset: 16 bit_size: 1 - name: RNGEN description: Random number generator clock enable bit_offset: 18 bit_size: 1 fieldset/AHBRSTR: description: AHB peripheral reset register fields: - name: DMA1RST description: DMA1 reset bit_offset: 0 bit_size: 1 - name: DMA2RST description: DMA1 reset bit_offset: 1 bit_size: 1 - name: FLASHRST description: FLASH reset bit_offset: 8 bit_size: 1 - name: CRCRST description: CRC reset bit_offset: 12 bit_size: 1 - name: AESRST description: AES hardware accelerator reset bit_offset: 16 bit_size: 1 - name: RNGRST description: Random number generator reset bit_offset: 18 bit_size: 1 fieldset/AHBSMENR: description: AHB peripheral clock enable in Sleep mode register fields: - name: DMA1SMEN description: DMA1 clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: DMA2SMEN description: DMA2 clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: FLASHSMEN description: Flash memory interface clock enable during Sleep mode bit_offset: 8 bit_size: 1 - name: SRAMSMEN description: SRAM clock enable during Sleep mode bit_offset: 9 bit_size: 1 - name: CRCSMEN description: CRC clock enable during Sleep mode bit_offset: 12 bit_size: 1 - name: AESSMEN description: AES hardware accelerator clock enable during Sleep mode bit_offset: 16 bit_size: 1 - name: RNGSMEN description: Random number generator clock enable during Sleep mode bit_offset: 18 bit_size: 1 fieldset/APBENR1: description: APB peripheral clock enable register 1 fields: - name: TIM2EN description: TIM2 timer clock enable bit_offset: 0 bit_size: 1 - name: TIM3EN description: TIM3 timer clock enable bit_offset: 1 bit_size: 1 - name: TIM4EN description: TIM4 timer clock enable bit_offset: 2 bit_size: 1 - name: TIM6EN description: TIM6 timer clock enable bit_offset: 4 bit_size: 1 - name: TIM7EN description: TIM7 timer clock enable bit_offset: 5 bit_size: 1 - name: LPUART2EN description: LPUART2 clock enable bit_offset: 7 bit_size: 1 - name: USART5EN description: USART5EN bit_offset: 8 bit_size: 1 - name: USART6EN description: USART6EN bit_offset: 9 bit_size: 1 - name: RTCAPBEN description: RTC APB clock enable bit_offset: 10 bit_size: 1 - name: WWDGEN description: WWDG clock enable bit_offset: 11 bit_size: 1 - name: FDCANEN description: USBEN bit_offset: 12 bit_size: 1 - name: USBEN description: USBEN bit_offset: 13 bit_size: 1 - name: SPI2EN description: SPI2 clock enable bit_offset: 14 bit_size: 1 - name: SPI3EN description: SPI3 clock enable bit_offset: 15 bit_size: 1 - name: CRSEN description: CRSEN bit_offset: 16 bit_size: 1 - name: USART2EN description: USART2 clock enable bit_offset: 17 bit_size: 1 - name: USART3EN description: USART3 clock enable bit_offset: 18 bit_size: 1 - name: USART4EN description: USART4 clock enable bit_offset: 19 bit_size: 1 - name: LPUART1EN description: LPUART1 clock enable bit_offset: 20 bit_size: 1 - name: I2C1EN description: I2C1 clock enable bit_offset: 21 bit_size: 1 - name: I2C2EN description: I2C2 clock enable bit_offset: 22 bit_size: 1 - name: I2C3EN description: I2C3 clock enable bit_offset: 23 bit_size: 1 - name: CECEN description: HDMI CEC clock enable bit_offset: 24 bit_size: 1 - name: UCPD1EN description: UCPD1 clock enable bit_offset: 25 bit_size: 1 - name: UCPD2EN description: UCPD2 clock enable bit_offset: 26 bit_size: 1 - name: DBGEN description: Debug support clock enable bit_offset: 27 bit_size: 1 - name: PWREN description: Power interface clock enable bit_offset: 28 bit_size: 1 - name: DAC1EN description: DAC1 interface clock enable bit_offset: 29 bit_size: 1 - name: LPTIM2EN description: LPTIM2 clock enable bit_offset: 30 bit_size: 1 - name: LPTIM1EN description: LPTIM1 clock enable bit_offset: 31 bit_size: 1 fieldset/APBENR2: description: APB peripheral clock enable register 2 fields: - name: SYSCFGEN description: SYSCFG, COMP and VREFBUF clock enable bit_offset: 0 bit_size: 1 - name: TIM1EN description: TIM1 timer clock enable bit_offset: 11 bit_size: 1 - name: SPI1EN description: SPI1 clock enable bit_offset: 12 bit_size: 1 - name: USART1EN description: USART1 clock enable bit_offset: 14 bit_size: 1 - name: TIM14EN description: TIM14 timer clock enable bit_offset: 15 bit_size: 1 - name: TIM15EN description: TIM15 timer clock enable bit_offset: 16 bit_size: 1 - name: TIM16EN description: TIM16 timer clock enable bit_offset: 17 bit_size: 1 - name: TIM17EN description: TIM16 timer clock enable bit_offset: 18 bit_size: 1 - name: ADCEN description: ADC clock enable bit_offset: 20 bit_size: 1 fieldset/APBRSTR1: description: APB peripheral reset register 1 fields: - name: TIM2RST description: TIM2 timer reset bit_offset: 0 bit_size: 1 - name: TIM3RST description: TIM3 timer reset bit_offset: 1 bit_size: 1 - name: TIM4RST description: TIM4 timer reset bit_offset: 2 bit_size: 1 - name: TIM6RST description: TIM6 timer reset bit_offset: 4 bit_size: 1 - name: TIM7RST description: TIM7 timer reset bit_offset: 5 bit_size: 1 - name: LPUART2RST description: LPUART2RST bit_offset: 7 bit_size: 1 - name: USART5RST description: USART5RST bit_offset: 8 bit_size: 1 - name: USART6RST description: USART6RST bit_offset: 9 bit_size: 1 - name: FDCANRST description: FDCANRST bit_offset: 12 bit_size: 1 - name: USBRST description: USBRST bit_offset: 13 bit_size: 1 - name: SPI2RST description: SPI2 reset bit_offset: 14 bit_size: 1 - name: SPI3RST description: SPI3 reset bit_offset: 15 bit_size: 1 - name: CRSRST description: CRSRST bit_offset: 16 bit_size: 1 - name: USART2RST description: USART2 reset bit_offset: 17 bit_size: 1 - name: USART3RST description: USART3 reset bit_offset: 18 bit_size: 1 - name: USART4RST description: USART4 reset bit_offset: 19 bit_size: 1 - name: LPUART1RST description: LPUART1 reset bit_offset: 20 bit_size: 1 - name: I2C1RST description: I2C1 reset bit_offset: 21 bit_size: 1 - name: I2C2RST description: I2C2 reset bit_offset: 22 bit_size: 1 - name: I2C3RST description: I2C3RST reset bit_offset: 23 bit_size: 1 - name: CECRST description: HDMI CEC reset bit_offset: 24 bit_size: 1 - name: UCPD1RST description: UCPD1 reset bit_offset: 25 bit_size: 1 - name: UCPD2RST description: UCPD2 reset bit_offset: 26 bit_size: 1 - name: DBGRST description: Debug support reset bit_offset: 27 bit_size: 1 - name: PWRRST description: Power interface reset bit_offset: 28 bit_size: 1 - name: DAC1RST description: DAC1 interface reset bit_offset: 29 bit_size: 1 - name: LPTIM2RST description: Low Power Timer 2 reset bit_offset: 30 bit_size: 1 - name: LPTIM1RST description: Low Power Timer 1 reset bit_offset: 31 bit_size: 1 fieldset/APBRSTR2: description: APB peripheral reset register 2 fields: - name: SYSCFGRST description: SYSCFG, COMP and VREFBUF reset bit_offset: 0 bit_size: 1 - name: TIM1RST description: TIM1 timer reset bit_offset: 11 bit_size: 1 - name: SPI1RST description: SPI1 reset bit_offset: 12 bit_size: 1 - name: USART1RST description: USART1 reset bit_offset: 14 bit_size: 1 - name: TIM14RST description: TIM14 timer reset bit_offset: 15 bit_size: 1 - name: TIM15RST description: TIM15 timer reset bit_offset: 16 bit_size: 1 - name: TIM16RST description: TIM16 timer reset bit_offset: 17 bit_size: 1 - name: TIM17RST description: TIM17 timer reset bit_offset: 18 bit_size: 1 - name: ADCRST description: ADC reset bit_offset: 20 bit_size: 1 fieldset/APBSMENR1: description: APB peripheral clock enable in Sleep mode register 1 fields: - name: TIM2SMEN description: TIM2 timer clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: TIM3SMEN description: TIM3 timer clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: TIM4SMEN description: TIM4 timer clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: TIM6SMEN description: TIM6 timer clock enable during Sleep mode bit_offset: 4 bit_size: 1 - name: TIM7SMEN description: TIM7 timer clock enable during Sleep mode bit_offset: 5 bit_size: 1 - name: LPUART2SMEN description: LPUART2 clock enable bit_offset: 7 bit_size: 1 - name: USART5SMEN description: USART5 clock enable bit_offset: 8 bit_size: 1 - name: USART6SMEN description: USART6 clock enable bit_offset: 9 bit_size: 1 - name: RTCAPBSMEN description: RTC APB clock enable during Sleep mode bit_offset: 10 bit_size: 1 - name: WWDGSMEN description: WWDG clock enable during Sleep mode bit_offset: 11 bit_size: 1 - name: FDCANSMEN description: FDCAN clock enable during Sleep mode bit_offset: 12 bit_size: 1 - name: USBSMEN description: USB clock enable during Sleep mode bit_offset: 13 bit_size: 1 - name: SPI2SMEN description: SPI2 clock enable during Sleep mode bit_offset: 14 bit_size: 1 - name: SPI3SMEN description: SPI3 clock enable during Sleep mode bit_offset: 15 bit_size: 1 - name: CRSSSMEN description: CRSS clock enable during Sleep mode bit_offset: 16 bit_size: 1 - name: USART2SMEN description: USART2 clock enable during Sleep mode bit_offset: 17 bit_size: 1 - name: USART3SMEN description: USART3 clock enable during Sleep mode bit_offset: 18 bit_size: 1 - name: USART4SMEN description: USART4 clock enable during Sleep mode bit_offset: 19 bit_size: 1 - name: LPUART1SMEN description: LPUART1 clock enable during Sleep mode bit_offset: 20 bit_size: 1 - name: I2C1SMEN description: I2C1 clock enable during Sleep mode bit_offset: 21 bit_size: 1 - name: I2C2SMEN description: I2C2 clock enable during Sleep mode bit_offset: 22 bit_size: 1 - name: I2C3SMEN description: I2C3 clock enable during Sleep mode bit_offset: 23 bit_size: 1 - name: CECSMEN description: HDMI CEC clock enable during Sleep mode bit_offset: 24 bit_size: 1 - name: UCPD1SMEN description: UCPD1 clock enable during Sleep mode bit_offset: 25 bit_size: 1 - name: UCPD2SMEN description: UCPD2 clock enable during Sleep mode bit_offset: 26 bit_size: 1 - name: DBGSMEN description: Debug support clock enable during Sleep mode bit_offset: 27 bit_size: 1 - name: PWRSMEN description: Power interface clock enable during Sleep mode bit_offset: 28 bit_size: 1 - name: DAC1SMEN description: DAC1 interface clock enable during Sleep mode bit_offset: 29 bit_size: 1 - name: LPTIM2SMEN description: Low Power Timer 2 clock enable during Sleep mode bit_offset: 30 bit_size: 1 - name: LPTIM1SMEN description: Low Power Timer 1 clock enable during Sleep mode bit_offset: 31 bit_size: 1 fieldset/APBSMENR2: description: APB peripheral clock enable in Sleep mode register 2 fields: - name: SYSCFGSMEN description: SYSCFG, COMP and VREFBUF clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: TIM1SMEN description: TIM1 timer clock enable during Sleep mode bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: SPI1 clock enable during Sleep mode bit_offset: 12 bit_size: 1 - name: USART1SMEN description: USART1 clock enable during Sleep mode bit_offset: 14 bit_size: 1 - name: TIM14SMEN description: TIM14 timer clock enable during Sleep mode bit_offset: 15 bit_size: 1 - name: TIM15SMEN description: TIM15 timer clock enable during Sleep mode bit_offset: 16 bit_size: 1 - name: TIM16SMEN description: TIM16 timer clock enable during Sleep mode bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: TIM16 timer clock enable during Sleep mode bit_offset: 18 bit_size: 1 - name: ADCSMEN description: ADC clock enable during Sleep mode bit_offset: 20 bit_size: 1 fieldset/BDCR: description: RTC domain control register fields: - name: LSEON description: LSE oscillator enable bit_offset: 0 bit_size: 1 - name: LSERDY description: LSE oscillator ready bit_offset: 1 bit_size: 1 - name: LSEBYP description: LSE oscillator bypass bit_offset: 2 bit_size: 1 - name: LSEDRV description: LSE oscillator drive capability bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: CSS on LSE enable bit_offset: 5 bit_size: 1 - name: LSECSSD description: CSS on LSE failure Detection bit_offset: 6 bit_size: 1 - name: RTCSEL description: RTC clock source selection bit_offset: 8 bit_size: 2 enum: RTCSEL - name: RTCEN description: RTC clock enable bit_offset: 15 bit_size: 1 - name: BDRST description: RTC domain software reset bit_offset: 16 bit_size: 1 - name: LSCOEN description: Low-speed clock output (LSCO) enable bit_offset: 24 bit_size: 1 - name: LSCOSEL description: Low-speed clock output selection bit_offset: 25 bit_size: 1 fieldset/CCIPR: description: Peripherals independent clock configuration register fields: - name: USART1SEL description: USART1 clock source selection bit_offset: 0 bit_size: 2 enum: USART1SEL - name: USART2SEL description: USART2 clock source selection bit_offset: 2 bit_size: 2 enum: USART2SEL - name: USART3SEL description: USART3 clock source selection bit_offset: 4 bit_size: 2 enum: USART3SEL - name: CECSEL description: HDMI CEC clock source selection bit_offset: 6 bit_size: 1 enum: CECSEL - name: LPUART2SEL description: LPUART2 clock source selection bit_offset: 8 bit_size: 2 enum: LPUART2SEL - name: LPUART1SEL description: LPUART1 clock source selection bit_offset: 10 bit_size: 2 enum: LPUART1SEL - name: I2C1SEL description: I2C1 clock source selection bit_offset: 12 bit_size: 2 enum: I2C1SEL - name: I2S2SEL description: I2S1 clock source selection bit_offset: 14 bit_size: 2 enum: I2C2I2S1SEL - name: LPTIM1SEL description: LPTIM1 clock source selection bit_offset: 18 bit_size: 2 enum: LPTIM1SEL - name: LPTIM2SEL description: LPTIM2 clock source selection bit_offset: 20 bit_size: 2 enum: LPTIM2SEL - name: TIM1SEL description: TIM1 clock source selection bit_offset: 22 bit_size: 1 enum: TIM1SEL - name: TIM15SEL description: TIM15 clock source selection bit_offset: 24 bit_size: 1 enum: TIM15SEL - name: RNGSEL description: RNG clock source selection bit_offset: 26 bit_size: 2 enum: RNGSEL - name: RNGDIV description: Division factor of RNG clock divider bit_offset: 28 bit_size: 2 enum: RNGDIV - name: ADCSEL description: ADCs clock source selection bit_offset: 30 bit_size: 2 enum: ADCSEL fieldset/CCIPR2: description: Peripherals independent clock configuration register 2 fields: - name: I2S1SEL description: I2S1SEL bit_offset: 0 bit_size: 2 enum: I2S1SEL - name: I2S2SEL description: I2S2SEL bit_offset: 2 bit_size: 2 enum: I2S2SEL - name: FDCANSEL description: FDCANSEL bit_offset: 8 bit_size: 2 enum: FDCANSEL - name: USBSEL description: USBSEL bit_offset: 12 bit_size: 2 enum: USBSEL fieldset/CFGR: description: Clock configuration register fields: - name: SW description: System clock switch bit_offset: 0 bit_size: 3 enum: SW - name: SWS description: System clock switch status bit_offset: 3 bit_size: 3 enum: SW - name: HPRE description: AHB prescaler bit_offset: 8 bit_size: 4 enum: HPRE - name: PPRE description: APB prescaler bit_offset: 12 bit_size: 3 enum: PPRE - name: MCO2SEL description: MCO2SEL bit_offset: 16 bit_size: 4 enum: MCOSEL - name: MCO2PRE description: MCO2PRE bit_offset: 20 bit_size: 4 enum: MCOPRE - name: MCO1SEL description: Microcontroller clock output bit_offset: 24 bit_size: 3 enum: MCOSEL - name: MCO1PRE description: Microcontroller clock output prescaler bit_offset: 28 bit_size: 3 enum: MCOPRE fieldset/CICR: description: Clock interrupt clear register fields: - name: LSIRDYC description: LSI ready interrupt clear bit_offset: 0 bit_size: 1 - name: LSERDYC description: LSE ready interrupt clear bit_offset: 1 bit_size: 1 - name: HSI48RDYC description: HSI48RDYC bit_offset: 2 bit_size: 1 - name: HSIRDYC description: HSI ready interrupt clear bit_offset: 3 bit_size: 1 - name: HSERDYC description: HSE ready interrupt clear bit_offset: 4 bit_size: 1 - name: PLLSYSRDYC description: PLL ready interrupt clear bit_offset: 5 bit_size: 1 - name: CSSC description: Clock security system interrupt clear bit_offset: 8 bit_size: 1 - name: LSECSSC description: LSE Clock security system interrupt clear bit_offset: 9 bit_size: 1 fieldset/CIER: description: Clock interrupt enable register fields: - name: LSIRDYIE description: LSI ready interrupt enable bit_offset: 0 bit_size: 1 - name: LSERDYIE description: LSE ready interrupt enable bit_offset: 1 bit_size: 1 - name: HSIRDYIE description: HSI ready interrupt enable bit_offset: 3 bit_size: 1 - name: HSERDYIE description: HSE ready interrupt enable bit_offset: 4 bit_size: 1 - name: PLLSYSRDYIE description: PLL ready interrupt enable bit_offset: 5 bit_size: 1 fieldset/CIFR: description: Clock interrupt flag register fields: - name: LSIRDYF description: LSI ready interrupt flag bit_offset: 0 bit_size: 1 - name: LSERDYF description: LSE ready interrupt flag bit_offset: 1 bit_size: 1 - name: HSI48RDYF description: HSI48RDYF bit_offset: 2 bit_size: 1 - name: HSIRDYF description: HSI ready interrupt flag bit_offset: 3 bit_size: 1 - name: HSERDYF description: HSE ready interrupt flag bit_offset: 4 bit_size: 1 - name: PLLSYSRDYF description: PLL ready interrupt flag bit_offset: 5 bit_size: 1 - name: CSSF description: Clock security system interrupt flag bit_offset: 8 bit_size: 1 - name: LSECSSF description: LSE Clock security system interrupt flag bit_offset: 9 bit_size: 1 fieldset/CR: description: Clock control register fields: - name: HSION description: HSI16 clock enable bit_offset: 8 bit_size: 1 - name: HSIKERON description: HSI16 always enable for peripheral kernels bit_offset: 9 bit_size: 1 - name: HSIRDY description: HSI16 clock ready flag bit_offset: 10 bit_size: 1 - name: HSIDIV description: HSI16 clock division factor bit_offset: 11 bit_size: 3 enum: HSIDIV - name: HSEON description: HSE clock enable bit_offset: 16 bit_size: 1 - name: HSERDY description: HSE clock ready flag bit_offset: 17 bit_size: 1 - name: HSEBYP description: HSE crystal oscillator bypass bit_offset: 18 bit_size: 1 - name: CSSON description: Clock security system enable bit_offset: 19 bit_size: 1 - name: HSI48ON description: HSI48ON bit_offset: 22 bit_size: 1 - name: HSI48RDY description: HSI48RDY bit_offset: 23 bit_size: 1 - name: PLLON description: PLL enable bit_offset: 24 bit_size: 1 - name: PLLRDY description: PLL clock ready flag bit_offset: 25 bit_size: 1 fieldset/CRRCR: description: RCC clock recovery RC register fields: - name: HSI48CAL description: HSI48 clock calibration bit_offset: 0 bit_size: 9 fieldset/CSR: description: Control/status register fields: - name: LSION description: LSI oscillator enable bit_offset: 0 bit_size: 1 - name: LSIRDY description: LSI oscillator ready bit_offset: 1 bit_size: 1 - name: RMVF description: Remove reset flags bit_offset: 23 bit_size: 1 - name: OBLRSTF description: Option byte loader reset flag bit_offset: 25 bit_size: 1 - name: PINRSTF description: Pin reset flag bit_offset: 26 bit_size: 1 - name: PWRRSTF description: BOR or POR/PDR flag bit_offset: 27 bit_size: 1 - name: SFTRSTF description: Software reset flag bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: Independent window watchdog reset flag bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 fieldset/GPIOENR: description: GPIO clock enable register fields: - name: GPIOAEN description: I/O port A clock enable bit_offset: 0 bit_size: 1 - name: GPIOBEN description: I/O port B clock enable bit_offset: 1 bit_size: 1 - name: GPIOCEN description: I/O port C clock enable bit_offset: 2 bit_size: 1 - name: GPIODEN description: I/O port D clock enable bit_offset: 3 bit_size: 1 - name: GPIOFEN description: I/O port F clock enable bit_offset: 5 bit_size: 1 fieldset/GPIORSTR: description: GPIO reset register fields: - name: GPIOARST description: I/O port A reset bit_offset: 0 bit_size: 1 - name: GPIOBRST description: I/O port B reset bit_offset: 1 bit_size: 1 - name: GPIOCRST description: I/O port C reset bit_offset: 2 bit_size: 1 - name: GPIODRST description: I/O port D reset bit_offset: 3 bit_size: 1 - name: GPIOFRST description: I/O port F reset bit_offset: 5 bit_size: 1 fieldset/GPIOSMENR: description: GPIO in Sleep mode clock enable register fields: - name: GPIOASMEN description: I/O port A clock enable during Sleep mode bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: I/O port B clock enable during Sleep mode bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: I/O port C clock enable during Sleep mode bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: I/O port D clock enable during Sleep mode bit_offset: 3 bit_size: 1 - name: GPIOFSMEN description: I/O port F clock enable during Sleep mode bit_offset: 5 bit_size: 1 fieldset/ICSCR: description: Internal clock sources calibration register fields: - name: HSICAL description: HSI16 clock calibration bit_offset: 0 bit_size: 8 - name: HSITRIM description: HSI16 clock trimming bit_offset: 8 bit_size: 7 fieldset/PLLCFGR: description: PLL configuration register fields: - name: PLLSRC description: PLL input clock source bit_offset: 0 bit_size: 2 enum: PLLSRC - name: PLLM description: Division factor M of the PLL input clock divider bit_offset: 4 bit_size: 3 enum: PLLM - name: PLLN description: PLL frequency multiplication factor N bit_offset: 8 bit_size: 7 enum: PLLN - name: PLLPEN description: PLLPCLK clock output enable bit_offset: 16 bit_size: 1 - name: PLLP description: PLL VCO division factor P for PLLPCLK clock output bit_offset: 17 bit_size: 5 enum: PLLP - name: PLLQEN description: PLLQCLK clock output enable bit_offset: 24 bit_size: 1 - name: PLLQ description: PLL VCO division factor Q for PLLQCLK clock output bit_offset: 25 bit_size: 3 enum: PLLQ - name: PLLREN description: PLLRCLK clock output enable bit_offset: 28 bit_size: 1 - name: PLLR description: PLL VCO division factor R for PLLRCLK clock output bit_offset: 29 bit_size: 3 enum: PLLR enum/ADCSEL: bit_size: 2 variants: - name: SYS description: SYSCLK used as ADC clock source value: 0 - name: PLL1_P description: PLLPCLK used as ADC clock source value: 1 - name: HSI description: HSI16 used as ADC clock source value: 2 enum/CECSEL: bit_size: 1 variants: - name: HSI_DIV_488 description: HSI16 divided by 488 used as CEC clock value: 0 - name: LSE description: LSE used as CEC clock value: 1 enum/FDCANSEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as FDCAN clock source value: 0 - name: PLL1_Q description: PLLQCLK used as FDCAN clock source value: 1 - name: HSE description: HSE used as FDCAN clock source value: 2 enum/HPRE: bit_size: 4 variants: - name: Div1 description: SYSCLK not divided value: 0 - name: Div2 description: SYSCLK is divided by 2 value: 8 - name: Div4 description: SYSCLK is divided by 4 value: 9 - name: Div8 description: SYSCLK is divided by 8 value: 10 - name: Div16 description: SYSCLK is divided by 16 value: 11 - name: Div64 description: SYSCLK is divided by 64 value: 12 - name: Div128 description: SYSCLK is divided by 128 value: 13 - name: Div256 description: SYSCLK is divided by 256 value: 14 - name: Div512 description: SYSCLK is divided by 512 value: 15 enum/HSIDIV: bit_size: 3 variants: - name: Div1 description: HSI clock is not divided value: 0 - name: Div2 description: HSI clock is divided by 2 value: 1 - name: Div4 description: HSI clock is divided by 4 value: 2 - name: Div8 description: HSI clock is divided by 8 value: 3 - name: Div16 description: HSI clock is divided by 16 value: 4 - name: Div32 description: HSI clock is divided by 32 value: 5 - name: Div64 description: HSI clock is divided by 64 value: 6 - name: Div128 description: HSI clock is divided by 128 value: 7 enum/I2C1SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as I2C1 clock source value: 0 - name: SYS description: SYSCLK used as I2C1 clock source value: 1 - name: HSI description: HSI16 used as I2C1 clock source value: 2 enum/I2C2I2S1SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as I2C2/I2S2 clock source value: 0 - name: SYS description: SYSCLK used as I2C2/I2S2 clock source value: 1 - name: HSI description: HSI16 used as I2C2/I2S2 clock source value: 2 - name: I2S_CKIN description: External clock used as I2C2/I2S2 clock source value: 3 enum/I2S1SEL: bit_size: 2 variants: - name: SYS description: SYSCLK used as I2S1 clock source value: 0 - name: PLL1_P description: PLLPCLK used as I2S1 clock source value: 1 - name: HSI description: HSI used as I2S1 clock source value: 2 - name: I2S_CKIN description: External clock used as I2S1 clock source value: 3 enum/I2S2SEL: bit_size: 2 variants: - name: SYS description: SYSCLK used as I2S2 clock source value: 0 - name: PLL1_P description: PLLPCLK used as I2S2 clock source value: 1 - name: HSI description: HSI used as I2S2 clock source value: 2 - name: I2S_CKIN description: External clock used as I2S2 clock source value: 3 enum/LPTIM1SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as LPTIM1 clock source value: 0 - name: LSI description: LSI used as LPTIM1 clock source value: 1 - name: HSI description: HSI16 used as LPTIM1 clock source value: 2 - name: LSE description: LSE used as LPTIM1 clock source value: 3 enum/LPTIM2SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as LPTIM2 clock source value: 0 - name: LSI description: LSI used as LPTIM2 clock source value: 1 - name: HSI description: HSI16 used as LPTIM2 clock source value: 2 - name: LSE description: LSE used as LPTIM2 clock source value: 3 enum/LPUART1SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as LPUART1 clock source value: 0 - name: SYS description: SYSCLK used as LPUART1 clock source value: 1 - name: HSI description: HSI16 used as LPUART1 clock source value: 2 - name: LSE description: LSE used as LPUART1 clock source value: 3 enum/LPUART2SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as LPUART2 clock source value: 0 - name: SYS description: SYSCLK used as LPUART2 clock source value: 1 - name: HSI description: HSI16 used as LPUART2 clock source value: 2 - name: LSE description: LSE used as LPUART2 clock source value: 3 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/MCOPRE: bit_size: 4 variants: - name: Div1 description: MCO1 not divided value: 0 - name: Div2 description: MCO clock is divided by 2 value: 1 - name: Div4 description: MCO clock is divided by 4 value: 2 - name: Div8 description: MCO clock is divided by 8 value: 3 - name: Div16 description: MCO clock is divided divided by 16 value: 4 - name: Div32 description: MCO clock is divided divided by 32 value: 5 - name: Div64 description: MCO clock is divided divided by 64 value: 6 - name: Div128 description: MCO clock is divided divided by 128 value: 7 - name: Div256 description: MCO clock is divided divided by 256 value: 8 - name: Div512 description: MCO clock is divided divided by 512 value: 9 - name: Div1024 description: MCO clock is divided divided by 1024 value: 10 enum/MCOSEL: bit_size: 4 variants: - name: DISABLE description: No clock, MCO output disabled value: 0 - name: SYS description: SYSCLK selected as MCO source value: 1 - name: HSI48 description: HSI48 selected as MCO source value: 2 - name: HSI description: HSI16 selected as MCO source value: 3 - name: HSE description: HSE selected as MCO source value: 4 - name: PLLRCLK description: PLLRCLK selected as MCO source value: 5 - name: LSI description: LSI selected as MCO source value: 6 - name: LSE description: LSE selected as MCO source value: 7 - name: PLL1_P description: PLLPCLK selected as MCO source value: 8 - name: PLL1_Q description: PLLQCLK selected as MCO source value: 9 - name: RTCCLK description: RTCCLK selected as MCO source value: 10 - name: RTC_WKUP description: RTC_Wakeup selected as MCO source value: 11 enum/PLLM: bit_size: 3 variants: - name: Div1 value: 0 - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 enum/PLLN: bit_size: 7 variants: - name: Mul8 value: 8 - name: Mul9 value: 9 - name: Mul10 value: 10 - name: Mul11 value: 11 - name: Mul12 value: 12 - name: Mul13 value: 13 - name: Mul14 value: 14 - name: Mul15 value: 15 - name: Mul16 value: 16 - name: Mul17 value: 17 - name: Mul18 value: 18 - name: Mul19 value: 19 - name: Mul20 value: 20 - name: Mul21 value: 21 - name: Mul22 value: 22 - name: Mul23 value: 23 - name: Mul24 value: 24 - name: Mul25 value: 25 - name: Mul26 value: 26 - name: Mul27 value: 27 - name: Mul28 value: 28 - name: Mul29 value: 29 - name: Mul30 value: 30 - name: Mul31 value: 31 - name: Mul32 value: 32 - name: Mul33 value: 33 - name: Mul34 value: 34 - name: Mul35 value: 35 - name: Mul36 value: 36 - name: Mul37 value: 37 - name: Mul38 value: 38 - name: Mul39 value: 39 - name: Mul40 value: 40 - name: Mul41 value: 41 - name: Mul42 value: 42 - name: Mul43 value: 43 - name: Mul44 value: 44 - name: Mul45 value: 45 - name: Mul46 value: 46 - name: Mul47 value: 47 - name: Mul48 value: 48 - name: Mul49 value: 49 - name: Mul50 value: 50 - name: Mul51 value: 51 - name: Mul52 value: 52 - name: Mul53 value: 53 - name: Mul54 value: 54 - name: Mul55 value: 55 - name: Mul56 value: 56 - name: Mul57 value: 57 - name: Mul58 value: 58 - name: Mul59 value: 59 - name: Mul60 value: 60 - name: Mul61 value: 61 - name: Mul62 value: 62 - name: Mul63 value: 63 - name: Mul64 value: 64 - name: Mul65 value: 65 - name: Mul66 value: 66 - name: Mul67 value: 67 - name: Mul68 value: 68 - name: Mul69 value: 69 - name: Mul70 value: 70 - name: Mul71 value: 71 - name: Mul72 value: 72 - name: Mul73 value: 73 - name: Mul74 value: 74 - name: Mul75 value: 75 - name: Mul76 value: 76 - name: Mul77 value: 77 - name: Mul78 value: 78 - name: Mul79 value: 79 - name: Mul80 value: 80 - name: Mul81 value: 81 - name: Mul82 value: 82 - name: Mul83 value: 83 - name: Mul84 value: 84 - name: Mul85 value: 85 - name: Mul86 value: 86 enum/PLLP: bit_size: 5 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 - name: Div9 value: 8 - name: Div10 value: 9 - name: Div11 value: 10 - name: Div12 value: 11 - name: Div13 value: 12 - name: Div14 value: 13 - name: Div15 value: 14 - name: Div16 value: 15 - name: Div17 value: 16 - name: Div18 value: 17 - name: Div19 value: 18 - name: Div20 value: 19 - name: Div21 value: 20 - name: Div22 value: 21 - name: Div23 value: 22 - name: Div24 value: 23 - name: Div25 value: 24 - name: Div26 value: 25 - name: Div27 value: 26 - name: Div28 value: 27 - name: Div29 value: 28 - name: Div30 value: 29 - name: Div31 value: 30 - name: Div32 value: 31 enum/PLLQ: bit_size: 3 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 enum/PLLR: bit_size: 3 variants: - name: Div2 value: 1 - name: Div3 value: 2 - name: Div4 value: 3 - name: Div5 value: 4 - name: Div6 value: 5 - name: Div7 value: 6 - name: Div8 value: 7 enum/PLLSRC: bit_size: 2 variants: - name: DISABLE description: No clock selected as PLL entry clock source value: 0 - name: HSI description: HSI16 selected as PLL entry clock source value: 2 - name: HSE description: HSE selected as PLL entry clock source value: 3 enum/PPRE: bit_size: 4 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK is divided by 2 value: 4 - name: Div4 description: HCLK is divided by 4 value: 5 - name: Div8 description: HCLK is divided by 8 value: 6 - name: Div16 description: HCLK is divided by 16 value: 7 enum/RNGDIV: bit_size: 2 variants: - name: Div1 description: RNG clock is not divided value: 0 - name: Div2 description: RNG clock is divided by 2 value: 1 - name: Div4 description: RNG clock is divided by 4 value: 2 - name: Div8 description: RNG clock is divided by 8 value: 3 enum/RNGSEL: bit_size: 2 variants: - name: DISABLE description: No clock used as RNG clock source value: 0 - name: HSI_DIV_8 description: HSI divided by 8 used as RNG clock source value: 1 - name: SYS description: SYSCLK used as RNG clock source value: 2 - name: PLL1_Q description: PLLQCLK used as RNG clock source value: 3 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE description: No clock used as RTC clock value: 0 - name: LSE description: LSE used as RTC clock value: 1 - name: LSI description: LSI used as RTC clock value: 2 - name: HSE_Div32 description: HSE divided by 32 used as RTC clock value: 3 enum/SW: bit_size: 3 variants: - name: HSI description: HSI selected as system clock value: 0 - name: HSE description: HSE selected as system clock value: 1 - name: PLL1_R description: PLLRCLK selected as system clock value: 2 - name: LSI description: LSI selected as system clock value: 3 - name: LSE description: LSE selected as system clock value: 4 enum/TIM15SEL: bit_size: 1 variants: - name: PCLK1_TIM description: TIMPCLK used as TIM15 clock source value: 0 - name: PLL1_Q description: PLLQCLK used as TIM15 clock source value: 1 enum/TIM1SEL: bit_size: 1 variants: - name: PCLK1_TIM description: TIMPCLK used as TIM1 clock source value: 0 - name: PLL1_Q description: PLLQCLK used as TIM1 clock source value: 1 enum/USART1SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as USART1 clock source value: 0 - name: SYS description: SYSCLK used as USART1 clock source value: 1 - name: HSI description: HSI16 used as USART1 clock source value: 2 - name: LSE description: LSE used as USART1 clock source value: 3 enum/USART2SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as USART2 clock source value: 0 - name: SYS description: SYSCLK used as USART2 clock source value: 1 - name: HSI description: HSI16 used as USART2 clock source value: 2 - name: LSE description: LSE used as USART2 clock source value: 3 enum/USART3SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK used as USART3 clock source value: 0 - name: SYS description: SYSCLK used as USART3 clock source value: 1 - name: HSI description: HSI16 used as USART3 clock source value: 2 - name: LSE description: LSE used as USART3 clock source value: 3 enum/USBSEL: bit_size: 2 variants: - name: HSI48 description: HSI48 used as USB clock source value: 0 - name: PLL1_Q description: PLLQCLK used as USB clock source value: 1 - name: HSE description: HSE used as USB clock source value: 2