PA0:
  CM4_EVENTOUT: 15
  COMP1_OUT: 12
  DEBUG_PWR-REGLP1S: 13
  I2C3_SMBA: 4
  I2S_CKIN: 5
  TIM2_CH1: 1
  TIM2_ETR: 14
  USART2_CTS: 7
  USART2_NSS: 7
PA1:
  CM4_EVENTOUT: 15
  DEBUG_PWR-REGLP2S: 13
  I2C1_SMBA: 4
  LPTIM3_OUT: 3
  LPUART1_RTS: 8
  SPI1_SCK: 5
  TIM2_CH2: 1
  USART2_DE: 7
  USART2_RTS: 7
PA10:
  CM4_EVENTOUT: 15
  DEBUG_RF-HSE32RDY: 13
  I2C1_SDA: 4
  I2S2_SD: 5
  RTC_REFIN: 0
  SPI2_MOSI: 5
  TIM17_BKIN: 14
  TIM1_CH3: 1
  USART1_RX: 7
PA11:
  CM4_EVENTOUT: 15
  DEBUG_RF-NRESET: 13
  I2C2_SDA: 4
  LPTIM3_ETR: 3
  SPI1_MISO: 5
  TIM1_BKIN2: 12
  TIM1_CH4: 1
  USART1_CTS: 7
  USART1_NSS: 7
PA12:
  CM4_EVENTOUT: 15
  I2C2_SCL: 4
  LPTIM3_IN1: 3
  RF_BUSY: 6
  SPI1_MOSI: 5
  TIM1_ETR: 1
  USART1_DE: 7
  USART1_RTS: 7
PA13:
  CM4_EVENTOUT: 15
  DEBUG_JTMS-SWDIO: 0
  I2C2_SMBA: 4
  IR_OUT: 8
PA14:
  CM4_EVENTOUT: 15
  DEBUG_JTCK-SWCLK: 0
  I2C1_SMBA: 4
  LPTIM1_OUT: 1
PA15:
  CM4_EVENTOUT: 15
  DEBUG_JTDI: 0
  I2C2_SDA: 4
  SPI1_NSS: 5
  TIM2_CH1: 1
  TIM2_ETR: 2
PA2:
  CM4_EVENTOUT: 15
  COMP2_OUT: 12
  DEBUG_PWR-LDORDY: 13
  LPUART1_TX: 8
  RCC_LSCO: 0
  TIM2_CH3: 1
  USART2_TX: 7
PA3:
  CM4_EVENTOUT: 15
  I2S2_MCK: 5
  LPUART1_RX: 8
  TIM2_CH4: 1
  USART2_RX: 7
PA4:
  CM4_EVENTOUT: 15
  DEBUG_SUBGHZSPI-NSSOUT: 13
  LPTIM1_OUT: 1
  LPTIM2_OUT: 14
  SPI1_NSS: 5
  USART2_CK: 7
PA5:
  CM4_EVENTOUT: 15
  DEBUG_SUBGHZSPI-SCKOUT: 13
  LPTIM2_ETR: 14
  SPI1_SCK: 5
  SPI2_MISO: 3
  TIM2_CH1: 1
  TIM2_ETR: 2
PA6:
  CM4_EVENTOUT: 15
  DEBUG_SUBGHZSPI-MISOOUT: 13
  I2C2_SMBA: 4
  LPUART1_CTS: 8
  SPI1_MISO: 5
  TIM16_CH1: 14
  TIM1_BKIN: 12
PA7:
  CM4_EVENTOUT: 15
  COMP2_OUT: 12
  DEBUG_SUBGHZSPI-MOSIOUT: 13
  I2C3_SCL: 4
  SPI1_MOSI: 5
  TIM17_CH1: 14
  TIM1_CH1N: 1
PA8:
  CM4_EVENTOUT: 15
  I2S2_CK: 5
  LPTIM2_OUT: 14
  RCC_MCO: 0
  SPI2_SCK: 5
  TIM1_CH1: 1
  USART1_CK: 7
PA9:
  CM4_EVENTOUT: 15
  I2C1_SCL: 4
  I2S2_CK: 5
  I2S2_WS: 3
  SPI2_NSS: 3
  SPI2_SCK: 5
  TIM1_CH2: 1
  USART1_TX: 7
PB0:
  CM4_EVENTOUT: 15
  COMP1_OUT: 12
PB1:
  CM4_EVENTOUT: 15
  LPTIM2_IN1: 14
  LPUART1_DE: 8
  LPUART1_RTS: 8
PB10:
  CM4_EVENTOUT: 15
  COMP1_OUT: 12
  I2C3_SCL: 4
  I2S2_CK: 5
  LPUART1_RX: 8
  SPI2_SCK: 5
  TIM2_CH3: 1
PB11:
  CM4_EVENTOUT: 15
  COMP2_OUT: 12
  I2C3_SDA: 4
  LPUART1_TX: 8
  TIM2_CH4: 1
PB12:
  CM4_EVENTOUT: 15
  I2C3_SMBA: 4
  I2S2_WS: 5
  LPUART1_DE: 8
  LPUART1_RTS: 8
  SPI2_NSS: 5
  TIM1_BKIN: 3
PB13:
  CM4_EVENTOUT: 15
  I2C3_SCL: 4
  I2S2_CK: 5
  LPUART1_CTS: 8
  SPI2_SCK: 5
  TIM1_CH1N: 1
PB14:
  CM4_EVENTOUT: 15
  I2C3_SDA: 4
  I2S2_MCK: 3
  SPI2_MISO: 5
  TIM1_CH2N: 1
PB15:
  CM4_EVENTOUT: 15
  I2C2_SCL: 4
  I2S2_SD: 5
  SPI2_MOSI: 5
  TIM1_CH3N: 1
PB2:
  CM4_EVENTOUT: 15
  DEBUG_RF-SMPSRDY: 13
  I2C3_SMBA: 4
  LPTIM1_OUT: 1
  SPI1_NSS: 5
PB3:
  CM4_EVENTOUT: 15
  DEBUG_JTDO-SWO: 0
  DEBUG_RF-DTB1: 13
  RF_IRQ0: 6
  SPI1_SCK: 5
  TIM2_CH2: 1
  USART1_DE: 7
  USART1_RTS: 7
PB4:
  CM4_EVENTOUT: 15
  DEBUG_RF-LDORDY: 13
  I2C3_SDA: 4
  SPI1_MISO: 5
  SYS_JTRST: 0
  TIM17_BKIN: 14
  USART1_CTS: 7
  USART1_NSS: 7
PB5:
  CM4_EVENTOUT: 15
  COMP2_OUT: 12
  I2C1_SMBA: 4
  LPTIM1_IN1: 1
  RF_IRQ1: 6
  SPI1_MOSI: 5
  TIM16_BKIN: 14
  USART1_CK: 7
PB6:
  CM4_EVENTOUT: 15
  I2C1_SCL: 4
  LPTIM1_ETR: 1
  TIM16_CH1N: 14
  USART1_TX: 7
PB7:
  CM4_EVENTOUT: 15
  I2C1_SDA: 4
  LPTIM1_IN2: 1
  TIM17_CH1N: 14
  TIM1_BKIN: 3
  USART1_RX: 7
PB8:
  CM4_EVENTOUT: 15
  I2C1_SCL: 4
  RF_IRQ2: 6
  TIM16_CH1: 14
  TIM1_CH2N: 1
PB9:
  CM4_EVENTOUT: 15
  I2C1_SDA: 4
  I2S2_WS: 5
  IR_OUT: 8
  SPI2_NSS: 5
  TIM17_CH1: 14
  TIM1_CH3N: 1
PC0:
  CM4_EVENTOUT: 15
  I2C3_SCL: 4
  LPTIM1_IN1: 1
  LPTIM2_IN1: 14
  LPUART1_RX: 8
PC1:
  CM4_EVENTOUT: 15
  I2C3_SDA: 4
  I2S2_SD: 3
  LPTIM1_OUT: 1
  LPUART1_TX: 8
  SPI2_MOSI: 3
PC13:
  CM4_EVENTOUT: 15
PC14:
  CM4_EVENTOUT: 15
PC15:
  CM4_EVENTOUT: 15
PC2:
  CM4_EVENTOUT: 15
  LPTIM1_IN2: 1
  SPI2_MISO: 5
PC3:
  CM4_EVENTOUT: 15
  I2S2_SD: 5
  LPTIM1_ETR: 1
  LPTIM2_ETR: 14
  SPI2_MOSI: 5
PC4:
  CM4_EVENTOUT: 15
PC5:
  CM4_EVENTOUT: 15
PC6:
  CM4_EVENTOUT: 15
  I2S2_MCK: 5
PH3:
  CM4_EVENTOUT: 15