PA0:
  LPTIM1_OUT: 5
  SPI2_SCK: 0
  TIM2_CH1: 2
  TIM2_ETR: 2
  USART2_CTS: 1
  USART2_NSS: 1
PA1:
  EVENTOUT: 7
  I2C1_SMBA: 6
  I2S1_CK: 0
  SPI1_SCK: 0
  TIM2_CH2: 2
  USART2_CK: 1
  USART2_DE: 1
  USART2_RTS: 1
PA10:
  EVENTOUT: 7
  I2C1_SDA: 6
  SPI2_MOSI: 0
  TIM17_BK: 5
  TIM1_CH3: 2
  USART1_RX: 1
PA11:
  I2C2_SCL: 6
  I2S1_MCK: 0
  SPI1_MISO: 0
  TIM1_BK2: 5
  TIM1_CH4: 2
  USART1_CTS: 1
  USART1_NSS: 1
PA12:
  I2C2_SDA: 6
  I2S1_SD: 0
  I2S_CKIN: 5
  SPI1_MOSI: 0
  TIM1_ETR: 2
  USART1_CK: 1
  USART1_DE: 1
  USART1_RTS: 1
PA13:
  EVENTOUT: 7
  IR_OUT: 1
  SYS_SWDIO: 0
PA14:
  EVENTOUT: 7
  SYS_SWCLK: 0
  USART2_TX: 1
PA15:
  EVENTOUT: 7
  I2S1_WS: 0
  SPI1_NSS: 0
  TIM2_CH1: 2
  TIM2_ETR: 2
  USART2_RX: 1
PA2:
  I2S1_SD: 0
  LPUART1_TX: 6
  SPI1_MOSI: 0
  TIM2_CH3: 2
  USART2_TX: 1
PA3:
  EVENTOUT: 7
  LPUART1_RX: 6
  SPI2_MISO: 0
  TIM2_CH4: 2
  USART2_RX: 1
PA4:
  EVENTOUT: 7
  I2S1_WS: 0
  LPTIM2_OUT: 5
  SPI1_NSS: 0
  SPI2_MOSI: 1
  TIM14_CH1: 4
PA5:
  EVENTOUT: 7
  I2S1_CK: 0
  LPTIM2_ETR: 5
  SPI1_SCK: 0
  TIM2_CH1: 2
  TIM2_ETR: 2
PA6:
  I2S1_MCK: 0
  LPUART1_CTS: 6
  SPI1_MISO: 0
  TIM16_CH1: 5
  TIM1_BK: 2
  TIM3_CH1: 1
PA7:
  I2S1_SD: 0
  SPI1_MOSI: 0
  TIM14_CH1: 4
  TIM17_CH1: 5
  TIM1_CH1N: 2
  TIM3_CH2: 1
PA8:
  EVENTOUT: 7
  LPTIM2_OUT: 5
  RCC_MCO: 0
  SPI2_NSS: 1
  TIM1_CH1: 2
PA9:
  EVENTOUT: 7
  I2C1_SCL: 6
  RCC_MCO: 0
  SPI2_MISO: 4
  TIM1_CH2: 2
  USART1_TX: 1
PB0:
  I2S1_WS: 0
  LPTIM1_OUT: 5
  SPI1_NSS: 0
  TIM1_CH2N: 2
  TIM3_CH3: 1
PB1:
  EVENTOUT: 7
  LPTIM2_IN1: 5
  LPUART1_DE: 6
  LPUART1_RTS: 6
  TIM14_CH1: 0
  TIM1_CH3N: 2
  TIM3_CH4: 1
PB10:
  I2C2_SCL: 6
  LPUART1_RX: 1
  SPI2_SCK: 5
  TIM2_CH3: 2
PB11:
  I2C2_SDA: 6
  LPUART1_TX: 1
  SPI2_MOSI: 0
  TIM2_CH4: 2
PB12:
  EVENTOUT: 7
  LPUART1_DE: 1
  LPUART1_RTS: 1
  SPI2_NSS: 0
  TIM1_BK: 2
PB13:
  EVENTOUT: 7
  I2C2_SCL: 6
  LPUART1_CTS: 1
  SPI2_SCK: 0
  TIM1_CH1N: 2
PB14:
  EVENTOUT: 7
  I2C2_SDA: 6
  SPI2_MISO: 0
  TIM1_CH2N: 2
PB15:
  EVENTOUT: 7
  SPI2_MOSI: 0
  TIM1_CH3N: 2
PB2:
  EVENTOUT: 7
  LPTIM1_OUT: 5
  SPI2_MISO: 1
PB3:
  EVENTOUT: 7
  I2S1_CK: 0
  SPI1_SCK: 0
  TIM1_CH2: 1
  TIM2_CH2: 2
  USART1_CK: 4
  USART1_DE: 4
  USART1_RTS: 4
PB4:
  EVENTOUT: 7
  I2S1_MCK: 0
  SPI1_MISO: 0
  TIM17_BK: 5
  TIM3_CH1: 1
  USART1_CTS: 4
  USART1_NSS: 4
PB5:
  I2C1_SMBA: 6
  I2S1_SD: 0
  LPTIM1_IN1: 5
  SPI1_MOSI: 0
  TIM16_BK: 2
  TIM3_CH2: 1
PB6:
  EVENTOUT: 7
  I2C1_SCL: 6
  LPTIM1_ETR: 5
  SPI2_MISO: 4
  TIM16_CH1N: 2
  TIM1_CH3: 1
  USART1_TX: 0
PB7:
  EVENTOUT: 7
  I2C1_SDA: 6
  LPTIM1_IN2: 5
  SPI2_MOSI: 1
  TIM17_CH1N: 2
  USART1_RX: 0
PB8:
  EVENTOUT: 7
  I2C1_SCL: 6
  SPI2_SCK: 1
  TIM16_CH1: 2
PB9:
  EVENTOUT: 7
  I2C1_SDA: 6
  IR_OUT: 0
  SPI2_NSS: 5
  TIM17_CH1: 2
PC13:
  TIM1_BK: 2
PC14:
  TIM1_BK2: 2
PC15:
  RCC_OSC32_EN: 0
  RCC_OSC_EN: 1
PC6:
  TIM2_CH3: 2
  TIM3_CH1: 1
PC7:
  TIM2_CH4: 2
  TIM3_CH2: 1
PD0:
  EVENTOUT: 0
  SPI2_NSS: 1
  TIM16_CH1: 2
PD1:
  EVENTOUT: 0
  SPI2_SCK: 1
  TIM17_CH1: 2
PD2:
  TIM1_CH1N: 2
  TIM3_ETR: 1
PD3:
  SPI2_MISO: 1
  TIM1_CH2N: 2
  USART2_CTS: 0
  USART2_NSS: 0
PF0:
  TIM14_CH1: 2
PF1:
  RCC_OSC_EN: 0
PF2:
  RCC_MCO: 0
PI8: {}