block/EXTI:
  description: Extended interrupt and event controller
  items:
  - name: RTSR
    description: rising trigger selection register
    array:
      len: 2
      stride: 32
    byte_offset: 0
    fieldset: LINES
  - name: FTSR
    description: falling trigger selection register
    array:
      len: 2
      stride: 32
    byte_offset: 4
    fieldset: LINES
  - name: SWIER
    description: software interrupt event register
    array:
      len: 2
      stride: 32
    byte_offset: 8
    fieldset: LINES
  - name: RPR
    description: rising edge pending register
    array:
      len: 2
      stride: 32
    byte_offset: 12
    fieldset: LINES
  - name: FPR
    description: falling edge pending register
    array:
      len: 2
      stride: 32
    byte_offset: 16
    fieldset: LINES
  - name: SECCFGR
    description: security configuration register
    array:
      len: 2
      stride: 32
    byte_offset: 20
    fieldset: SEC
  - name: PRIVCFGR
    description: privilege configuration register
    array:
      len: 2
      stride: 32
    byte_offset: 24
    fieldset: PRIV
  - name: EXTICR
    description: external interrupt selection register
    array:
      len: 4
      stride: 4
    byte_offset: 96
    fieldset: EXTI
  - name: LOCKR
    description: lock register
    byte_offset: 112
    fieldset: LOCKR
  - name: IMR
    description: CPU wakeup with interrupt mask register
    array:
      len: 2
      stride: 16
    byte_offset: 128
    fieldset: LINES
  - name: EMR
    description: CPU wakeup with event mask register
    array:
      len: 2
      stride: 16
    byte_offset: 132
    fieldset: LINES
fieldset/EXTI:
  description: EXTI external interrupt selection register
  fields:
  - name: EXTI
    description: "EXTI12 GPIO port selection\r These bits are written by software to select the source input for EXTI12 external interrupt.\r When EXTI_PRIVCFGR.PRIV12 is disabled, EXTI12 can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIV12 is enabled, EXTI12 can only be accessed with privileged access. Unprivileged write to this bit is discarded.\r Others: reserved"
    bit_offset: 0
    bit_size: 8
    array:
      len: 4
      stride: 8
fieldset/LINES:
  description: EXTI lines register, 1 bit per line
  fields:
  - name: LINE
    description: EXTI line
    bit_offset: 0
    bit_size: 1
    array:
      len: 32
      stride: 1
fieldset/LOCKR:
  description: lock register
  fields:
  - name: LOCK
    description: "Global security and privilege configuration registers (EXTI_SECCFGR and EXTI_PRIVCFGR) lock \r This bit is written once after reset."
    bit_offset: 0
    bit_size: 1
fieldset/PRIV:
  description: privilege configuration register
  fields:
  - name: PRIV
    description: "Security enable on event input x\r When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-secure access.\r When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access. Non-secure write to this PRIVx is discarded."
    bit_offset: 0
    bit_size: 1
    array:
      len: 32
      stride: 1
fieldset/SEC:
  description: security configuration register
  fields:
  - name: SEC
    description: "Security enable on event input x\r When EXTI_PRIVCFGR.PRIVx is disabled, SECx can be accessed with privileged and unprivileged access.\r When EXTI_PRIVCFGR.PRIVx is enabled, SECx can only be written with privileged access. Unprivileged write to this SECx is discarded."
    bit_offset: 0
    bit_size: 1
    array:
      len: 32
      stride: 1