block/DBGMCU:
  description: Debug support
  items:
  - name: IDCODE
    description: MCU Device ID Code Register
    byte_offset: 0
    access: Read
    fieldset: IDCODE
  - name: CR
    description: Debug MCU Configuration Register
    byte_offset: 4
    fieldset: CR
  - name: APB1FZR1
    description: APB1 Low Freeze Register CPU1
    byte_offset: 60
    fieldset: APB1FZR1
  - name: C2AP_B1FZR1
    description: APB1 Low Freeze Register CPU2
    byte_offset: 64
    fieldset: C2AP_B1FZR1
  - name: APB1FZR2
    description: APB1 High Freeze Register CPU1
    byte_offset: 68
    fieldset: APB1FZR2
  - name: C2APB1FZR2
    description: APB1 High Freeze Register CPU2
    byte_offset: 72
    fieldset: C2APB1FZR2
  - name: C2APB2FZR
    description: APB2 Freeze Register CPU2
    byte_offset: 72
    fieldset: C2APB2FZR
  - name: APB2FZR
    description: APB2 Freeze Register CPU1
    byte_offset: 76
    fieldset: APB2FZR
fieldset/APB1FZR1:
  description: APB1 Low Freeze Register CPU1
  fields:
  - name: TIM2
    description: Debug Timer 2 stopped when Core is halted
    bit_offset: 0
    bit_size: 1
  - name: RTC
    description: RTC counter stopped when core is halted
    bit_offset: 10
    bit_size: 1
  - name: WWDG
    description: WWDG counter stopped when core is halted
    bit_offset: 11
    bit_size: 1
  - name: IWDG
    description: IWDG counter stopped when core is halted
    bit_offset: 12
    bit_size: 1
  - name: I2C1
    description: Debug I2C1 SMBUS timeout stopped when Core is halted
    bit_offset: 21
    bit_size: 1
  - name: I2C3
    description: Debug I2C3 SMBUS timeout stopped when core is halted
    bit_offset: 23
    bit_size: 1
  - name: LPTIM1
    description: Debug LPTIM1 stopped when Core is halted
    bit_offset: 31
    bit_size: 1
fieldset/APB1FZR2:
  description: APB1 High Freeze Register CPU1
  fields:
  - name: LPTIM2
    description: LPTIM2 counter stopped when core is halted
    bit_offset: 5
    bit_size: 1
fieldset/APB2FZR:
  description: APB2 Freeze Register CPU1
  fields:
  - name: TIM1
    description: TIM1 counter stopped when core is halted
    bit_offset: 11
    bit_size: 1
  - name: TIM16
    description: TIM16 counter stopped when core is halted
    bit_offset: 17
    bit_size: 1
  - name: TIM17
    description: TIM17 counter stopped when core is halted
    bit_offset: 18
    bit_size: 1
fieldset/C2APB1FZR2:
  description: APB1 High Freeze Register CPU2
  fields:
  - name: LPTIM2
    description: LPTIM2 counter stopped when core is halted
    bit_offset: 5
    bit_size: 1
fieldset/C2APB2FZR:
  description: APB2 Freeze Register CPU2
  fields:
  - name: TIM1
    description: TIM1 counter stopped when core is halted
    bit_offset: 11
    bit_size: 1
  - name: TIM16
    description: TIM16 counter stopped when core is halted
    bit_offset: 17
    bit_size: 1
  - name: TIM17
    description: TIM17 counter stopped when core is halted
    bit_offset: 18
    bit_size: 1
fieldset/C2AP_B1FZR1:
  description: APB1 Low Freeze Register CPU2
  fields:
  - name: LPTIM2
    description: LPTIM2 counter stopped when core is halted
    bit_offset: 0
    bit_size: 1
  - name: RTC
    description: RTC counter stopped when core is halted
    bit_offset: 10
    bit_size: 1
  - name: IWDG
    description: IWDG stopped when core is halted
    bit_offset: 12
    bit_size: 1
  - name: I2C1
    description: I2C1 SMBUS timeout stopped when core is halted
    bit_offset: 21
    bit_size: 1
  - name: I2C3
    description: I2C3 SMBUS timeout stopped when core is halted
    bit_offset: 23
    bit_size: 1
  - name: LPTIM1
    description: LPTIM1 counter stopped when core is halted
    bit_offset: 31
    bit_size: 1
fieldset/CR:
  description: Debug MCU Configuration Register
  fields:
  - name: DBG_SLEEP
    description: Debug Sleep Mode
    bit_offset: 0
    bit_size: 1
  - name: DBG_STOP
    description: Debug Stop Mode
    bit_offset: 1
    bit_size: 1
  - name: DBG_STANDBY
    description: Debug Standby Mode
    bit_offset: 2
    bit_size: 1
  - name: TRACE_IOEN
    description: Trace port and clock enable
    bit_offset: 5
    bit_size: 1
  - name: TRGOEN
    description: External trigger output enable
    bit_offset: 28
    bit_size: 1
fieldset/IDCODE:
  description: MCU Device ID Code Register
  fields:
  - name: DEV_ID
    description: Device Identifier
    bit_offset: 0
    bit_size: 12
  - name: REV_ID
    description: Revision Identifier
    bit_offset: 16
    bit_size: 16