PA0:
  CM4_EVENTOUT: 15
  COMP1_OUT: 12
  TIM2_CH1: 1
  TIM2_ETR: 14
PA1:
  CM4_EVENTOUT: 15
  I2C1_SMBA: 4
  SPI1_SCK: 5
  TIM2_CH2: 1
PA10:
  CM4_EVENTOUT: 15
  I2C1_SDA: 4
  TIM1_CH3: 1
  TSC_G7_IO2: 9
  USART1_RX: 7
PA11:
  CM4_EVENTOUT: 15
  SPI1_MISO: 5
  TIM1_BKIN2: 2
  TIM1_CH4: 1
  USART1_CTS: 7
  USART1_NSS: 7
PA12:
  CM4_EVENTOUT: 15
  LPUART1_RX: 8
  SPI1_MOSI: 5
  TIM1_ETR: 1
  USART1_DE: 7
  USART1_RTS: 7
PA13:
  CM4_EVENTOUT: 15
  SPI1_MOSI: 5
  SYS_JTMS-SWDIO: 0
  TSC_G7_IO1: 9
PA14:
  CM4_EVENTOUT: 15
  I2C1_SMBA: 4
  LPTIM1_OUT: 1
  SPI1_NSS: 5
  SYS_JTCK-SWCLK: 0
PA15:
  CM4_EVENTOUT: 15
  RCC_MCO: 6
  SPI1_NSS: 5
  SYS_JTDI: 0
  TIM2_CH1: 1
  TIM2_ETR: 2
  TSC_G3_IO1: 9
PA2:
  CM4_EVENTOUT: 15
  LPUART1_TX: 8
  RCC_LSCO: 0
  TIM2_CH3: 1
PA3:
  CM4_EVENTOUT: 15
  LPUART1_RX: 8
  TIM2_CH4: 1
PA4:
  CM4_EVENTOUT: 15
  LPTIM2_OUT: 14
  SPI1_NSS: 5
PA5:
  CM4_EVENTOUT: 15
  LPTIM2_ETR: 14
  SPI1_MOSI: 4
  SPI1_SCK: 5
  TIM2_CH1: 1
  TIM2_ETR: 2
PA6:
  CM4_EVENTOUT: 15
  LPUART1_CTS: 8
  SPI1_MISO: 5
  TIM1_BKIN: 1
PA7:
  CM4_EVENTOUT: 15
  SPI1_MOSI: 5
  TIM1_CH1N: 1
PA8:
  CM4_EVENTOUT: 15
  LPTIM2_OUT: 14
  RCC_MCO: 0
  TIM1_CH1: 1
  USART1_CK: 7
PA9:
  CM4_EVENTOUT: 15
  I2C1_SCL: 4
  TIM1_CH2: 1
  USART1_TX: 7
PB0:
  CM4_EVENTOUT: 15
  COMP1_OUT: 12
  RF_TX_MOD_EXT_PA: 6
PB1:
  CM4_EVENTOUT: 15
  LPTIM2_IN1: 14
  LPUART1_DE: 8
  LPUART1_RTS: 8
PB10:
  CM4_EVENTOUT: 15
  TSC_G3_IO2: 9
PB12:
  CM4_EVENTOUT: 15
  TIM2_CH2: 1
  TSC_G1_IO1: 9
PB13:
  CM4_EVENTOUT: 15
  TIM2_CH3: 1
  TSC_G1_IO2: 9
PB14:
  CM4_EVENTOUT: 15
  TIM1_CH1: 1
PB15:
  CM4_EVENTOUT: 15
  TIM2_CH1: 1
PB2:
  CM4_EVENTOUT: 15
  LPTIM1_OUT: 1
  RTC_OUT: 0
  SPI1_NSS: 5
PB3:
  CM4_EVENTOUT: 15
  SPI1_SCK: 5
  SYS_JTDO-SWO: 0
  TIM2_CH2: 1
  USART1_DE: 7
  USART1_RTS: 7
PB4:
  CM4_EVENTOUT: 15
  SPI1_MISO: 5
  SYS_JTRST: 0
  TSC_G2_IO1: 9
  USART1_CTS: 7
  USART1_NSS: 7
PB5:
  CM4_EVENTOUT: 15
  I2C1_SMBA: 4
  LPTIM1_IN1: 1
  LPUART1_TX: 8
  SPI1_MOSI: 5
  TSC_G2_IO2: 9
  USART1_CK: 7
PB6:
  CM4_EVENTOUT: 15
  I2C1_SCL: 4
  LPTIM1_ETR: 1
  RCC_MCO: 0
  SPI1_NSS: 5
  TSC_G2_IO3: 9
  USART1_TX: 7
PB7:
  CM4_EVENTOUT: 15
  I2C1_SDA: 4
  LPTIM1_IN2: 1
  TIM1_BKIN: 3
  TIM1_CH3: 12
  TSC_G2_IO4: 9
  USART1_RX: 7
PB8:
  CM4_EVENTOUT: 15
  I2C1_SCL: 4
  TIM1_CH2N: 1
  TSC_G7_IO3: 9
PB9:
  CM4_EVENTOUT: 15
  I2C1_SDA: 4
  TIM1_CH3N: 1
  TSC_G7_IO4: 9
PC1:
  CM4_EVENTOUT: 15
  TSC_G3_IO3: 9
PC13: {}
PC14:
  CM4_EVENTOUT: 15
PC15:
  CM4_EVENTOUT: 15
PE4:
  CM4_EVENTOUT: 15
PH3:
  CM4_EVENTOUT: 15
  RCC_LSCO: 0
PI8: {}