block/RCC: description: RCC address block description items: - name: CR description: RCC clock control register byte_offset: 0 fieldset: CR - name: ICSCR description: RCC internal clock source calibration register byte_offset: 4 fieldset: ICSCR - name: CFGR description: RCC clock configuration register byte_offset: 8 fieldset: CFGR - name: CIER description: RCC clock interrupt enable register byte_offset: 24 fieldset: CIER - name: CIFR description: RCC clock interrupt flag register byte_offset: 28 fieldset: CIFR - name: CICR description: RCC clock interrupt clear register byte_offset: 32 fieldset: CICR - name: GPIORSTR description: RCC I/O port reset register byte_offset: 36 fieldset: GPIORSTR - name: AHBRSTR description: RCC AHB peripheral reset register byte_offset: 40 fieldset: AHBRSTR - name: APBRSTR1 description: RCC APB peripheral reset register 1 byte_offset: 44 fieldset: APBRSTR1 - name: APBRSTR2 description: RCC APB peripheral reset register 2 byte_offset: 48 fieldset: APBRSTR2 - name: GPIOENR description: RCC I/O port clock enable register byte_offset: 52 fieldset: GPIOENR - name: AHBENR description: RCC AHB peripheral clock enable register byte_offset: 56 fieldset: AHBENR - name: APBENR1 description: RCC APB peripheral clock enable register 1 byte_offset: 60 fieldset: APBENR1 - name: APBENR2 description: RCC APB peripheral clock enable register 2 byte_offset: 64 fieldset: APBENR2 - name: GPIOSMENR description: RCC I/O port in Sleep mode clock enable register byte_offset: 68 fieldset: GPIOSMENR - name: AHBSMENR description: RCC AHB peripheral clock enable in Sleep/Stop mode register byte_offset: 72 fieldset: AHBSMENR - name: APBSMENR1 description: RCC APB peripheral clock enable in Sleep/Stop mode register 1 byte_offset: 76 fieldset: APBSMENR1 - name: APBSMENR2 description: RCC APB peripheral clock enable in Sleep/Stop mode register 2 byte_offset: 80 fieldset: APBSMENR2 - name: CCIPR description: RCC peripherals independent clock configuration register byte_offset: 84 fieldset: CCIPR - name: CSR1 description: RCC control/status register 1 byte_offset: 92 fieldset: CSR1 - name: CSR2 description: RCC control/status register 2 byte_offset: 96 fieldset: CSR2 fieldset/AHBENR: description: RCC AHB peripheral clock enable register fields: - name: DMA1EN description: "DMA1 and DMAMUX clock enable\r Set and cleared by software.\r DMAMUX is enabled as long as at least one DMA peripheral is enabled." bit_offset: 0 bit_size: 1 - name: FLASHEN description: "Flash memory interface clock enable\r Set and cleared by software.\r This bit can only be cleared when the Flash memory is in power down mode." bit_offset: 8 bit_size: 1 - name: CRCEN description: "CRC clock enable\r Set and cleared by software." bit_offset: 12 bit_size: 1 fieldset/AHBRSTR: description: RCC AHB peripheral reset register fields: - name: DMA1RST description: "DMA1 and DMAMUX reset\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: FLASHRST description: "Flash memory interface reset\r Set and cleared by software.\r This bit can only be set when the Flash memory is in power down mode." bit_offset: 8 bit_size: 1 - name: CRCRST description: "CRC reset\r Set and cleared by software." bit_offset: 12 bit_size: 1 fieldset/AHBSMENR: description: RCC AHB peripheral clock enable in Sleep/Stop mode register fields: - name: DMA1SMEN description: "DMA1 and DMAMUX clock enable during Sleep mode\r Set and cleared by software.\r Clock to DMAMUX during Sleep mode is enabled as long as the clock in Sleep mode is enabled to at least one DMA peripheral." bit_offset: 0 bit_size: 1 - name: FLASHSMEN description: "Flash memory interface clock enable during Sleep mode\r Set and cleared by software.\r This bit can be activated only when the Flash memory is in power down mode." bit_offset: 8 bit_size: 1 - name: SRAMSMEN description: "SRAM clock enable during Sleep mode\r Set and cleared by software." bit_offset: 9 bit_size: 1 - name: CRCSMEN description: "CRC clock enable during Sleep mode\r Set and cleared by software." bit_offset: 12 bit_size: 1 fieldset/APBENR1: description: RCC APB peripheral clock enable register 1 fields: - name: TIM3EN description: "TIM3 timer clock enable\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: RTCAPBEN description: "RTC APB clock enable\r Set and cleared by software." bit_offset: 10 bit_size: 1 - name: WWDGEN description: "WWDG clock enable\r Set by software to enable the window watchdog clock. Cleared by hardware system reset\r This bit can also be set by hardware if the WWDG_SW option bit is 0." bit_offset: 11 bit_size: 1 - name: USART2EN description: "USART2 clock enable\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: I2C1EN description: "I2C1 clock enable\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: DBGEN description: "Debug support clock enable\r Set and cleared by software." bit_offset: 27 bit_size: 1 - name: PWREN description: "Power interface clock enable\r Set and cleared by software." bit_offset: 28 bit_size: 1 fieldset/APBENR2: description: RCC APB peripheral clock enable register 2 fields: - name: SYSCFGEN description: "SYSCFG clock enable\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: TIM1EN description: "TIM1 timer clock enable\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: SPI1EN description: "SPI1 clock enable\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: USART1EN description: "USART1 clock enable\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: TIM14EN description: "TIM14 timer clock enable\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: TIM16EN description: "TIM16 timer clock enable\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: TIM17EN description: "TIM16 timer clock enable\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: ADCEN description: "ADC clock enable\r Set and cleared by software." bit_offset: 20 bit_size: 1 fieldset/APBRSTR1: description: RCC APB peripheral reset register 1 fields: - name: TIM3RST description: "TIM3 timer reset\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: USART2RST description: "USART2 reset\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: I2C1RST description: "I2C1 reset\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: DBGRST description: "Debug support reset\r Set and cleared by software." bit_offset: 27 bit_size: 1 - name: PWRRST description: "Power interface reset\r Set and cleared by software." bit_offset: 28 bit_size: 1 fieldset/APBRSTR2: description: RCC APB peripheral reset register 2 fields: - name: SYSCFGRST description: "SYSCFG reset\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: TIM1RST description: "TIM1 timer reset\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: SPI1RST description: "SPI1 reset\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: USART1RST description: "USART1 reset\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: TIM14RST description: "TIM14 timer reset\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: TIM16RST description: "TIM16 timer reset\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: TIM17RST description: "TIM16 timer reset\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: ADCRST description: "ADC reset\r Set and cleared by software." bit_offset: 20 bit_size: 1 fieldset/APBSMENR1: description: RCC APB peripheral clock enable in Sleep/Stop mode register 1 fields: - name: TIM3SMEN description: "TIM3 timer clock enable during Sleep mode\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: RTCAPBSMEN description: "RTC APB clock enable during Sleep mode\r Set and cleared by software." bit_offset: 10 bit_size: 1 - name: WWDGSMEN description: "WWDG clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: USART2SMEN description: "USART2 clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: I2C1SMEN description: "I2C1 clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 21 bit_size: 1 - name: DBGSMEN description: "Debug support clock enable during Sleep mode\r Set and cleared by software." bit_offset: 27 bit_size: 1 - name: PWRSMEN description: "Power interface clock enable during Sleep mode\r Set and cleared by software." bit_offset: 28 bit_size: 1 fieldset/APBSMENR2: description: RCC APB peripheral clock enable in Sleep/Stop mode register 2 fields: - name: SYSCFGSMEN description: "SYSCFG clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: TIM1SMEN description: "TIM1 timer clock enable during Sleep mode\r Set and cleared by software." bit_offset: 11 bit_size: 1 - name: SPI1SMEN description: "SPI1 clock enable during Sleep mode\r Set and cleared by software." bit_offset: 12 bit_size: 1 - name: USART1SMEN description: "USART1 clock enable during Sleep and Stop modes\r Set and cleared by software." bit_offset: 14 bit_size: 1 - name: TIM14SMEN description: "TIM14 timer clock enable during Sleep mode\r Set and cleared by software." bit_offset: 15 bit_size: 1 - name: TIM16SMEN description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software." bit_offset: 17 bit_size: 1 - name: TIM17SMEN description: "TIM16 timer clock enable during Sleep mode\r Set and cleared by software." bit_offset: 18 bit_size: 1 - name: ADCSMEN description: "ADC clock enable during Sleep mode\r Set and cleared by software." bit_offset: 20 bit_size: 1 fieldset/CCIPR: description: RCC peripherals independent clock configuration register fields: - name: USART1SEL description: "USART1 clock source selection\r This bitfield is controlled by software to select USART1 clock source as follows:" bit_offset: 0 bit_size: 2 enum: USART1SEL - name: I2C1SEL description: "I2C1 clock source selection\r This bitfield is controlled by software to select I2C1 clock source as follows:" bit_offset: 12 bit_size: 2 enum: I2C1SEL - name: I2S1SEL description: "I2S1 clock source selection\r This bitfield is controlled by software to select I2S1 clock source as follows:" bit_offset: 14 bit_size: 2 enum: I2S1SEL - name: ADCSEL description: "ADCs clock source selection\r This bitfield is controlled by software to select the clock source for ADC:" bit_offset: 30 bit_size: 2 enum: ADCSEL fieldset/CFGR: description: RCC clock configuration register fields: - name: SW description: "System clock switch\r This bitfield is controlled by software and hardware. The bitfield selects the clock for SYSCLK as follows:\r Others: Reserved\r The setting is forced by hardware to 000 (HSISYS selected) when the MCU exits Stop, or Standby, or Shutdown mode, or when the setting is 001 (HSE selected) and HSE oscillator failure is detected." bit_offset: 0 bit_size: 3 enum: SW - name: SWS description: "System clock switch status\r This bitfield is controlled by hardware to indicate the clock source used as system clock:\r Others: Reserved" bit_offset: 3 bit_size: 3 enum: SW - name: HPRE description: "AHB prescaler\r This bitfield is controlled by software. To produce HCLK clock, it sets the division factor of SYSCLK clock as follows:\r 0xxx: 1" bit_offset: 8 bit_size: 4 enum: HPRE - name: PPRE description: "APB prescaler\r This bitfield is controlled by software. To produce PCLK clock, it sets the division factor of HCLK clock as follows:\r 0xx: 1" bit_offset: 12 bit_size: 3 enum: PPRE - name: MCO2SEL description: "Microcontroller clock output 2 clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO2 output as follows:\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO2 clock source switching." bit_offset: 16 bit_size: 4 enum: MCOSEL - name: MCO2PRE description: "Microcontroller clock output 2 prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO2 output as follows:\r ...\r It is highly recommended to set this field before the MCO2 output is enabled." bit_offset: 20 bit_size: 4 enum: MCOPRE - name: MCO1SEL description: "Microcontroller clock output clock selector\r This bitfield is controlled by software. It sets the clock selector for MCO output as follows:\r Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Any other value means no clock on MCO." bit_offset: 24 bit_size: 4 enum: MCOSEL - name: MCO1PRE description: "Microcontroller clock output prescaler\r This bitfield is controlled by software. It sets the division factor of the clock sent to the MCO output as follows:\r ...\r It is highly recommended to set this field before the MCO output is enabled." bit_offset: 28 bit_size: 4 enum: MCOPRE fieldset/CICR: description: RCC clock interrupt clear register fields: - name: LSIRDYC description: "LSI ready interrupt clear\r This bit is set by software to clear the LSIRDYF flag." bit_offset: 0 bit_size: 1 - name: LSERDYC description: "LSE ready interrupt clear\r This bit is set by software to clear the LSERDYF flag." bit_offset: 1 bit_size: 1 - name: HSIRDYC description: "HSI ready interrupt clear\r This bit is set software to clear the HSIRDYF flag." bit_offset: 3 bit_size: 1 - name: HSERDYC description: "HSE ready interrupt clear\r This bit is set by software to clear the HSERDYF flag." bit_offset: 4 bit_size: 1 - name: CSSC description: "Clock security system interrupt clear\r This bit is set by software to clear the HSECSSF flag." bit_offset: 8 bit_size: 1 - name: LSECSSC description: "LSE Clock security system interrupt clear\r This bit is set by software to clear the LSECSSF flag." bit_offset: 9 bit_size: 1 fieldset/CIER: description: RCC clock interrupt enable register fields: - name: LSIRDYIE description: "LSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization:" bit_offset: 0 bit_size: 1 - name: LSERDYIE description: "LSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization:" bit_offset: 1 bit_size: 1 - name: HSIRDYIE description: "HSI ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSI oscillator stabilization:" bit_offset: 3 bit_size: 1 - name: HSERDYIE description: "HSE ready interrupt enable\r Set and cleared by software to enable/disable interrupt caused by the HSE oscillator stabilization:" bit_offset: 4 bit_size: 1 fieldset/CIFR: description: RCC clock interrupt flag register fields: - name: LSIRDYF description: "LSI ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.\r Cleared by software setting the LSIRDYC bit." bit_offset: 0 bit_size: 1 - name: LSERDYF description: "LSE ready interrupt flag\r This flag indicates a pending interrupt upon LSE clock getting ready.\r Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.\r Cleared by software setting the LSERDYC bit." bit_offset: 1 bit_size: 1 - name: HSIRDYF description: "HSI ready interrupt flag\r This flag indicates a pending interrupt upon HSI clock getting ready.\r Set by hardware when the HSI clock becomes stable and HSIRDYIE is set in response to setting the HSION (refer to ). When HSION is not set but the HSI oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.\r Cleared by software setting the HSIRDYC bit." bit_offset: 3 bit_size: 1 - name: HSERDYF description: "HSE ready interrupt flag\r This flag indicates a pending interrupt upon HSE clock getting ready.\r Set by hardware when the HSE clock becomes stable and HSERDYIE is set.\r Cleared by software setting the HSERDYC bit." bit_offset: 4 bit_size: 1 - name: CSSF description: "HSE clock security system interrupt flag\r This flag indicates a pending interrupt upon HSE clock failure.\r Set by hardware when a failure is detected in the HSE oscillator.\r Cleared by software setting the CSSC bit." bit_offset: 8 bit_size: 1 - name: LSECSSF description: "LSE clock security system interrupt flag\r This flag indicates a pending interrupt upon LSE clock failure.\r Set by hardware when a failure is detected in the LSE oscillator.\r Cleared by software by setting the LSECSSC bit." bit_offset: 9 bit_size: 1 fieldset/CR: description: RCC clock control register fields: - name: SYSDIV description: "System clock division factor\r This bitfield controlled by software sets the division factor of the system clock divider to produce SYSCLK clock:" bit_offset: 2 bit_size: 3 enum: SYSDIV - name: HSIKERDIV description: "HSI kernel clock division factor\r This bitfield controlled by software sets the division factor of the kernel clock divider to produce HSIKER clock:" bit_offset: 5 bit_size: 3 enum: HSIKERDIV - name: HSION description: "HSI clock enable\r Set and cleared by software and hardware, with hardware taking priority.\r Kept low by hardware as long as the device is in a low-power mode.\r Kept high by hardware as long as the system is clocked with a clock derived from HSI. This includes the exit from low-power modes and the system clock fall-back to HSI upon failing HSE oscillator clock selected as system clock source." bit_offset: 8 bit_size: 1 - name: HSIKERON description: "HSI always-enable for peripheral kernels.\r Set and cleared by software.\r Setting the bit activates the HSI oscillator in Run and Stop modes, regardless of the HSION bit state. The HSI clock can only feed USART1, USART2, and I2C1 peripherals configured with HSI as kernel clock.\r Note: Keeping the HSI active in Stop mode allows speeding up the serial interface communication as the HSI clock is ready immediately upon exiting Stop mode." bit_offset: 9 bit_size: 1 - name: HSIRDY description: "HSI clock ready flag\r Set by hardware when the HSI oscillator is enabled through HSION and ready to use (stable).\r Note: Upon clearing HSION, HSIRDY goes low after six HSI clock cycles." bit_offset: 10 bit_size: 1 - name: HSIDIV description: "HSI clock division factor\r This bitfield controlled by software sets the division factor of the HSI clock divider to produce HSISYS clock:" bit_offset: 11 bit_size: 3 enum: HSIDIV - name: HSEON description: "HSE clock enable\r Set and cleared by software.\r Cleared by hardware to stop the HSE oscillator when entering Stop, or Standby, or Shutdown mode. This bit cannot be cleared if the HSE oscillator is used directly or indirectly as the system clock." bit_offset: 16 bit_size: 1 - name: HSERDY description: "HSE clock ready flag\r Set by hardware to indicate that the HSE oscillator is stable and ready for use.\r Note: Upon clearing HSEON, HSERDY goes low after six HSE clock cycles." bit_offset: 17 bit_size: 1 - name: HSEBYP description: "HSE crystal oscillator bypass\r Set and cleared by software.\r When the bit is set, the internal HSE oscillator is bypassed for use of an external clock. The external clock must then be enabled with the HSEON bit set. Write access to the bit is only effective when the HSE oscillator is disabled." bit_offset: 18 bit_size: 1 - name: CSSON description: "Clock security system enable\r Set by software to enable the clock security system. When the bit is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected. The bit is cleared by hardware upon reset." bit_offset: 19 bit_size: 1 fieldset/CSR1: description: RCC control/status register 1 fields: - name: LSEON description: "LSE oscillator enable\r Set and cleared by software to enable LSE oscillator:" bit_offset: 0 bit_size: 1 - name: LSERDY description: "LSE oscillator ready\r Set and cleared by hardware to indicate when the external 32 kHz oscillator is ready (stable):\r After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles." bit_offset: 1 bit_size: 1 - name: LSEBYP description: "LSE oscillator bypass\r Set and cleared by software to bypass the LSE oscillator (in debug mode).\r This bit can be written only when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0)." bit_offset: 2 bit_size: 1 - name: LSEDRV description: "LSE oscillator drive capability\r Set by software to select the LSE oscillator drive capability as follows:\r Applicable when the LSE oscillator is in Xtal mode, as opposed to bypass mode." bit_offset: 3 bit_size: 2 enum: LSEDRV - name: LSECSSON description: "CSS on LSE enable\r Set by software to enable the clock security system on LSE (32 kHz) oscillator as follows:\r LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.\r Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD\r =1). In that case the software must disable the LSECSSON bit." bit_offset: 5 bit_size: 1 - name: LSECSSD description: "CSS on LSE failure Detection\r Set by hardware to indicate when a failure is detected by the clock security system\r on the external 32 kHz oscillator (LSE):" bit_offset: 6 bit_size: 1 - name: RTCSEL description: "RTC clock source selection\r Set by software to select the clock source for the RTC as follows:\r Once the RTC clock source is selected, it cannot be changed anymore unless the RTC domain is reset, or unless a failure is detected on LSE (LSECSSD is set). The RTCRST bit can be used to reset this bitfield to 00." bit_offset: 8 bit_size: 2 enum: RTCSEL - name: RTCEN description: "RTC clock enable\r Set and cleared by software. The bit enables clock to RTC and TAMP." bit_offset: 15 bit_size: 1 - name: RTCRST description: "RTC domain software reset\r Set and cleared by software to reset the RTC domain:" bit_offset: 16 bit_size: 1 - name: LSCOEN description: "Low-speed clock output (LSCO) enable\r Set and cleared by software." bit_offset: 24 bit_size: 1 - name: LSCOSEL description: "Low-speed clock output selection\r Set and cleared by software to select the low-speed output clock:" bit_offset: 25 bit_size: 1 enum: LSCOSEL fieldset/CSR2: description: RCC control/status register 2 fields: - name: LSION description: "LSI oscillator enable\r Set and cleared by software to enable/disable the LSI oscillator:" bit_offset: 0 bit_size: 1 - name: LSIRDY description: "LSI oscillator ready\r Set and cleared by hardware to indicate when the LSI oscillator is ready (stable):\r After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if LSION = 0 if the LSI is requested by the Clock Security System on LSE, by the Independent Watchdog or by the RTC." bit_offset: 1 bit_size: 1 - name: RMVF description: "Remove reset flags\r Set by software to clear the reset flags." bit_offset: 23 bit_size: 1 - name: OBLRSTF description: "Option byte loader reset flag\r Set by hardware when a reset from the Option byte loading occurs.\r Cleared by setting the RMVF bit." bit_offset: 25 bit_size: 1 - name: PINRSTF description: "Pin reset flag\r Set by hardware when a reset from the NRST pin occurs.\r Cleared by setting the RMVF bit." bit_offset: 26 bit_size: 1 - name: PWRRSTF description: "BOR or POR/PDR flag\r Set by hardware when a BOR or POR/PDR occurs.\r Cleared by setting the RMVF bit." bit_offset: 27 bit_size: 1 - name: SFTRSTF description: "Software reset flag\r Set by hardware when a software reset occurs.\r Cleared by setting the RMVF bit." bit_offset: 28 bit_size: 1 - name: IWDGRSTF description: "Independent window watchdog reset flag\r Set by hardware when an independent watchdog reset domain occurs.\r Cleared by setting the RMVF bit." bit_offset: 29 bit_size: 1 - name: WWDGRSTF description: "Window watchdog reset flag\r Set by hardware when a window watchdog reset occurs.\r Cleared by setting the RMVF bit." bit_offset: 30 bit_size: 1 - name: LPWRRSTF description: "Low-power reset flag\r Set by hardware when a reset occurs due to illegal Stop, or Standby, or Shutdown mode entry.\r Cleared by setting the RMVF bit.\r This operates only if nRST_STOP, or nRST_STDBY or nRST_SHDW option bits are cleared." bit_offset: 31 bit_size: 1 fieldset/GPIOENR: description: RCC I/O port clock enable register fields: - name: GPIOAEN description: "I/O port A clock enable\r This bit is set and cleared by software." bit_offset: 0 bit_size: 1 - name: GPIOBEN description: "I/O port B clock enable\r This bit is set and cleared by software." bit_offset: 1 bit_size: 1 - name: GPIOCEN description: "I/O port C clock enable\r This bit is set and cleared by software." bit_offset: 2 bit_size: 1 - name: GPIODEN description: "I/O port D clock enable\r This bit is set and cleared by software." bit_offset: 3 bit_size: 1 - name: GPIOFEN description: "I/O port F clock enable\r This bit is set and cleared by software." bit_offset: 5 bit_size: 1 fieldset/GPIORSTR: description: RCC I/O port reset register fields: - name: GPIOARST description: "I/O port A reset\r This bit is set and cleared by software." bit_offset: 0 bit_size: 1 - name: GPIOBRST description: "I/O port B reset\r This bit is set and cleared by software." bit_offset: 1 bit_size: 1 - name: GPIOCRST description: "I/O port C reset\r This bit is set and cleared by software." bit_offset: 2 bit_size: 1 - name: GPIODRST description: "I/O port D reset\r This bit is set and cleared by software." bit_offset: 3 bit_size: 1 - name: GPIOFRST description: "I/O port F reset\r This bit is set and cleared by software." bit_offset: 5 bit_size: 1 fieldset/GPIOSMENR: description: RCC I/O port in Sleep mode clock enable register fields: - name: GPIOASMEN description: "I/O port A clock enable during Sleep mode\r Set and cleared by software." bit_offset: 0 bit_size: 1 - name: GPIOBSMEN description: "I/O port B clock enable during Sleep mode\r Set and cleared by software." bit_offset: 1 bit_size: 1 - name: GPIOCSMEN description: "I/O port C clock enable during Sleep mode\r Set and cleared by software." bit_offset: 2 bit_size: 1 - name: GPIODSMEN description: "I/O port D clock enable during Sleep mode\r Set and cleared by software." bit_offset: 3 bit_size: 1 - name: GPIOFSMEN description: "I/O port F clock enable during Sleep mode\r Set and cleared by software." bit_offset: 5 bit_size: 1 fieldset/ICSCR: description: RCC internal clock source calibration register fields: - name: HSICAL description: "HSI clock calibration\r This bitfield directly acts on the HSI clock frequency. Its value is a sum of an internal factory-programmed number and the value of the HSITRIM[6:0] bitfield. In the factory, the internal number is set to calibrate the HSI clock frequency to 48 MHz (with HSITRIM[6:0] left at its reset value). Refer to the device datasheet for HSI calibration accuracy and for the frequency trimming granularity.\r Note: The trimming effect presents discontinuities at HSICAL[7:0] multiples of 64." bit_offset: 0 bit_size: 8 - name: HSITRIM description: "HSI clock trimming\r The value of this bitfield contributes to the HSICAL[7:0] bitfield value.\r It allows HSI clock frequency user trimming.\r The HSI frequency accuracy as stated in the device datasheet applies when this bitfield is left at its reset value." bit_offset: 8 bit_size: 7 enum/ADCSEL: bit_size: 2 variants: - name: SYS description: System clock value: 0 - name: HSI description: HSIKER value: 2 enum/HPRE: bit_size: 4 variants: - name: Div1 description: SYSCLK not divided value: 0 - name: Div2 description: SYSCLK is divided by 2 value: 8 - name: Div4 description: SYSCLK is divided by 4 value: 9 - name: Div8 description: SYSCLK is divided by 8 value: 10 - name: Div16 description: SYSCLK is divided by 16 value: 11 - name: Div64 description: SYSCLK is divided by 64 value: 12 - name: Div128 description: SYSCLK is divided by 128 value: 13 - name: Div256 description: SYSCLK is divided by 256 value: 14 - name: Div512 description: SYSCLK is divided by 512 value: 15 enum/HSIDIV: bit_size: 3 variants: - name: Div1 description: HSI clock is not divided value: 0 - name: Div2 description: HSI clock is divided by 2 value: 1 - name: Div4 description: HSI clock is divided by 4 value: 2 - name: Div8 description: HSI clock is divided by 8 value: 3 - name: Div16 description: HSI clock is divided by 16 value: 4 - name: Div32 description: HSI clock is divided by 32 value: 5 - name: Div64 description: HSI clock is divided by 64 value: 6 - name: Div128 description: HSI clock is divided by 128 value: 7 enum/HSIKERDIV: bit_size: 3 variants: - name: Div1 description: '1' value: 0 - name: Div2 description: '2' value: 1 - name: Div3 description: 3 (reset value) value: 2 - name: Div4 description: '4' value: 3 - name: Div5 description: '5' value: 4 - name: Div6 description: '6' value: 5 - name: Div7 description: '7' value: 6 - name: Div8 description: '8' value: 7 enum/I2C1SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK value: 0 - name: SYS description: SYSCLK value: 1 - name: HSI description: HSIKER value: 2 enum/I2S1SEL: bit_size: 2 variants: - name: SYS description: SYSCLK value: 0 - name: HSI description: HSIKER value: 2 - name: I2S_CKIN description: I2S_CKIN value: 3 enum/LSCOSEL: bit_size: 1 variants: - name: LSI description: LSI value: 0 - name: LSE description: LSE value: 1 enum/LSEDRV: bit_size: 2 variants: - name: Low description: Low driving capability value: 0 - name: MediumLow description: Medium low driving capability value: 1 - name: MediumHigh description: Medium high driving capability value: 2 - name: High description: High driving capability value: 3 enum/MCOPRE: bit_size: 4 variants: - name: Div1 description: MCO2 not divided value: 0 - name: Div2 description: MCO clock is divided by 2 value: 1 - name: Div4 description: MCO clock is divided by 4 value: 2 - name: Div8 description: MCO clock is divided by 8 value: 3 - name: Div16 description: MCO clock is divided divided by 16 value: 4 - name: Div32 description: MCO clock is divided divided by 32 value: 5 - name: Div64 description: MCO clock is divided divided by 64 value: 6 - name: Div128 description: MCO clock is divided divided by 128 value: 7 enum/MCOSEL: bit_size: 4 variants: - name: DISABLE description: No clock, MCO output disabled value: 0 - name: SYS description: SYSCLK selected as MCO source value: 1 - name: HSI description: HSI selected as MCO source value: 3 - name: HSE description: HSE selected as MCO source value: 4 - name: LSI description: LSI selected as MCO source value: 6 - name: LSE description: LSE selected as MCO source value: 7 enum/PPRE: bit_size: 3 variants: - name: Div1 description: HCLK not divided value: 0 - name: Div2 description: HCLK is divided by 2 value: 4 - name: Div4 description: HCLK is divided by 4 value: 5 - name: Div8 description: HCLK is divided by 8 value: 6 - name: Div16 description: HCLK is divided by 16 value: 7 enum/RTCSEL: bit_size: 2 variants: - name: DISABLE description: No clock used as RTC clock value: 0 - name: LSE description: LSE used as RTC clock value: 1 - name: LSI description: LSI used as RTC clock value: 2 - name: HSE_Div32 description: HSE divided by 32 used as RTC clock value: 3 enum/SW: bit_size: 3 variants: - name: HSI description: HSI selected as system clock value: 0 - name: HSE description: HSE selected as system clock value: 1 - name: LSI description: LSI selected as system clock value: 3 - name: LSE description: LSE selected as system clock value: 4 enum/SYSDIV: bit_size: 3 variants: - name: Div1 description: '1' value: 0 - name: Div2 description: '2' value: 1 - name: Div3 description: 3 (reset value) value: 2 - name: Div4 description: '4' value: 3 - name: Div5 description: '5' value: 4 - name: Div6 description: '6' value: 5 - name: Div7 description: '7' value: 6 - name: Div8 description: '8' value: 7 enum/USART1SEL: bit_size: 2 variants: - name: PCLK1 description: PCLK value: 0 - name: SYS description: SYSCLK value: 1 - name: HSI description: HSIKER value: 2 - name: LSE description: LSE value: 3