block/DBGMCU: description: Microcontroller debug unit items: - name: IDCODE description: identity code register byte_offset: 0 fieldset: IDCODE - name: CR description: status and configuration register byte_offset: 4 fieldset: CR - name: APB1LFZR description: APB1L peripheral freeze register byte_offset: 8 fieldset: APB1LFZR - name: APB1HFZR description: APB1H peripheral freeze register byte_offset: 12 fieldset: APB1HFZR - name: APB2FZR description: APB2 peripheral freeze register byte_offset: 16 fieldset: APB2FZR - name: APB7FZR description: APB7 peripheral freeze register byte_offset: 36 fieldset: APB7FZR - name: AHB1FZR description: AHB1 peripheral freeze register byte_offset: 40 fieldset: AHB1FZR - name: SR description: status register byte_offset: 252 fieldset: SR - name: DBG_AUTH_HOST description: debug host authentication register byte_offset: 256 fieldset: DBG_AUTH_HOST - name: DBG_AUTH_DEVICE description: debug device authentication register byte_offset: 260 fieldset: DBG_AUTH_DEVICE - name: PNCR description: part number codification register byte_offset: 2012 fieldset: PNCR - name: PIDR4 description: CoreSight peripheral identity register 4 byte_offset: 4048 fieldset: PIDR4 - name: PIDR0 description: CoreSight peripheral identity register 0 byte_offset: 4064 fieldset: PIDR0 - name: PIDR1 description: CoreSight peripheral identity register 1 byte_offset: 4068 fieldset: PIDR1 - name: PIDR2 description: CoreSight peripheral identity register 2 byte_offset: 4072 fieldset: PIDR2 - name: PIDR3 description: CoreSight peripheral identity register 3 byte_offset: 4076 fieldset: PIDR3 - name: CIDR0 description: CoreSight component identity register 0 byte_offset: 4080 fieldset: CIDR0 - name: CIDR1 description: CoreSight peripheral identity register 1 byte_offset: 4084 fieldset: CIDR1 - name: CIDR2 description: CoreSight component identity register 2 byte_offset: 4088 fieldset: CIDR2 - name: CIDR3 description: CoreSight component identity register 3 byte_offset: 4092 fieldset: CIDR3 fieldset/AHB1FZR: description: AHB1 peripheral freeze register fields: - name: DBG_GPDMA1_CH0_STOP description: "GPDMA 1 channel 0 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC0." bit_offset: 0 bit_size: 1 - name: DBG_GPDMA1_CH1_STOP description: "GPDMA 1 channel 1 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC1." bit_offset: 1 bit_size: 1 - name: DBG_GPDMA1_CH2_STOP description: "GPDMA 1 channel 2 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC2." bit_offset: 2 bit_size: 1 - name: DBG_GPDMA1_CH3_STOP description: "GPDMA 1 channel 3 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC3." bit_offset: 3 bit_size: 1 - name: DBG_GPDMA1_CH4_STOP description: "GPDMA 1 channel 4 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC4." bit_offset: 4 bit_size: 1 - name: DBG_GPDMA1_CH5_STOP description: "GPDMA 1 channel 5 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC5." bit_offset: 5 bit_size: 1 - name: DBG_GPDMA1_CH6_STOP description: "GPDMA 1 channel 6 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC6." bit_offset: 6 bit_size: 1 - name: DBG_GPDMA1_CH7_STOP description: "GPDMA 1 channel 7 stop in CPU debug\r Write access can be protected by GPDMA_SECCFGR.SEC7." bit_offset: 7 bit_size: 1 fieldset/APB1HFZR: description: APB1H peripheral freeze register fields: - name: DBG_LPTIM2_STOP description: "LPTIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.LPTIM2SEC." bit_offset: 5 bit_size: 1 fieldset/APB1LFZR: description: APB1L peripheral freeze register fields: - name: DBG_TIM2_STOP description: "TIM2 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM2SEC." bit_offset: 0 bit_size: 1 - name: DBG_TIM3_STOP description: "TIM3 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM3SEC." bit_offset: 1 bit_size: 1 - name: DBG_WWDG_STOP description: "WWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.WWDGSEC" bit_offset: 11 bit_size: 1 - name: DBG_IWDG_STOP description: "IWDG stop in CPU debug\r Write access can be protected by GTZC_TZSC.IWDGSEC." bit_offset: 12 bit_size: 1 - name: DBG_I2C1_STOP description: "I2C1 SMBUS timeout stop in CPU debug\r Write access can be protected by GTZC_TZSC.I2C1SEC." bit_offset: 21 bit_size: 1 fieldset/APB2FZR: description: APB2 peripheral freeze register fields: - name: DBG_TIM1_STOP description: "TIM1 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM1SEC." bit_offset: 11 bit_size: 1 - name: DBG_TIM16_STOP description: "TIM16 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM16SEC." bit_offset: 17 bit_size: 1 - name: DBG_TIM17_STOP description: "TIM17 stop in CPU debug\r Write access can be protected by GTZC_TZSC.TIM17SEC." bit_offset: 18 bit_size: 1 fieldset/APB7FZR: description: APB7 peripheral freeze register fields: - name: DBG_I2C3_STOP description: "I2C3 stop in CPU debug\r Access can be protected by GTZC_TZSC.I2C3SEC." bit_offset: 10 bit_size: 1 - name: DBG_LPTIM1_STOP description: "LPTIM1 stop in CPU debug\r Access can be protected by GTZC_TZSC.LPTIM1SEC." bit_offset: 17 bit_size: 1 - name: DBG_RTC_STOP description: "RTC stop in CPU debug\r Access can be protected by GTZC_TZSC.TIM17SEC.\r Can only be accessed secure when one or more features in the RTC or TAMP is/are secure." bit_offset: 30 bit_size: 1 fieldset/CIDR0: description: CoreSight component identity register 0 fields: - name: PREAMBLE description: Component ID bits [7:0] bit_offset: 0 bit_size: 8 fieldset/CIDR1: description: CoreSight peripheral identity register 1 fields: - name: PREAMBLE description: Component ID bits [11:8] bit_offset: 0 bit_size: 4 - name: CLASS description: Component ID bits [15:12] - component class bit_offset: 4 bit_size: 4 fieldset/CIDR2: description: CoreSight component identity register 2 fields: - name: PREAMBLE description: Component ID bits [23:16] bit_offset: 0 bit_size: 8 fieldset/CIDR3: description: CoreSight component identity register 3 fields: - name: PREAMBLE description: Component ID bits [31:24] bit_offset: 0 bit_size: 8 fieldset/CR: description: status and configuration register fields: - name: DBG_STOP description: "Allows debug in Stop mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillators is used as system clock during Stop debug mode, allowing CPU debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state." bit_offset: 1 bit_size: 1 - name: DBG_STANDBY description: "Allows debug in Standby mode\r Write access can be protected by PWR_SECCFGR.LPMSEC.\r The CPU debug and clocks remain active and the HSI16 oscillator is used as system clock, the supply and SRAM memory content is maintained during Standby debug mode, allowing CPU debug capability. On exit from Standby mode, a standby reset is performed." bit_offset: 2 bit_size: 1 - name: LPMS description: "Device low power mode selected\r 10x: Standby mode\r others reserved" bit_offset: 16 bit_size: 3 - name: STOPF description: Device Stop flag bit_offset: 19 bit_size: 1 - name: SBF description: Device Standby flag bit_offset: 20 bit_size: 1 - name: CS description: CPU Sleep bit_offset: 24 bit_size: 1 - name: CDS description: CPU DeepSleep bit_offset: 25 bit_size: 1 fieldset/DBG_AUTH_DEVICE: description: debug device authentication register fields: - name: AUTH_ID description: "Device specific ID\r Device specific ID used for RDP regression." bit_offset: 0 bit_size: 32 fieldset/DBG_AUTH_HOST: description: debug host authentication register fields: - name: AUTH_KEY description: "Device authentication key\r The device specific 64-bit authentication key (OEMn key) must be written to this register (in two successive 32-bit writes, least significant word first) to permit RDP regression. Writing a wrong key locks access to the device and prevent code execution from the Flash memory." bit_offset: 0 bit_size: 32 fieldset/IDCODE: description: identity code register fields: - name: DEV_ID description: Device ID bit_offset: 0 bit_size: 12 - name: REV_ID description: Revision ID bit_offset: 16 bit_size: 16 fieldset/PIDR0: description: CoreSight peripheral identity register 0 fields: - name: PARTNUM description: Part number bits [7:0] bit_offset: 0 bit_size: 8 fieldset/PIDR1: description: CoreSight peripheral identity register 1 fields: - name: PARTNUM description: Part number bits [11:8] bit_offset: 0 bit_size: 4 - name: JEP106ID description: JEP106 identity code bits [3:0] bit_offset: 4 bit_size: 4 fieldset/PIDR2: description: CoreSight peripheral identity register 2 fields: - name: JEP106ID description: JEP106 identity code bits [6:4] bit_offset: 0 bit_size: 3 - name: JEDEC description: JEDEC assigned value bit_offset: 3 bit_size: 1 - name: REVISION description: Component revision number bit_offset: 4 bit_size: 4 fieldset/PIDR3: description: CoreSight peripheral identity register 3 fields: - name: CMOD description: Customer modified bit_offset: 0 bit_size: 4 - name: REVAND description: Metal fix version bit_offset: 4 bit_size: 4 fieldset/PIDR4: description: CoreSight peripheral identity register 4 fields: - name: JEP106CON description: JEP106 continuation code bit_offset: 0 bit_size: 4 - name: F4KCOUNT description: Register file size bit_offset: 4 bit_size: 4 fieldset/PNCR: description: part number codification register fields: - name: CODIFICATION description: Part number codification bit_offset: 0 bit_size: 32 fieldset/SR: description: status register fields: - name: AP_PRESENT description: "Bit n identifies whether access port APn is present in device \r Bit n�=�0: APn absent \r Bit n�=�1: APn present" bit_offset: 0 bit_size: 16 - name: AP_ENABLED description: "Bit n identifies whether access port APn is open (can be accessed via the debug port) or locked (debug access to the APn is blocked, except for access) \r Bit n�=�0: APn locked (except for access to DBGMCU)\r Bit n�=�1: APn enabled" bit_offset: 16 bit_size: 16