---
block/FLASH:
  description: Flash
  items:
  - byte_offset: 0
    description: Access control register
    fieldset: ACR
    name: ACR
  - access: Write
    byte_offset: 8
    description: Flash key register
    fieldset: KEYR
    name: KEYR
  - access: Write
    byte_offset: 12
    description: Option byte key register
    fieldset: OPTKEYR
    name: OPTKEYR
  - byte_offset: 16
    description: Status register
    fieldset: SR
    name: SR
  - byte_offset: 20
    description: Flash control register
    fieldset: CR
    name: CR
  - byte_offset: 24
    description: Flash ECC register
    fieldset: ECCR
    name: ECCR
  - byte_offset: 32
    description: Flash option register
    fieldset: OPTR
    name: OPTR
  - byte_offset: 36
    description: Flash Bank 1 PCROP Start address zone A register
    fieldset: PCROP1ASR
    name: PCROP1ASR
  - byte_offset: 40
    description: Flash Bank 1 PCROP End address zone A register
    fieldset: PCROP1AER
    name: PCROP1AER
  - byte_offset: 44
    description: Flash Bank 1 WRP area A address register
    fieldset: WRP1AR
    name: WRP1AR
  - byte_offset: 48
    description: Flash Bank 1 WRP area B address register
    fieldset: WRP1BR
    name: WRP1BR
  - byte_offset: 52
    description: Flash Bank 1 PCROP Start address area B register
    fieldset: PCROP1BSR
    name: PCROP1BSR
  - byte_offset: 56
    description: Flash Bank 1 PCROP End address area B register
    fieldset: PCROP1BER
    name: PCROP1BER
  - byte_offset: 60
    description: IPCC mailbox data buffer address register
    fieldset: IPCCBR
    name: IPCCBR
  - byte_offset: 92
    description: CPU2 cortex M0 access control register
    fieldset: C2ACR
    name: C2ACR
  - byte_offset: 96
    description: CPU2 cortex M0 status register
    fieldset: C2SR
    name: C2SR
  - byte_offset: 100
    description: CPU2 cortex M0 control register
    fieldset: C2CR
    name: C2CR
  - byte_offset: 128
    description: Secure flash start address register
    fieldset: SFR
    name: SFR
  - byte_offset: 132
    description: Secure SRAM2 start address and cortex M0 reset vector register
    fieldset: SRRVR
    name: SRRVR
fieldset/ACR:
  description: Access control register
  fields:
  - bit_offset: 0
    bit_size: 3
    description: Latency
    name: LATENCY
  - bit_offset: 8
    bit_size: 1
    description: Prefetch enable
    name: PRFTEN
  - bit_offset: 9
    bit_size: 1
    description: Instruction cache enable
    name: ICEN
  - bit_offset: 10
    bit_size: 1
    description: Data cache enable
    name: DCEN
  - bit_offset: 11
    bit_size: 1
    description: Instruction cache reset
    name: ICRST
  - bit_offset: 12
    bit_size: 1
    description: Data cache reset
    name: DCRST
  - bit_offset: 15
    bit_size: 1
    description: CPU1 CortexM4 program erase suspend request
    name: PES
  - bit_offset: 16
    bit_size: 1
    description: Flash User area empty
    name: EMPTY
fieldset/C2ACR:
  description: CPU2 cortex M0 access control register
  fields:
  - bit_offset: 8
    bit_size: 1
    description: CPU2 cortex M0 prefetch enable
    name: PRFTEN
  - bit_offset: 9
    bit_size: 1
    description: CPU2 cortex M0 instruction cache enable
    name: ICEN
  - bit_offset: 11
    bit_size: 1
    description: CPU2 cortex M0 instruction cache reset
    name: ICRST
  - bit_offset: 15
    bit_size: 1
    description: CPU2 cortex M0 program erase suspend request
    name: PES
fieldset/C2CR:
  description: CPU2 cortex M0 control register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Programming
    name: PG
  - bit_offset: 1
    bit_size: 1
    description: Page erase
    name: PER
  - bit_offset: 2
    bit_size: 1
    description: Masse erase
    name: MER
  - bit_offset: 3
    bit_size: 8
    description: Page Number selection
    name: PNB
  - bit_offset: 16
    bit_size: 1
    description: Start
    name: STRT
  - bit_offset: 18
    bit_size: 1
    description: Fast programming
    name: FSTPG
  - bit_offset: 24
    bit_size: 1
    description: End of operation interrupt enable
    name: EOPIE
  - bit_offset: 25
    bit_size: 1
    description: Error interrupt enable
    name: ERRIE
  - bit_offset: 26
    bit_size: 1
    description: PCROP read error interrupt enable
    name: RDERRIE
fieldset/C2SR:
  description: CPU2 cortex M0 status register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: End of operation
    name: EOP
  - bit_offset: 1
    bit_size: 1
    description: Operation error
    name: OPERR
  - bit_offset: 3
    bit_size: 1
    description: Programming error
    name: PROGERR
  - bit_offset: 4
    bit_size: 1
    description: write protection error
    name: WRPERR
  - bit_offset: 5
    bit_size: 1
    description: Programming alignment error
    name: PGAERR
  - bit_offset: 6
    bit_size: 1
    description: Size error
    name: SIZERR
  - bit_offset: 7
    bit_size: 1
    description: Programming sequence error
    name: PGSERR
  - bit_offset: 8
    bit_size: 1
    description: Fast programming data miss error
    name: MISSERR
  - bit_offset: 9
    bit_size: 1
    description: Fast programming error
    name: FASTERR
  - bit_offset: 14
    bit_size: 1
    description: PCROP read error
    name: RDERR
  - bit_offset: 16
    bit_size: 1
    description: Busy
    name: BSY
  - bit_offset: 18
    bit_size: 1
    description: Programming or erase configuration busy
    name: CFGBSY
  - bit_offset: 19
    bit_size: 1
    description: Programming or erase operation suspended
    name: PESD
fieldset/CR:
  description: Flash control register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: Programming
    name: PG
  - bit_offset: 1
    bit_size: 1
    description: Page erase
    name: PER
  - bit_offset: 2
    bit_size: 1
    description: This bit triggers the mass erase (all user pages) when set
    name: MER
  - bit_offset: 3
    bit_size: 8
    description: Page number selection
    name: PNB
  - bit_offset: 16
    bit_size: 1
    description: Start
    name: STRT
  - bit_offset: 17
    bit_size: 1
    description: Options modification start
    name: OPTSTRT
  - bit_offset: 18
    bit_size: 1
    description: Fast programming
    name: FSTPG
  - bit_offset: 24
    bit_size: 1
    description: End of operation interrupt enable
    name: EOPIE
  - bit_offset: 25
    bit_size: 1
    description: Error interrupt enable
    name: ERRIE
  - bit_offset: 26
    bit_size: 1
    description: PCROP read error interrupt enable
    name: RDERRIE
  - bit_offset: 27
    bit_size: 1
    description: Force the option byte loading
    name: OBL_LAUNCH
  - bit_offset: 30
    bit_size: 1
    description: Options Lock
    name: OPTLOCK
  - bit_offset: 31
    bit_size: 1
    description: FLASH_CR Lock
    name: LOCK
fieldset/ECCR:
  description: Flash ECC register
  fields:
  - bit_offset: 0
    bit_size: 17
    description: ECC fail address
    name: ADDR_ECC
  - bit_offset: 20
    bit_size: 1
    description: System Flash ECC fail
    name: SYSF_ECC
  - bit_offset: 24
    bit_size: 1
    description: ECC correction interrupt enable
    name: ECCCIE
  - bit_offset: 26
    bit_size: 3
    description: CPU identification
    name: CPUID
  - bit_offset: 30
    bit_size: 1
    description: ECC correction
    name: ECCC
  - bit_offset: 31
    bit_size: 1
    description: ECC detection
    name: ECCD
fieldset/IPCCBR:
  description: IPCC mailbox data buffer address register
  fields:
  - bit_offset: 0
    bit_size: 14
    description: PCC mailbox data buffer base address
    name: IPCCDBA
fieldset/KEYR:
  description: Flash key register
  fields:
  - bit_offset: 0
    bit_size: 32
    description: KEYR
    name: KEYR
fieldset/OPTKEYR:
  description: Option byte key register
  fields:
  - bit_offset: 0
    bit_size: 32
    description: Option byte key
    name: OPTKEYR
fieldset/OPTR:
  description: Flash option register
  fields:
  - bit_offset: 0
    bit_size: 8
    description: Read protection level
    name: RDP
  - bit_offset: 8
    bit_size: 1
    description: Security enabled
    name: ESE
  - bit_offset: 9
    bit_size: 3
    description: BOR reset Level
    name: BOR_LEV
  - bit_offset: 12
    bit_size: 1
    description: nRST_STOP
    name: nRST_STOP
  - bit_offset: 13
    bit_size: 1
    description: nRST_STDBY
    name: nRST_STDBY
  - bit_offset: 14
    bit_size: 1
    description: nRST_SHDW
    name: nRST_SHDW
  - bit_offset: 16
    bit_size: 1
    description: Independent watchdog selection
    name: IDWG_SW
  - bit_offset: 17
    bit_size: 1
    description: Independent watchdog counter freeze in Stop mode
    name: IWDG_STOP
  - bit_offset: 18
    bit_size: 1
    description: Independent watchdog counter freeze in Standby mode
    name: IWDG_STDBY
  - bit_offset: 19
    bit_size: 1
    description: Window watchdog selection
    name: WWDG_SW
  - bit_offset: 23
    bit_size: 1
    description: Boot configuration
    name: nBOOT1
  - bit_offset: 24
    bit_size: 1
    description: SRAM2 parity check enable
    name: SRAM2_PE
  - bit_offset: 25
    bit_size: 1
    description: SRAM2 Erase when system reset
    name: SRAM2_RST
  - bit_offset: 26
    bit_size: 1
    description: Software Boot0
    name: nSWBOOT0
  - bit_offset: 27
    bit_size: 1
    description: nBoot0 option bit
    name: nBOOT0
  - bit_offset: 29
    bit_size: 3
    description: Radio Automatic Gain Control Trimming
    name: AGC_TRIM
fieldset/PCROP1AER:
  description: Flash Bank 1 PCROP End address zone A register
  fields:
  - bit_offset: 0
    bit_size: 9
    description: Bank 1 PCROP area end offset
    name: PCROP1A_END
  - bit_offset: 31
    bit_size: 1
    description: PCROP area preserved when RDP level decreased
    name: PCROP_RDP
fieldset/PCROP1ASR:
  description: Flash Bank 1 PCROP Start address zone A register
  fields:
  - bit_offset: 0
    bit_size: 9
    description: Bank 1 PCROPQ area start offset
    name: PCROP1A_STRT
fieldset/PCROP1BER:
  description: Flash Bank 1 PCROP End address area B register
  fields:
  - bit_offset: 0
    bit_size: 9
    description: Bank 1 PCROP area end area B offset
    name: PCROP1B_END
fieldset/PCROP1BSR:
  description: Flash Bank 1 PCROP Start address area B register
  fields:
  - bit_offset: 0
    bit_size: 9
    description: Bank 1 PCROP area B start offset
    name: PCROP1B_STRT
fieldset/SFR:
  description: Secure flash start address register
  fields:
  - bit_offset: 0
    bit_size: 8
    description: Secure flash start address
    name: SFSA
  - bit_offset: 8
    bit_size: 1
    description: Flash security disable
    name: FSD
  - bit_offset: 12
    bit_size: 1
    description: Disable Cortex M0 debug access
    name: DDS
fieldset/SR:
  description: Status register
  fields:
  - bit_offset: 0
    bit_size: 1
    description: End of operation
    name: EOP
  - bit_offset: 1
    bit_size: 1
    description: Operation error
    name: OPERR
  - bit_offset: 3
    bit_size: 1
    description: Programming error
    name: PROGERR
  - bit_offset: 4
    bit_size: 1
    description: Write protected error
    name: WRPERR
  - bit_offset: 5
    bit_size: 1
    description: Programming alignment error
    name: PGAERR
  - bit_offset: 6
    bit_size: 1
    description: Size error
    name: SIZERR
  - bit_offset: 7
    bit_size: 1
    description: Programming sequence error
    name: PGSERR
  - bit_offset: 8
    bit_size: 1
    description: Fast programming data miss error
    name: MISERR
  - bit_offset: 9
    bit_size: 1
    description: Fast programming error
    name: FASTERR
  - bit_offset: 13
    bit_size: 1
    description: User Option OPTVAL indication
    name: OPTNV
  - bit_offset: 14
    bit_size: 1
    description: PCROP read error
    name: RDERR
  - bit_offset: 15
    bit_size: 1
    description: Option validity error
    name: OPTVERR
  - bit_offset: 16
    bit_size: 1
    description: Busy
    name: BSY
  - bit_offset: 18
    bit_size: 1
    description: Programming or erase configuration busy
    name: CFGBSY
  - bit_offset: 19
    bit_size: 1
    description: Programming or erase operation suspended
    name: PESD
fieldset/SRRVR:
  description: Secure SRAM2 start address and cortex M0 reset vector register
  fields:
  - bit_offset: 0
    bit_size: 18
    description: cortex M0 access control register
    name: SBRV
  - bit_offset: 18
    bit_size: 5
    description: Secure backup SRAM2a start address
    name: SBRSA
  - bit_offset: 23
    bit_size: 1
    description: backup SRAM2a security disable
    name: BRSD
  - bit_offset: 25
    bit_size: 5
    description: Secure non backup SRAM2a start address
    name: SNBRSA
  - bit_offset: 30
    bit_size: 1
    description: non-backup SRAM2b security disable
    name: NBRSD
  - bit_offset: 31
    bit_size: 1
    description: CPU2 cortex M0 boot reset vector memory selection
    name: C2OPT
fieldset/WRP1AR:
  description: Flash Bank 1 WRP area A address register
  fields:
  - bit_offset: 0
    bit_size: 8
    description: Bank 1 WRP first area A start offset
    name: WRP1A_STRT
  - bit_offset: 16
    bit_size: 8
    description: Bank 1 WRP first area A end offset
    name: WRP1A_END
fieldset/WRP1BR:
  description: Flash Bank 1 WRP area B address register
  fields:
  - bit_offset: 0
    bit_size: 8
    description: Bank 1 WRP second area B start offset
    name: WRP1B_END
  - bit_offset: 16
    bit_size: 8
    description: Bank 1 WRP second area B end offset
    name: WRP1B_STRT