PA0: COMP1_OUT: 7 LPTIM1_IN1: 1 LPUART1_RX: 6 TIM2_CH1: 2 TIM2_ETR: 5 USART2_CTS: 4 USART2_RX: 0 PA1: EVENTOUT: 0 I2C1_SMBA: 3 LPTIM1_IN2: 1 LPUART1_TX: 6 TIM21_ETR: 5 TIM2_CH2: 2 USART2_DE: 4 USART2_RTS: 4 PA10: COMP1_OUT: 7 I2C1_SDA: 1 RTC_REFIN: 2 TIM21_CH1: 0 TIM2_CH3: 5 USART2_RX: 4 PA11: COMP1_OUT: 7 EVENTOUT: 2 LPTIM1_OUT: 1 SPI1_MISO: 0 TIM21_CH2: 5 USART2_CTS: 4 PA12: COMP2_OUT: 7 EVENTOUT: 2 SPI1_MOSI: 0 USART2_DE: 4 USART2_RTS: 4 PA13: COMP1_OUT: 7 I2C1_SDA: 3 LPTIM1_ETR: 1 LPUART1_RX: 6 SPI1_SCK: 5 SYS_SWDIO: 0 PA14: COMP2_OUT: 7 I2C1_SMBA: 3 LPTIM1_OUT: 1 LPUART1_TX: 6 SPI1_MISO: 5 SYS_SWCLK: 0 USART2_TX: 4 PA15: EVENTOUT: 3 SPI1_NSS: 0 TIM2_CH1: 5 TIM2_ETR: 2 USART2_RX: 4 PA2: COMP2_OUT: 7 LPUART1_TX: 6 TIM21_CH1: 0 TIM2_CH3: 2 USART2_TX: 4 PA3: LPUART1_RX: 6 TIM21_CH2: 0 TIM2_CH4: 2 USART2_RX: 4 PA4: COMP2_OUT: 7 I2C1_SCL: 3 LPTIM1_ETR: 2 LPTIM1_IN1: 1 LPUART1_TX: 6 SPI1_NSS: 0 TIM2_ETR: 5 USART2_CK: 4 PA5: LPTIM1_IN2: 1 SPI1_SCK: 0 TIM2_CH1: 5 TIM2_ETR: 2 PA6: COMP1_OUT: 7 EVENTOUT: 6 LPTIM1_ETR: 1 LPUART1_CTS: 4 SPI1_MISO: 0 PA7: COMP2_OUT: 7 EVENTOUT: 6 LPTIM1_OUT: 1 SPI1_MOSI: 0 TIM21_ETR: 5 USART2_CTS: 4 PA8: EVENTOUT: 3 LPTIM1_IN1: 2 RCC_MCO: 0 TIM2_CH1: 5 USART2_CK: 4 PA9: COMP1_OUT: 7 I2C1_SCL: 1 LPTIM1_OUT: 2 RCC_MCO: 0 TIM21_CH2: 5 USART2_TX: 4 PB0: EVENTOUT: 0 SPI1_MISO: 1 TIM2_CH2: 2 TIM2_CH3: 5 USART2_DE: 4 USART2_RTS: 4 PB1: LPTIM1_IN1: 2 LPUART1_DE: 4 LPUART1_RTS: 4 SPI1_MOSI: 1 TIM2_CH4: 5 USART2_CK: 0 PB2: LPTIM1_OUT: 2 PB3: EVENTOUT: 4 SPI1_SCK: 0 TIM2_CH2: 2 PB4: EVENTOUT: 2 SPI1_MISO: 0 PB5: I2C1_SMBA: 3 LPTIM1_IN1: 2 SPI1_MOSI: 0 TIM21_CH1: 5 PB6: I2C1_SCL: 1 LPTIM1_ETR: 2 LPUART1_TX: 6 TIM2_CH3: 5 USART2_TX: 0 PB7: I2C1_SDA: 1 LPTIM1_IN2: 2 LPUART1_RX: 6 TIM2_CH4: 5 USART2_RX: 0 PB8: EVENTOUT: 2 I2C1_SCL: 4 SPI1_NSS: 5 USART2_TX: 0 PB9: {} PC13: {} PC14: {} PC15: {} PI8: {}